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authorKhem Raj <raj.khem@gmail.com>2011-12-05 17:04:03 -0800
committerKhem Raj <raj.khem@gmail.com>2011-12-05 18:55:51 -0800
commita3aea9e69ab69dd4b5ac2ad4a602b74f9ef30fa2 (patch)
tree2ac969c53b292839a20f62b3a9795e1fdca6295b /meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99549.patch
parent2378ee8f21741abd23e434260a88c62cb0e151f1 (diff)
downloadmeta-openembedded-a3aea9e69ab69dd4b5ac2ad4a602b74f9ef30fa2.tar.gz
gcc-4.5: Backport with-linker-hash-style and backports from FSF & linaro
backport --with-linker-hash-style from trunk, fix GNU_HASH QA warnings once for all Explicitly disable configuring with cloog/ppl while building gcc if the user has it installed on build box then gcc's configure will try to use it and it can go wrong and create problems since we never built it so Move to tip of FSF gcc-4_5-branch brings in bug fixes PR 50091/ppc 50464/x86 50273/fortran 44473/c++ mangler 49965/sparc 50565/c 50659/fortran 50618/c++ 50737/alpha 50793/c++ 50788/x86/SSE 50691/pa 50875/x86/SSE 50979/sparc 30282/ppc 51187/rtl 50888/bootstrap 48190/debug/QEMUhog Merge fix for LP689887/linaro https://bugs.launchpad.net/gcc-linaro/+bug/689887 Signed-off-by: Khem Raj <raj.khem@gmail.com>
Diffstat (limited to 'meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99549.patch')
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99549.patch460
1 files changed, 460 insertions, 0 deletions
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99549.patch b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99549.patch
new file mode 100644
index 0000000000..43617024a1
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99549.patch
@@ -0,0 +1,460 @@
12011-10-03 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 Backport from mainline:
5
6 2010-12-06 Jakub Jelinek <jakub@redhat.com>
7
8 PR debug/46771
9 * reginfo.c (init_subregs_of_mode): Don't call find_subregs_of_mode
10 on DEBUG_INSNs.
11
122011-10-03 Richard Sandiford <richard.sandiford@linaro.org>
13
14 gcc/
15 Backport from mainline:
16
17 2011-09-22 Richard Sandiford <richard.sandiford@linaro.org>
18
19 * config/arm/predicates.md (expandable_comparison_operator): New
20 predicate, extracted from...
21 (arm_comparison_operator): ...here.
22 * config/arm/arm.md (cbranchsi4, cbranchsf4, cbranchdf4, cbranchdi4)
23 (cstoresi4, cstoresf4, cstoredf4, cstoredi4, movsicc, movsfcc)
24 (movdfcc): Use expandable_comparison_operator.
25
26 gcc/testsuite/
27 Backport from mainline:
28
29 2011-09-22 Richard Sandiford <richard.sandiford@linaro.org>
30
31 * gcc.target/arm/cmp-1.c: New test.
32 * gcc.target/arm/cmp-2.c: Likewise.
33
342011-10-03 Richard Sandiford <richard.sandiford@linaro.org>
35
36 gcc/
37 Backport from mainline:
38
39 2011-09-07 Richard Sandiford <richard.sandiford@linaro.org>
40
41 PR target/49030
42 * config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare.
43 * config/arm/arm.c (maybe_get_arm_condition_code): New function,
44 reusing the old code from get_arm_condition_code. Return ARM_NV
45 for invalid comparison codes.
46 (get_arm_condition_code): Redefine in terms of
47 maybe_get_arm_condition_code.
48 * config/arm/predicates.md (arm_comparison_operator): Use
49 maybe_get_arm_condition_code.
50
51 gcc/testsuite/
52 Backport from mainline:
53
54 2011-09-07 Richard Sandiford <richard.sandiford@linaro.org>
55
56 PR target/49030
57 * gcc.dg/torture/pr49030.c: New test.
58
59=== modified file 'gcc/config/arm/arm-protos.h'
60--- old/gcc/config/arm/arm-protos.h 2011-09-15 10:06:35 +0000
61+++ new/gcc/config/arm/arm-protos.h 2011-10-03 10:09:06 +0000
62@@ -182,6 +182,7 @@
63 #endif
64 extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
65 #ifdef RTX_CODE
66+extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
67 extern void thumb1_final_prescan_insn (rtx);
68 extern void thumb2_final_prescan_insn (rtx);
69 extern const char *thumb_load_double_from_address (rtx *);
70
71=== modified file 'gcc/config/arm/arm.c'
72--- old/gcc/config/arm/arm.c 2011-09-15 10:06:35 +0000
73+++ new/gcc/config/arm/arm.c 2011-10-03 10:09:06 +0000
74@@ -17196,10 +17196,10 @@
75 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
76
77 /* Returns the index of the ARM condition code string in
78- `arm_condition_codes'. COMPARISON should be an rtx like
79- `(eq (...) (...))'. */
80-static enum arm_cond_code
81-get_arm_condition_code (rtx comparison)
82+ `arm_condition_codes', or ARM_NV if the comparison is invalid.
83+ COMPARISON should be an rtx like `(eq (...) (...))'. */
84+enum arm_cond_code
85+maybe_get_arm_condition_code (rtx comparison)
86 {
87 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
88 enum arm_cond_code code;
89@@ -17223,11 +17223,11 @@
90 case CC_DLTUmode: code = ARM_CC;
91
92 dominance:
93- gcc_assert (comp_code == EQ || comp_code == NE);
94-
95 if (comp_code == EQ)
96 return ARM_INVERSE_CONDITION_CODE (code);
97- return code;
98+ if (comp_code == NE)
99+ return code;
100+ return ARM_NV;
101
102 case CC_NOOVmode:
103 switch (comp_code)
104@@ -17236,7 +17236,7 @@
105 case EQ: return ARM_EQ;
106 case GE: return ARM_PL;
107 case LT: return ARM_MI;
108- default: gcc_unreachable ();
109+ default: return ARM_NV;
110 }
111
112 case CC_Zmode:
113@@ -17244,7 +17244,7 @@
114 {
115 case NE: return ARM_NE;
116 case EQ: return ARM_EQ;
117- default: gcc_unreachable ();
118+ default: return ARM_NV;
119 }
120
121 case CC_Nmode:
122@@ -17252,7 +17252,7 @@
123 {
124 case NE: return ARM_MI;
125 case EQ: return ARM_PL;
126- default: gcc_unreachable ();
127+ default: return ARM_NV;
128 }
129
130 case CCFPEmode:
131@@ -17277,7 +17277,7 @@
132 /* UNEQ and LTGT do not have a representation. */
133 case UNEQ: /* Fall through. */
134 case LTGT: /* Fall through. */
135- default: gcc_unreachable ();
136+ default: return ARM_NV;
137 }
138
139 case CC_SWPmode:
140@@ -17293,7 +17293,7 @@
141 case GTU: return ARM_CC;
142 case LEU: return ARM_CS;
143 case LTU: return ARM_HI;
144- default: gcc_unreachable ();
145+ default: return ARM_NV;
146 }
147
148 case CC_Cmode:
149@@ -17301,7 +17301,7 @@
150 {
151 case LTU: return ARM_CS;
152 case GEU: return ARM_CC;
153- default: gcc_unreachable ();
154+ default: return ARM_NV;
155 }
156
157 case CC_CZmode:
158@@ -17313,7 +17313,7 @@
159 case GTU: return ARM_HI;
160 case LEU: return ARM_LS;
161 case LTU: return ARM_CC;
162- default: gcc_unreachable ();
163+ default: return ARM_NV;
164 }
165
166 case CC_NCVmode:
167@@ -17323,7 +17323,7 @@
168 case LT: return ARM_LT;
169 case GEU: return ARM_CS;
170 case LTU: return ARM_CC;
171- default: gcc_unreachable ();
172+ default: return ARM_NV;
173 }
174
175 case CCmode:
176@@ -17339,13 +17339,22 @@
177 case GTU: return ARM_HI;
178 case LEU: return ARM_LS;
179 case LTU: return ARM_CC;
180- default: gcc_unreachable ();
181+ default: return ARM_NV;
182 }
183
184 default: gcc_unreachable ();
185 }
186 }
187
188+/* Like maybe_get_arm_condition_code, but never return ARM_NV. */
189+static enum arm_cond_code
190+get_arm_condition_code (rtx comparison)
191+{
192+ enum arm_cond_code code = maybe_get_arm_condition_code (comparison);
193+ gcc_assert (code != ARM_NV);
194+ return code;
195+}
196+
197 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
198 instructions. */
199 void
200
201=== modified file 'gcc/config/arm/arm.md'
202--- old/gcc/config/arm/arm.md 2011-07-12 16:35:20 +0000
203+++ new/gcc/config/arm/arm.md 2011-10-03 10:09:55 +0000
204@@ -6428,7 +6428,7 @@
205
206 (define_expand "cbranchsi4"
207 [(set (pc) (if_then_else
208- (match_operator 0 "arm_comparison_operator"
209+ (match_operator 0 "expandable_comparison_operator"
210 [(match_operand:SI 1 "s_register_operand" "")
211 (match_operand:SI 2 "nonmemory_operand" "")])
212 (label_ref (match_operand 3 "" ""))
213@@ -6479,7 +6479,7 @@
214
215 (define_expand "cbranchsf4"
216 [(set (pc) (if_then_else
217- (match_operator 0 "arm_comparison_operator"
218+ (match_operator 0 "expandable_comparison_operator"
219 [(match_operand:SF 1 "s_register_operand" "")
220 (match_operand:SF 2 "arm_float_compare_operand" "")])
221 (label_ref (match_operand 3 "" ""))
222@@ -6491,7 +6491,7 @@
223
224 (define_expand "cbranchdf4"
225 [(set (pc) (if_then_else
226- (match_operator 0 "arm_comparison_operator"
227+ (match_operator 0 "expandable_comparison_operator"
228 [(match_operand:DF 1 "s_register_operand" "")
229 (match_operand:DF 2 "arm_float_compare_operand" "")])
230 (label_ref (match_operand 3 "" ""))
231@@ -6503,7 +6503,7 @@
232
233 (define_expand "cbranchdi4"
234 [(set (pc) (if_then_else
235- (match_operator 0 "arm_comparison_operator"
236+ (match_operator 0 "expandable_comparison_operator"
237 [(match_operand:DI 1 "cmpdi_operand" "")
238 (match_operand:DI 2 "cmpdi_operand" "")])
239 (label_ref (match_operand 3 "" ""))
240@@ -7898,7 +7898,7 @@
241
242 (define_expand "cstoresi4"
243 [(set (match_operand:SI 0 "s_register_operand" "")
244- (match_operator:SI 1 "arm_comparison_operator"
245+ (match_operator:SI 1 "expandable_comparison_operator"
246 [(match_operand:SI 2 "s_register_operand" "")
247 (match_operand:SI 3 "reg_or_int_operand" "")]))]
248 "TARGET_32BIT || TARGET_THUMB1"
249@@ -8034,7 +8034,7 @@
250
251 (define_expand "cstoresf4"
252 [(set (match_operand:SI 0 "s_register_operand" "")
253- (match_operator:SI 1 "arm_comparison_operator"
254+ (match_operator:SI 1 "expandable_comparison_operator"
255 [(match_operand:SF 2 "s_register_operand" "")
256 (match_operand:SF 3 "arm_float_compare_operand" "")]))]
257 "TARGET_32BIT && TARGET_HARD_FLOAT"
258@@ -8044,7 +8044,7 @@
259
260 (define_expand "cstoredf4"
261 [(set (match_operand:SI 0 "s_register_operand" "")
262- (match_operator:SI 1 "arm_comparison_operator"
263+ (match_operator:SI 1 "expandable_comparison_operator"
264 [(match_operand:DF 2 "s_register_operand" "")
265 (match_operand:DF 3 "arm_float_compare_operand" "")]))]
266 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
267@@ -8054,7 +8054,7 @@
268
269 (define_expand "cstoredi4"
270 [(set (match_operand:SI 0 "s_register_operand" "")
271- (match_operator:SI 1 "arm_comparison_operator"
272+ (match_operator:SI 1 "expandable_comparison_operator"
273 [(match_operand:DI 2 "cmpdi_operand" "")
274 (match_operand:DI 3 "cmpdi_operand" "")]))]
275 "TARGET_32BIT"
276@@ -8174,7 +8174,7 @@
277
278 (define_expand "movsicc"
279 [(set (match_operand:SI 0 "s_register_operand" "")
280- (if_then_else:SI (match_operand 1 "arm_comparison_operator" "")
281+ (if_then_else:SI (match_operand 1 "expandable_comparison_operator" "")
282 (match_operand:SI 2 "arm_not_operand" "")
283 (match_operand:SI 3 "arm_not_operand" "")))]
284 "TARGET_32BIT"
285@@ -8194,7 +8194,7 @@
286
287 (define_expand "movsfcc"
288 [(set (match_operand:SF 0 "s_register_operand" "")
289- (if_then_else:SF (match_operand 1 "arm_comparison_operator" "")
290+ (if_then_else:SF (match_operand 1 "expandable_comparison_operator" "")
291 (match_operand:SF 2 "s_register_operand" "")
292 (match_operand:SF 3 "nonmemory_operand" "")))]
293 "TARGET_32BIT && TARGET_HARD_FLOAT"
294@@ -8220,7 +8220,7 @@
295
296 (define_expand "movdfcc"
297 [(set (match_operand:DF 0 "s_register_operand" "")
298- (if_then_else:DF (match_operand 1 "arm_comparison_operator" "")
299+ (if_then_else:DF (match_operand 1 "expandable_comparison_operator" "")
300 (match_operand:DF 2 "s_register_operand" "")
301 (match_operand:DF 3 "arm_float_add_operand" "")))]
302 "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
303
304=== modified file 'gcc/config/arm/predicates.md'
305--- old/gcc/config/arm/predicates.md 2011-09-15 10:06:35 +0000
306+++ new/gcc/config/arm/predicates.md 2011-10-03 10:09:55 +0000
307@@ -236,11 +236,15 @@
308
309 ;; True for integer comparisons and, if FP is active, for comparisons
310 ;; other than LTGT or UNEQ.
311+(define_special_predicate "expandable_comparison_operator"
312+ (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
313+ unordered,ordered,unlt,unle,unge,ungt"))
314+
315+;; Likewise, but only accept comparisons that are directly supported
316+;; by ARM condition codes.
317 (define_special_predicate "arm_comparison_operator"
318- (ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu")
319- (and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT
320- && (TARGET_FPA || TARGET_VFP)")
321- (match_code "unordered,ordered,unlt,unle,unge,ungt"))))
322+ (and (match_operand 0 "expandable_comparison_operator")
323+ (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
324
325 (define_special_predicate "lt_ge_comparison_operator"
326 (match_code "lt,ge"))
327
328=== modified file 'gcc/reginfo.c'
329--- old/gcc/reginfo.c 2011-09-15 10:06:35 +0000
330+++ new/gcc/reginfo.c 2011-10-03 10:10:17 +0000
331@@ -1350,7 +1350,7 @@
332
333 FOR_EACH_BB (bb)
334 FOR_BB_INSNS (bb, insn)
335- if (INSN_P (insn))
336+ if (NONDEBUG_INSN_P (insn))
337 find_subregs_of_mode (PATTERN (insn));
338 }
339
340
341=== added file 'gcc/testsuite/gcc.dg/torture/pr49030.c'
342--- old/gcc/testsuite/gcc.dg/torture/pr49030.c 1970-01-01 00:00:00 +0000
343+++ new/gcc/testsuite/gcc.dg/torture/pr49030.c 2011-10-03 10:09:06 +0000
344@@ -0,0 +1,19 @@
345+void
346+sample_move_d32u24_sS (char *dst, float *src, unsigned long nsamples,
347+ unsigned long dst_skip)
348+{
349+ long long y;
350+ while (nsamples--)
351+ {
352+ y = (long long) (*src * 8388608.0f) << 8;
353+ if (y > 2147483647) {
354+ *(int *) dst = 2147483647;
355+ } else if (y < -2147483647 - 1) {
356+ *(int *) dst = -2147483647 - 1;
357+ } else {
358+ *(int *) dst = (int) y;
359+ }
360+ dst += dst_skip;
361+ src++;
362+ }
363+}
364
365=== added file 'gcc/testsuite/gcc.target/arm/cmp-1.c'
366--- old/gcc/testsuite/gcc.target/arm/cmp-1.c 1970-01-01 00:00:00 +0000
367+++ new/gcc/testsuite/gcc.target/arm/cmp-1.c 2011-10-03 10:09:55 +0000
368@@ -0,0 +1,37 @@
369+/* { dg-do compile } */
370+/* { dg-options "-O" } */
371+/* { dg-final { scan-assembler-not "\tbl\t" } } */
372+/* { dg-final { scan-assembler-not "__aeabi" } } */
373+int x, y;
374+
375+#define TEST_EXPR(NAME, ARGS, EXPR) \
376+ int NAME##1 ARGS { return (EXPR); } \
377+ int NAME##2 ARGS { return !(EXPR); } \
378+ int NAME##3 ARGS { return (EXPR) ? x : y; } \
379+ void NAME##4 ARGS { if (EXPR) x++; } \
380+ void NAME##5 ARGS { if (!(EXPR)) x++; }
381+
382+#define TEST(NAME, TYPE, OPERATOR) \
383+ TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), a1 OPERATOR a2) \
384+ TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), a1 OPERATOR *a2) \
385+ TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), *a1 OPERATOR a2) \
386+ TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), *a1 OPERATOR *a2) \
387+ TEST_EXPR (NAME##_rc, (TYPE a1), a1 OPERATOR 100) \
388+ TEST_EXPR (NAME##_cr, (TYPE a1), 100 OPERATOR a1)
389+
390+#define TEST_OP(NAME, OPERATOR) \
391+ TEST (sc_##NAME, signed char, OPERATOR) \
392+ TEST (uc_##NAME, unsigned char, OPERATOR) \
393+ TEST (ss_##NAME, short, OPERATOR) \
394+ TEST (us_##NAME, unsigned short, OPERATOR) \
395+ TEST (si_##NAME, int, OPERATOR) \
396+ TEST (ui_##NAME, unsigned int, OPERATOR) \
397+ TEST (sll_##NAME, long long, OPERATOR) \
398+ TEST (ull_##NAME, unsigned long long, OPERATOR)
399+
400+TEST_OP (eq, ==)
401+TEST_OP (ne, !=)
402+TEST_OP (lt, <)
403+TEST_OP (gt, >)
404+TEST_OP (le, <=)
405+TEST_OP (ge, >=)
406
407=== added file 'gcc/testsuite/gcc.target/arm/cmp-2.c'
408--- old/gcc/testsuite/gcc.target/arm/cmp-2.c 1970-01-01 00:00:00 +0000
409+++ new/gcc/testsuite/gcc.target/arm/cmp-2.c 2011-10-03 10:09:55 +0000
410@@ -0,0 +1,49 @@
411+/* { dg-do compile } */
412+/* { dg-require-effective-target arm_vfp_ok } */
413+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
414+/* { dg-options "-O -mfpu=vfp -mfloat-abi=softfp" } */
415+/* { dg-final { scan-assembler-not "\tbl\t" } } */
416+/* { dg-final { scan-assembler-not "__aeabi" } } */
417+int x, y;
418+
419+#define EQ(X, Y) ((X) == (Y))
420+#define NE(X, Y) ((X) != (Y))
421+#define LT(X, Y) ((X) < (Y))
422+#define GT(X, Y) ((X) > (Y))
423+#define LE(X, Y) ((X) <= (Y))
424+#define GE(X, Y) ((X) >= (Y))
425+
426+#define TEST_EXPR(NAME, ARGS, EXPR) \
427+ int NAME##1 ARGS { return (EXPR); } \
428+ int NAME##2 ARGS { return !(EXPR); } \
429+ int NAME##3 ARGS { return (EXPR) ? x : y; } \
430+ void NAME##4 ARGS { if (EXPR) x++; } \
431+ void NAME##5 ARGS { if (!(EXPR)) x++; }
432+
433+#define TEST(NAME, TYPE, OPERATOR) \
434+ TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), OPERATOR (a1, a2)) \
435+ TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), OPERATOR (a1, *a2)) \
436+ TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), OPERATOR (*a1, a2)) \
437+ TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), OPERATOR (*a1, *a2)) \
438+ TEST_EXPR (NAME##_rc, (TYPE a1), OPERATOR (a1, 100)) \
439+ TEST_EXPR (NAME##_cr, (TYPE a1), OPERATOR (100, a1))
440+
441+#define TEST_OP(NAME, OPERATOR) \
442+ TEST (f_##NAME, float, OPERATOR) \
443+ TEST (d_##NAME, double, OPERATOR) \
444+ TEST (ld_##NAME, long double, OPERATOR)
445+
446+TEST_OP (eq, EQ)
447+TEST_OP (ne, NE)
448+TEST_OP (lt, LT)
449+TEST_OP (gt, GT)
450+TEST_OP (le, LE)
451+TEST_OP (ge, GE)
452+TEST_OP (blt, __builtin_isless)
453+TEST_OP (bgt, __builtin_isgreater)
454+TEST_OP (ble, __builtin_islessequal)
455+TEST_OP (bge, __builtin_isgreaterequal)
456+/* This one should be expanded into separate ordered and equality
457+ comparisons. */
458+TEST_OP (blg, __builtin_islessgreater)
459+TEST_OP (bun, __builtin_isunordered)
460
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