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authorKhem Raj <raj.khem@gmail.com>2011-09-29 22:12:52 +0000
committerKoen Kooi <koen@dominion.thruhere.net>2011-10-04 13:48:57 +0200
commitb9b5306e551f26d76e9dc5fa6f10c2c095fe6e0f (patch)
tree3908112a2010485903e16f9f7fec5d0fec2a37fa /meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch
parent9f2e55480dc94e90ac09ca468cf2f0dacb54ae2d (diff)
downloadmeta-openembedded-b9b5306e551f26d76e9dc5fa6f10c2c095fe6e0f.tar.gz
gcc-4.6: Bring in latest linaro patches
Adjust existing patches for latest FSF gcc-4_6-branch Signed-off-by: Khem Raj <raj.khem@gmail.com> Acked-by: Martin Jansa <Martin.Jansa@gmail.com> Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Diffstat (limited to 'meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch')
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch80
1 files changed, 4 insertions, 76 deletions
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch
index 8d2ce21762..4abfa02a77 100644
--- a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch
@@ -1,87 +1,16 @@
12011-06-28 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> 12011-06-28 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2 2
3 Backport from mainline. 3 Backport from mainline.
4 LP 791327
5 gcc/
6 2011-06-09 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
7
8 PR target/49335
9 * config/arm/predicates.md (add_operator): New.
10 * config/arm/arm.md ("*arith_shiftsi"): Fix for SP reg usage
11 in Thumb2.
12
132011-06-28 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
14
15 Backport from mainline.
16 gcc/ 4 gcc/
17 2011-06-24 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> 5 2011-06-24 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
18 6
19 PR target/49385 7 PR target/49385
20 * config/arm/thumb2.md (*thumb2_movhi_insn): Make sure atleast 8 * config/arm/thumb2.md (*thumb2_movhi_insn): Make sure atleast
21 one of the operands is a register. 9 one of the operands is a register.
22 10Index: gcc-4_6-branch/gcc/config/arm/thumb2.md
23=== modified file 'gcc/config/arm/arm.md' 11===================================================================
24--- old/gcc/config/arm/arm.md 2011-06-27 22:14:07 +0000 12--- gcc-4_6-branch.orig/gcc/config/arm/thumb2.md 2011-09-16 20:22:40.000000000 -0700
25+++ new/gcc/config/arm/arm.md 2011-06-28 12:02:27 +0000 13+++ gcc-4_6-branch/gcc/config/arm/thumb2.md 2011-09-16 20:28:47.648690433 -0700
26@@ -8584,18 +8584,22 @@
27 ;; Patterns to allow combination of arithmetic, cond code and shifts
28
29 (define_insn "*arith_shiftsi"
30- [(set (match_operand:SI 0 "s_register_operand" "=r,r")
31+ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
32 (match_operator:SI 1 "shiftable_operator"
33 [(match_operator:SI 3 "shift_operator"
34- [(match_operand:SI 4 "s_register_operand" "r,r")
35- (match_operand:SI 5 "shift_amount_operand" "M,r")])
36- (match_operand:SI 2 "s_register_operand" "rk,rk")]))]
37+ [(match_operand:SI 4 "s_register_operand" "r,r,r,r")
38+ (match_operand:SI 5 "shift_amount_operand" "M,M,M,r")])
39+ (match_operand:SI 2 "s_register_operand" "rk,rk,r,rk")]))]
40 "TARGET_32BIT"
41 "%i1%?\\t%0, %2, %4%S3"
42 [(set_attr "predicable" "yes")
43 (set_attr "shift" "4")
44- (set_attr "arch" "32,a")
45- ;; We have to make sure to disable the second alternative if
46+ (set_attr "arch" "a,t2,t2,a")
47+ ;; Thumb2 doesn't allow the stack pointer to be used for
48+ ;; operand1 for all operations other than add and sub. In this case
49+ ;; the minus operation is a candidate for an rsub and hence needs
50+ ;; to be disabled.
51+ ;; We have to make sure to disable the fourth alternative if
52 ;; the shift_operator is MULT, since otherwise the insn will
53 ;; also match a multiply_accumulate pattern and validate_change
54 ;; will allow a replacement of the constant with a register
55@@ -8603,9 +8607,13 @@
56 (set_attr_alternative "insn_enabled"
57 [(const_string "yes")
58 (if_then_else
59+ (match_operand:SI 1 "add_operator" "")
60+ (const_string "yes") (const_string "no"))
61+ (const_string "yes")
62+ (if_then_else
63 (match_operand:SI 3 "mult_operator" "")
64 (const_string "no") (const_string "yes"))])
65- (set_attr "type" "alu_shift,alu_shift_reg")])
66+ (set_attr "type" "alu_shift,alu_shift,alu_shift,alu_shift_reg")])
67
68 (define_split
69 [(set (match_operand:SI 0 "s_register_operand" "")
70
71=== modified file 'gcc/config/arm/predicates.md'
72--- old/gcc/config/arm/predicates.md 2011-05-03 15:14:56 +0000
73+++ new/gcc/config/arm/predicates.md 2011-06-22 15:50:23 +0000
74@@ -687,3 +687,6 @@
75 (define_special_predicate "neon_struct_operand"
76 (and (match_code "mem")
77 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
78+
79+(define_special_predicate "add_operator"
80+ (match_code "plus"))
81
82=== modified file 'gcc/config/arm/thumb2.md'
83--- old/gcc/config/arm/thumb2.md 2011-06-14 14:37:30 +0000
84+++ new/gcc/config/arm/thumb2.md 2011-06-20 12:18:27 +0000
85@@ -207,7 +207,9 @@ 14@@ -207,7 +207,9 @@
86 (define_insn "*thumb2_movhi_insn" 15 (define_insn "*thumb2_movhi_insn"
87 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r") 16 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
@@ -93,4 +22,3 @@
93 "@ 22 "@
94 mov%?\\t%0, %1\\t%@ movhi 23 mov%?\\t%0, %1\\t%@ movhi
95 movw%?\\t%0, %L1\\t%@ movhi 24 movw%?\\t%0, %L1\\t%@ movhi
96