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-rw-r--r--meta-oe/recipes-dbs/postgresql/files/0001-Add-support-for-RISC-V.patch31
1 files changed, 14 insertions, 17 deletions
diff --git a/meta-oe/recipes-dbs/postgresql/files/0001-Add-support-for-RISC-V.patch b/meta-oe/recipes-dbs/postgresql/files/0001-Add-support-for-RISC-V.patch
index 7a4ba9897c..34d34ecad9 100644
--- a/meta-oe/recipes-dbs/postgresql/files/0001-Add-support-for-RISC-V.patch
+++ b/meta-oe/recipes-dbs/postgresql/files/0001-Add-support-for-RISC-V.patch
@@ -1,21 +1,19 @@
1From 780fd27ea6f7f2c446c46a7a5e26d94106c67efd Mon Sep 17 00:00:00 2001 1From ba079b8d6a50796db41bb0ddf4c22bfe022ef898 Mon Sep 17 00:00:00 2001
2From: "Richard W.M. Jones" <rjones@redhat.com> 2From: "Richard W.M. Jones" <rjones@redhat.com>
3Date: Sun, 20 Nov 2016 15:04:52 +0000 3Date: Sun, 20 Nov 2016 15:04:52 +0000
4Subject: [PATCH] Add support for RISC-V. 4Subject: [PATCH 1/5] Add support for RISC-V.
5 5
6The architecture is sufficiently similar to aarch64 that simply 6The architecture is sufficiently similar to aarch64 that simply
7extending the existing aarch64 macro works. 7extending the existing aarch64 macro works.
8--- 8---
9Upstream-Status: Pending 9 src/include/storage/s_lock.h | 5 +++--
10 10 1 file changed, 3 insertions(+), 2 deletions(-)
11 src/include/storage/s_lock.h | 6 +++---
12 1 file changed, 3 insertions(+), 3 deletions(-)
13 11
14diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h 12diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h
15index 4d3ffc7..22e27bf 100644 13index c9fa84c..9b491e8 100644
16--- a/src/include/storage/s_lock.h 14--- a/src/include/storage/s_lock.h
17+++ b/src/include/storage/s_lock.h 15+++ b/src/include/storage/s_lock.h
18@@ -317,11 +317,12 @@ tas(volatile slock_t *lock) 16@@ -252,11 +252,12 @@ spin_delay(void)
19 17
20 /* 18 /*
21 * On ARM and ARM64, we use __sync_lock_test_and_set(int *, int) if available. 19 * On ARM and ARM64, we use __sync_lock_test_and_set(int *, int) if available.
@@ -24,21 +22,20 @@ index 4d3ffc7..22e27bf 100644
24 * We use the int-width variant of the builtin because it works on more chips 22 * We use the int-width variant of the builtin because it works on more chips
25 * than other widths. 23 * than other widths.
26 */ 24 */
27-#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64) 25-#if defined(__arm__) || defined(__arm) || defined(__aarch64__)
28+#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64) || defined(__riscv) 26+#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__riscv)
29 #ifdef HAVE_GCC__SYNC_INT32_TAS 27 #ifdef HAVE_GCC__SYNC_INT32_TAS
30 #define HAS_TEST_AND_SET 28 #define HAS_TEST_AND_SET
31 29
32@@ -355,8 +356,7 @@ spin_delay(void) 30@@ -290,7 +291,7 @@ spin_delay(void)
33 31
34 #endif /* __aarch64__ || __aarch64 */ 32 #endif /* __aarch64__ */
35 #endif /* HAVE_GCC__SYNC_INT32_TAS */ 33 #endif /* HAVE_GCC__SYNC_INT32_TAS */
36-#endif /* __arm__ || __arm || __aarch64__ || __aarch64 */ 34-#endif /* __arm__ || __arm || __aarch64__ */
37- 35+#endif /* __arm__ || __arm || __aarch64__ || __riscv */
38+#endif /* __arm__ || __arm || __aarch64__ || __aarch64 || __riscv */ 36
39 37
40 /* S/390 and S/390x Linux (32- and 64-bit zSeries) */ 38 /* S/390 and S/390x Linux (32- and 64-bit zSeries) */
41 #if defined(__s390__) || defined(__s390x__)
42-- 39--
432.34.1 402.25.1
44 41