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1 files changed, 342 insertions, 0 deletions
diff --git a/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch b/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch
new file mode 100644
index 0000000000..0705e4183f
--- /dev/null
+++ b/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch
@@ -0,0 +1,342 @@
12010-08-18 Julian Brown <julian@codesourcery.com>
2
3 Issue #9222
4
5 gcc/
6 * config/arm/neon.md (UNSPEC_VCLE, UNSPEC_VCLT): New constants for
7 unspecs.
8 (vcond<mode>, vcondu<mode>): New expanders.
9 (neon_vceq<mode>, neon_vcge<mode>, neon_vcgt<mode>): Support
10 comparisons with zero.
11 (neon_vcle<mode>, neon_vclt<mode>): New patterns.
12 * config/arm/constraints.md (Dz): New constraint.
13
14 2010-08-18 Jie Zhang <jie@codesourcery.com>
15
16 Backport from mainline:
17
18=== modified file 'gcc/config/arm/constraints.md'
19Index: gcc-4.5/gcc/config/arm/constraints.md
20===================================================================
21--- gcc-4.5.orig/gcc/config/arm/constraints.md
22+++ gcc-4.5/gcc/config/arm/constraints.md
23@@ -29,7 +29,7 @@
24 ;; in Thumb-1 state: I, J, K, L, M, N, O
25
26 ;; The following multi-letter normal constraints have been used:
27-;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di
28+;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dz
29 ;; in Thumb-1 state: Pa, Pb
30 ;; in Thumb-2 state: Ps, Pt, Pv
31
32@@ -173,6 +173,12 @@
33 (and (match_code "const_double")
34 (match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)")))
35
36+(define_constraint "Dz"
37+ "@internal
38+ In ARM/Thumb-2 state a vector of constant zeros."
39+ (and (match_code "const_vector")
40+ (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
41+
42 (define_constraint "Da"
43 "@internal
44 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
45Index: gcc-4.5/gcc/config/arm/neon.md
46===================================================================
47--- gcc-4.5.orig/gcc/config/arm/neon.md
48+++ gcc-4.5/gcc/config/arm/neon.md
49@@ -141,7 +141,9 @@
50 (UNSPEC_VUZP2 202)
51 (UNSPEC_VZIP1 203)
52 (UNSPEC_VZIP2 204)
53- (UNSPEC_MISALIGNED_ACCESS 205)])
54+ (UNSPEC_MISALIGNED_ACCESS 205)
55+ (UNSPEC_VCLE 206)
56+ (UNSPEC_VCLT 207)])
57
58 ;; Double-width vector modes.
59 (define_mode_iterator VD [V8QI V4HI V2SI V2SF])
60@@ -1804,6 +1806,169 @@
61 [(set_attr "neon_type" "neon_int_5")]
62 )
63
64+;; Conditional instructions. These are comparisons with conditional moves for
65+;; vectors. They perform the assignment:
66+;;
67+;; Vop0 = (Vop4 <op3> Vop5) ? Vop1 : Vop2;
68+;;
69+;; where op3 is <, <=, ==, !=, >= or >. Operations are performed
70+;; element-wise.
71+
72+(define_expand "vcond<mode>"
73+ [(set (match_operand:VDQW 0 "s_register_operand" "")
74+ (if_then_else:VDQW
75+ (match_operator 3 "arm_comparison_operator"
76+ [(match_operand:VDQW 4 "s_register_operand" "")
77+ (match_operand:VDQW 5 "nonmemory_operand" "")])
78+ (match_operand:VDQW 1 "s_register_operand" "")
79+ (match_operand:VDQW 2 "s_register_operand" "")))]
80+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
81+{
82+ rtx mask;
83+ int inverse = 0, immediate_zero = 0;
84+ /* See the description of "magic" bits in the 'T' case of
85+ arm_print_operand. */
86+ HOST_WIDE_INT magic_word = (<MODE>mode == V2SFmode || <MODE>mode == V4SFmode)
87+ ? 3 : 1;
88+ rtx magic_rtx = GEN_INT (magic_word);
89+
90+ mask = gen_reg_rtx (<V_cmp_result>mode);
91+
92+ if (operands[5] == CONST0_RTX (<MODE>mode))
93+ immediate_zero = 1;
94+ else if (!REG_P (operands[5]))
95+ operands[5] = force_reg (<MODE>mode, operands[5]);
96+
97+ switch (GET_CODE (operands[3]))
98+ {
99+ case GE:
100+ emit_insn (gen_neon_vcge<mode> (mask, operands[4], operands[5],
101+ magic_rtx));
102+ break;
103+
104+ case GT:
105+ emit_insn (gen_neon_vcgt<mode> (mask, operands[4], operands[5],
106+ magic_rtx));
107+ break;
108+
109+ case EQ:
110+ emit_insn (gen_neon_vceq<mode> (mask, operands[4], operands[5],
111+ magic_rtx));
112+ break;
113+
114+ case LE:
115+ if (immediate_zero)
116+ emit_insn (gen_neon_vcle<mode> (mask, operands[4], operands[5],
117+ magic_rtx));
118+ else
119+ emit_insn (gen_neon_vcge<mode> (mask, operands[5], operands[4],
120+ magic_rtx));
121+ break;
122+
123+ case LT:
124+ if (immediate_zero)
125+ emit_insn (gen_neon_vclt<mode> (mask, operands[4], operands[5],
126+ magic_rtx));
127+ else
128+ emit_insn (gen_neon_vcgt<mode> (mask, operands[5], operands[4],
129+ magic_rtx));
130+ break;
131+
132+ case NE:
133+ emit_insn (gen_neon_vceq<mode> (mask, operands[4], operands[5],
134+ magic_rtx));
135+ inverse = 1;
136+ break;
137+
138+ default:
139+ gcc_unreachable ();
140+ }
141+
142+ if (inverse)
143+ emit_insn (gen_neon_vbsl<mode> (operands[0], mask, operands[2],
144+ operands[1]));
145+ else
146+ emit_insn (gen_neon_vbsl<mode> (operands[0], mask, operands[1],
147+ operands[2]));
148+
149+ DONE;
150+})
151+
152+(define_expand "vcondu<mode>"
153+ [(set (match_operand:VDQIW 0 "s_register_operand" "")
154+ (if_then_else:VDQIW
155+ (match_operator 3 "arm_comparison_operator"
156+ [(match_operand:VDQIW 4 "s_register_operand" "")
157+ (match_operand:VDQIW 5 "s_register_operand" "")])
158+ (match_operand:VDQIW 1 "s_register_operand" "")
159+ (match_operand:VDQIW 2 "s_register_operand" "")))]
160+ "TARGET_NEON"
161+{
162+ rtx mask;
163+ int inverse = 0, immediate_zero = 0;
164+
165+ mask = gen_reg_rtx (<V_cmp_result>mode);
166+
167+ if (operands[5] == CONST0_RTX (<MODE>mode))
168+ immediate_zero = 1;
169+ else if (!REG_P (operands[5]))
170+ operands[5] = force_reg (<MODE>mode, operands[5]);
171+
172+ switch (GET_CODE (operands[3]))
173+ {
174+ case GEU:
175+ emit_insn (gen_neon_vcge<mode> (mask, operands[4], operands[5],
176+ const0_rtx));
177+ break;
178+
179+ case GTU:
180+ emit_insn (gen_neon_vcgt<mode> (mask, operands[4], operands[5],
181+ const0_rtx));
182+ break;
183+
184+ case EQ:
185+ emit_insn (gen_neon_vceq<mode> (mask, operands[4], operands[5],
186+ const0_rtx));
187+ break;
188+
189+ case LEU:
190+ if (immediate_zero)
191+ emit_insn (gen_neon_vcle<mode> (mask, operands[4], operands[5],
192+ const0_rtx));
193+ else
194+ emit_insn (gen_neon_vcge<mode> (mask, operands[5], operands[4],
195+ const0_rtx));
196+ break;
197+
198+ case LTU:
199+ if (immediate_zero)
200+ emit_insn (gen_neon_vclt<mode> (mask, operands[4], operands[5],
201+ const0_rtx));
202+ else
203+ emit_insn (gen_neon_vcgt<mode> (mask, operands[5], operands[4],
204+ const0_rtx));
205+ break;
206+
207+ case NE:
208+ emit_insn (gen_neon_vceq<mode> (mask, operands[4], operands[5],
209+ const0_rtx));
210+ inverse = 1;
211+ break;
212+
213+ default:
214+ gcc_unreachable ();
215+ }
216+
217+ if (inverse)
218+ emit_insn (gen_neon_vbsl<mode> (operands[0], mask, operands[2],
219+ operands[1]));
220+ else
221+ emit_insn (gen_neon_vbsl<mode> (operands[0], mask, operands[1],
222+ operands[2]));
223+
224+ DONE;
225+})
226+
227 ;; Patterns for builtins.
228
229 ; good for plain vadd, vaddq.
230@@ -2215,13 +2380,16 @@
231 )
232
233 (define_insn "neon_vceq<mode>"
234- [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
235- (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w")
236- (match_operand:VDQW 2 "s_register_operand" "w")
237- (match_operand:SI 3 "immediate_operand" "i")]
238- UNSPEC_VCEQ))]
239+ [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w")
240+ (unspec:<V_cmp_result>
241+ [(match_operand:VDQW 1 "s_register_operand" "w,w")
242+ (match_operand:VDQW 2 "nonmemory_operand" "w,Dz")
243+ (match_operand:SI 3 "immediate_operand" "i,i")]
244+ UNSPEC_VCEQ))]
245 "TARGET_NEON"
246- "vceq.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
247+ "@
248+ vceq.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
249+ vceq.<V_if_elem>\t%<V_reg>0, %<V_reg>1, #0"
250 [(set (attr "neon_type")
251 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
252 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
253@@ -2231,13 +2399,16 @@
254 )
255
256 (define_insn "neon_vcge<mode>"
257- [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
258- (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w")
259- (match_operand:VDQW 2 "s_register_operand" "w")
260- (match_operand:SI 3 "immediate_operand" "i")]
261- UNSPEC_VCGE))]
262+ [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w")
263+ (unspec:<V_cmp_result>
264+ [(match_operand:VDQW 1 "s_register_operand" "w,w")
265+ (match_operand:VDQW 2 "nonmemory_operand" "w,Dz")
266+ (match_operand:SI 3 "immediate_operand" "i,i")]
267+ UNSPEC_VCGE))]
268 "TARGET_NEON"
269- "vcge.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
270+ "@
271+ vcge.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
272+ vcge.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0"
273 [(set (attr "neon_type")
274 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
275 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
276@@ -2247,13 +2418,16 @@
277 )
278
279 (define_insn "neon_vcgt<mode>"
280- [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
281- (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w")
282- (match_operand:VDQW 2 "s_register_operand" "w")
283- (match_operand:SI 3 "immediate_operand" "i")]
284- UNSPEC_VCGT))]
285+ [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w")
286+ (unspec:<V_cmp_result>
287+ [(match_operand:VDQW 1 "s_register_operand" "w,w")
288+ (match_operand:VDQW 2 "nonmemory_operand" "w,Dz")
289+ (match_operand:SI 3 "immediate_operand" "i,i")]
290+ UNSPEC_VCGT))]
291 "TARGET_NEON"
292- "vcgt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
293+ "@
294+ vcgt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
295+ vcgt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0"
296 [(set (attr "neon_type")
297 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
298 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
299@@ -2262,6 +2436,43 @@
300 (const_string "neon_int_5")))]
301 )
302
303+;; VCLE and VCLT only support comparisons with immediate zero (register
304+;; variants are VCGE and VCGT with operands reversed).
305+
306+(define_insn "neon_vcle<mode>"
307+ [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
308+ (unspec:<V_cmp_result>
309+ [(match_operand:VDQW 1 "s_register_operand" "w")
310+ (match_operand:VDQW 2 "nonmemory_operand" "Dz")
311+ (match_operand:SI 3 "immediate_operand" "i")]
312+ UNSPEC_VCLE))]
313+ "TARGET_NEON"
314+ "vcle.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0"
315+ [(set (attr "neon_type")
316+ (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
317+ (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
318+ (const_string "neon_fp_vadd_ddd_vabs_dd")
319+ (const_string "neon_fp_vadd_qqq_vabs_qq"))
320+ (const_string "neon_int_5")))]
321+)
322+
323+(define_insn "neon_vclt<mode>"
324+ [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
325+ (unspec:<V_cmp_result>
326+ [(match_operand:VDQW 1 "s_register_operand" "w")
327+ (match_operand:VDQW 2 "nonmemory_operand" "Dz")
328+ (match_operand:SI 3 "immediate_operand" "i")]
329+ UNSPEC_VCLT))]
330+ "TARGET_NEON"
331+ "vclt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0"
332+ [(set (attr "neon_type")
333+ (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
334+ (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
335+ (const_string "neon_fp_vadd_ddd_vabs_dd")
336+ (const_string "neon_fp_vadd_qqq_vabs_qq"))
337+ (const_string "neon_int_5")))]
338+)
339+
340 (define_insn "neon_vcage<mode>"
341 [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
342 (unspec:<V_cmp_result> [(match_operand:VCVTF 1 "s_register_operand" "w")
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