summaryrefslogtreecommitdiffstats
path: root/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99408.patch
diff options
context:
space:
mode:
Diffstat (limited to 'toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99408.patch')
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99408.patch603
1 files changed, 603 insertions, 0 deletions
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99408.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99408.patch
new file mode 100644
index 0000000000..1d873ba653
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99408.patch
@@ -0,0 +1,603 @@
12010-10-01 Julian Brown <julian@codesourcery.com>
2
3 Revert:
4
5 Backport from FSF:
6
7 2010-08-07 Marcus Shawcroft <marcus.shawcroft@arm.com>
8
9 gcc/
10 * config/arm/linux-atomic.c (SUBWORD_VAL_CAS): Instantiate with
11 'unsigned short' and 'unsigned char' instead of 'short' and
12 'char'. (SUBWORD_BOOL_CAS): Likewise.
13 (SUBWORD_SYNC_OP): Likewise.
14 (SUBWORD_TEST_AND_SET): Likewise.
15 (FETCH_AND_OP_WORD): Parenthesise INF_OP
16 (SUBWORD_SYNC_OP): Likewise.
17 (OP_AND_FETCH_WORD): Likewise.
18
19 gcc/testsuite/
20 * lib/target-supports.exp: (check_effective_target_sync_int_long):
21 Add arm*-*-linux-gnueabi.
22 (check_effective_target_sync_char_short): Likewise.
23
24=== modified file 'gcc/config/arm/arm-protos.h'
25Index: gcc-4.5/gcc/config/arm/arm-protos.h
26===================================================================
27--- gcc-4.5.orig/gcc/config/arm/arm-protos.h
28+++ gcc-4.5/gcc/config/arm/arm-protos.h
29@@ -151,11 +151,6 @@ extern const char *vfp_output_fstmd (rtx
30 extern void arm_set_return_address (rtx, rtx);
31 extern int arm_eliminable_register (rtx);
32 extern const char *arm_output_shift(rtx *, int);
33-extern void arm_expand_sync (enum machine_mode, struct arm_sync_generator *,
34- rtx, rtx, rtx, rtx);
35-extern const char *arm_output_memory_barrier (rtx *);
36-extern const char *arm_output_sync_insn (rtx, rtx *);
37-extern unsigned int arm_sync_loop_insns (rtx , rtx *);
38
39 extern bool arm_output_addr_const_extra (FILE *, rtx);
40
41Index: gcc-4.5/gcc/config/arm/arm.c
42===================================================================
43--- gcc-4.5.orig/gcc/config/arm/arm.c
44+++ gcc-4.5/gcc/config/arm/arm.c
45@@ -605,7 +605,6 @@ static int thumb_call_reg_needed;
46 #define FL_NEON (1 << 20) /* Neon instructions. */
47 #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M
48 architecture. */
49-#define FL_ARCH7 (1 << 22) /* Architecture 7. */
50
51 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
52
53@@ -626,7 +625,7 @@ static int thumb_call_reg_needed;
54 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
55 #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
56 #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
57-#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
58+#define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM)
59 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
60 #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
61 #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
62@@ -664,9 +663,6 @@ int arm_arch6 = 0;
63 /* Nonzero if this chip supports the ARM 6K extensions. */
64 int arm_arch6k = 0;
65
66-/* Nonzero if this chip supports the ARM 7 extensions. */
67-int arm_arch7 = 0;
68-
69 /* Nonzero if instructions not present in the 'M' profile can be used. */
70 int arm_arch_notm = 0;
71
72@@ -1638,7 +1634,6 @@ arm_override_options (void)
73 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
74 arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
75 arm_arch_notm = (insn_flags & FL_NOTM) != 0;
76- arm_arch7 = (insn_flags & FL_ARCH7) != 0;
77 arm_arch7em = (insn_flags & FL_ARCH7EM) != 0;
78 arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
79 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
80@@ -16595,17 +16590,6 @@ arm_print_operand (FILE *stream, rtx x,
81 }
82 return;
83
84- case 'C':
85- {
86- rtx addr;
87-
88- gcc_assert (GET_CODE (x) == MEM);
89- addr = XEXP (x, 0);
90- gcc_assert (GET_CODE (addr) == REG);
91- asm_fprintf (stream, "[%r]", REGNO (addr));
92- }
93- return;
94-
95 /* Translate an S register number into a D register number and element index. */
96 case 'y':
97 {
98@@ -22840,372 +22824,4 @@ arm_builtin_support_vector_misalignment
99 is_packed);
100 }
101
102-/* Legitimize a memory reference for sync primitive implemented using
103- ldrex / strex. We currently force the form of the reference to be
104- indirect without offset. We do not yet support the indirect offset
105- addressing supported by some ARM targets for these
106- instructions. */
107-static rtx
108-arm_legitimize_sync_memory (rtx memory)
109-{
110- rtx addr = force_reg (Pmode, XEXP (memory, 0));
111- rtx legitimate_memory = gen_rtx_MEM (GET_MODE (memory), addr);
112-
113- set_mem_alias_set (legitimate_memory, ALIAS_SET_MEMORY_BARRIER);
114- MEM_VOLATILE_P (legitimate_memory) = MEM_VOLATILE_P (memory);
115- return legitimate_memory;
116-}
117-
118-/* An instruction emitter. */
119-typedef void (* emit_f) (int label, const char *, rtx *);
120-
121-/* An instruction emitter that emits via the conventional
122- output_asm_insn. */
123-static void
124-arm_emit (int label ATTRIBUTE_UNUSED, const char *pattern, rtx *operands)
125-{
126- output_asm_insn (pattern, operands);
127-}
128-
129-/* Count the number of emitted synchronization instructions. */
130-static unsigned arm_insn_count;
131-
132-/* An emitter that counts emitted instructions but does not actually
133- emit instruction into the the instruction stream. */
134-static void
135-arm_count (int label,
136- const char *pattern ATTRIBUTE_UNUSED,
137- rtx *operands ATTRIBUTE_UNUSED)
138-{
139- if (! label)
140- ++ arm_insn_count;
141-}
142-
143-/* Construct a pattern using conventional output formatting and feed
144- it to output_asm_insn. Provides a mechanism to construct the
145- output pattern on the fly. Note the hard limit on the pattern
146- buffer size. */
147-static void
148-arm_output_asm_insn (emit_f emit, int label, rtx *operands,
149- const char *pattern, ...)
150-{
151- va_list ap;
152- char buffer[256];
153-
154- va_start (ap, pattern);
155- vsprintf (buffer, pattern, ap);
156- va_end (ap);
157- emit (label, buffer, operands);
158-}
159-
160-/* Emit the memory barrier instruction, if any, provided by this
161- target to a specified emitter. */
162-static void
163-arm_process_output_memory_barrier (emit_f emit, rtx *operands)
164-{
165- if (TARGET_HAVE_DMB)
166- {
167- /* Note we issue a system level barrier. We should consider
168- issuing a inner shareabilty zone barrier here instead, ie.
169- "DMB ISH". */
170- emit (0, "dmb\tsy", operands);
171- return;
172- }
173-
174- if (TARGET_HAVE_DMB_MCR)
175- {
176- emit (0, "mcr\tp15, 0, r0, c7, c10, 5", operands);
177- return;
178- }
179-
180- gcc_unreachable ();
181-}
182-
183-/* Emit the memory barrier instruction, if any, provided by this
184- target. */
185-const char *
186-arm_output_memory_barrier (rtx *operands)
187-{
188- arm_process_output_memory_barrier (arm_emit, operands);
189- return "";
190-}
191-
192-/* Helper to figure out the instruction suffix required on ldrex/strex
193- for operations on an object of the specified mode. */
194-static const char *
195-arm_ldrex_suffix (enum machine_mode mode)
196-{
197- switch (mode)
198- {
199- case QImode: return "b";
200- case HImode: return "h";
201- case SImode: return "";
202- case DImode: return "d";
203- default:
204- gcc_unreachable ();
205- }
206- return "";
207-}
208-
209-/* Emit an ldrex{b,h,d, } instruction appropriate for the specified
210- mode. */
211-static void
212-arm_output_ldrex (emit_f emit,
213- enum machine_mode mode,
214- rtx target,
215- rtx memory)
216-{
217- const char *suffix = arm_ldrex_suffix (mode);
218- rtx operands[2];
219-
220- operands[0] = target;
221- operands[1] = memory;
222- arm_output_asm_insn (emit, 0, operands, "ldrex%s\t%%0, %%C1", suffix);
223-}
224-
225-/* Emit a strex{b,h,d, } instruction appropriate for the specified
226- mode. */
227-static void
228-arm_output_strex (emit_f emit,
229- enum machine_mode mode,
230- const char *cc,
231- rtx result,
232- rtx value,
233- rtx memory)
234-{
235- const char *suffix = arm_ldrex_suffix (mode);
236- rtx operands[3];
237-
238- operands[0] = result;
239- operands[1] = value;
240- operands[2] = memory;
241- arm_output_asm_insn (emit, 0, operands, "strex%s%s\t%%0, %%1, %%C2", suffix,
242- cc);
243-}
244-
245-/* Helper to emit a two operand instruction. */
246-static void
247-arm_output_op2 (emit_f emit, const char *mnemonic, rtx d, rtx s)
248-{
249- rtx operands[2];
250-
251- operands[0] = d;
252- operands[1] = s;
253- arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1", mnemonic);
254-}
255-
256-/* Helper to emit a three operand instruction. */
257-static void
258-arm_output_op3 (emit_f emit, const char *mnemonic, rtx d, rtx a, rtx b)
259-{
260- rtx operands[3];
261-
262- operands[0] = d;
263- operands[1] = a;
264- operands[2] = b;
265- arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1, %%2", mnemonic);
266-}
267-
268-/* Emit a load store exclusive synchronization loop.
269-
270- do
271- old_value = [mem]
272- if old_value != required_value
273- break;
274- t1 = sync_op (old_value, new_value)
275- [mem] = t1, t2 = [0|1]
276- while ! t2
277-
278- Note:
279- t1 == t2 is not permitted
280- t1 == old_value is permitted
281-
282- required_value:
283-
284- RTX register or const_int representing the required old_value for
285- the modify to continue, if NULL no comparsion is performed. */
286-static void
287-arm_output_sync_loop (emit_f emit,
288- enum machine_mode mode,
289- rtx old_value,
290- rtx memory,
291- rtx required_value,
292- rtx new_value,
293- rtx t1,
294- rtx t2,
295- enum attr_sync_op sync_op,
296- int early_barrier_required)
297-{
298- rtx operands[1];
299-
300- gcc_assert (t1 != t2);
301-
302- if (early_barrier_required)
303- arm_process_output_memory_barrier (emit, NULL);
304-
305- arm_output_asm_insn (emit, 1, operands, "%sLSYT%%=:", LOCAL_LABEL_PREFIX);
306-
307- arm_output_ldrex (emit, mode, old_value, memory);
308-
309- if (required_value)
310- {
311- rtx operands[2];
312-
313- operands[0] = old_value;
314- operands[1] = required_value;
315- arm_output_asm_insn (emit, 0, operands, "cmp\t%%0, %%1");
316- arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYB%%=", LOCAL_LABEL_PREFIX);
317- }
318-
319- switch (sync_op)
320- {
321- case SYNC_OP_ADD:
322- arm_output_op3 (emit, "add", t1, old_value, new_value);
323- break;
324-
325- case SYNC_OP_SUB:
326- arm_output_op3 (emit, "sub", t1, old_value, new_value);
327- break;
328-
329- case SYNC_OP_IOR:
330- arm_output_op3 (emit, "orr", t1, old_value, new_value);
331- break;
332-
333- case SYNC_OP_XOR:
334- arm_output_op3 (emit, "eor", t1, old_value, new_value);
335- break;
336-
337- case SYNC_OP_AND:
338- arm_output_op3 (emit,"and", t1, old_value, new_value);
339- break;
340-
341- case SYNC_OP_NAND:
342- arm_output_op3 (emit, "and", t1, old_value, new_value);
343- arm_output_op2 (emit, "mvn", t1, t1);
344- break;
345-
346- case SYNC_OP_NONE:
347- t1 = new_value;
348- break;
349- }
350-
351- arm_output_strex (emit, mode, "", t2, t1, memory);
352- operands[0] = t2;
353- arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0");
354- arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", LOCAL_LABEL_PREFIX);
355-
356- arm_process_output_memory_barrier (emit, NULL);
357- arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX);
358-}
359-
360-static rtx
361-arm_get_sync_operand (rtx *operands, int index, rtx default_value)
362-{
363- if (index > 0)
364- default_value = operands[index - 1];
365-
366- return default_value;
367-}
368-
369-#define FETCH_SYNC_OPERAND(NAME, DEFAULT) \
370- arm_get_sync_operand (operands, (int) get_attr_sync_##NAME (insn), DEFAULT);
371-
372-/* Extract the operands for a synchroniztion instruction from the
373- instructions attributes and emit the instruction. */
374-static void
375-arm_process_output_sync_insn (emit_f emit, rtx insn, rtx *operands)
376-{
377- rtx result, memory, required_value, new_value, t1, t2;
378- int early_barrier;
379- enum machine_mode mode;
380- enum attr_sync_op sync_op;
381-
382- result = FETCH_SYNC_OPERAND(result, 0);
383- memory = FETCH_SYNC_OPERAND(memory, 0);
384- required_value = FETCH_SYNC_OPERAND(required_value, 0);
385- new_value = FETCH_SYNC_OPERAND(new_value, 0);
386- t1 = FETCH_SYNC_OPERAND(t1, 0);
387- t2 = FETCH_SYNC_OPERAND(t2, 0);
388- early_barrier =
389- get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES;
390- sync_op = get_attr_sync_op (insn);
391- mode = GET_MODE (memory);
392-
393- arm_output_sync_loop (emit, mode, result, memory, required_value,
394- new_value, t1, t2, sync_op, early_barrier);
395-}
396-
397-/* Emit a synchronization instruction loop. */
398-const char *
399-arm_output_sync_insn (rtx insn, rtx *operands)
400-{
401- arm_process_output_sync_insn (arm_emit, insn, operands);
402- return "";
403-}
404-
405-/* Count the number of machine instruction that will be emitted for a
406- synchronization instruction. Note that the emitter used does not
407- emit instructions, it just counts instructions being carefull not
408- to count labels. */
409-unsigned int
410-arm_sync_loop_insns (rtx insn, rtx *operands)
411-{
412- arm_insn_count = 0;
413- arm_process_output_sync_insn (arm_count, insn, operands);
414- return arm_insn_count;
415-}
416-
417-/* Helper to call a target sync instruction generator, dealing with
418- the variation in operands required by the different generators. */
419-static rtx
420-arm_call_generator (struct arm_sync_generator *generator, rtx old_value,
421- rtx memory, rtx required_value, rtx new_value)
422-{
423- switch (generator->op)
424- {
425- case arm_sync_generator_omn:
426- gcc_assert (! required_value);
427- return generator->u.omn (old_value, memory, new_value);
428-
429- case arm_sync_generator_omrn:
430- gcc_assert (required_value);
431- return generator->u.omrn (old_value, memory, required_value, new_value);
432- }
433-
434- return NULL;
435-}
436-
437-/* Expand a synchronization loop. The synchronization loop is expanded
438- as an opaque block of instructions in order to ensure that we do
439- not subsequently get extraneous memory accesses inserted within the
440- critical region. The exclusive access property of ldrex/strex is
441- only guaranteed in there are no intervening memory accesses. */
442-void
443-arm_expand_sync (enum machine_mode mode,
444- struct arm_sync_generator *generator,
445- rtx target, rtx memory, rtx required_value, rtx new_value)
446-{
447- if (target == NULL)
448- target = gen_reg_rtx (mode);
449-
450- memory = arm_legitimize_sync_memory (memory);
451- if (mode != SImode)
452- {
453- rtx load_temp = gen_reg_rtx (SImode);
454-
455- if (required_value)
456- required_value = convert_modes (SImode, mode, required_value, true);
457-
458- new_value = convert_modes (SImode, mode, new_value, true);
459- emit_insn (arm_call_generator (generator, load_temp, memory,
460- required_value, new_value));
461- emit_move_insn (target, gen_lowpart (mode, load_temp));
462- }
463- else
464- {
465- emit_insn (arm_call_generator (generator, target, memory, required_value,
466- new_value));
467- }
468-}
469-
470 #include "gt-arm.h"
471Index: gcc-4.5/gcc/config/arm/arm.h
472===================================================================
473--- gcc-4.5.orig/gcc/config/arm/arm.h
474+++ gcc-4.5/gcc/config/arm/arm.h
475@@ -128,24 +128,6 @@ enum target_cpus
476 /* The processor for which instructions should be scheduled. */
477 extern enum processor_type arm_tune;
478
479-enum arm_sync_generator_tag
480- {
481- arm_sync_generator_omn,
482- arm_sync_generator_omrn
483- };
484-
485-/* Wrapper to pass around a polymorphic pointer to a sync instruction
486- generator and. */
487-struct arm_sync_generator
488-{
489- enum arm_sync_generator_tag op;
490- union
491- {
492- rtx (* omn) (rtx, rtx, rtx);
493- rtx (* omrn) (rtx, rtx, rtx, rtx);
494- } u;
495-};
496-
497 typedef enum arm_cond_code
498 {
499 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
500@@ -290,20 +272,6 @@ extern void (*arm_lang_output_object_att
501 for Thumb-2. */
502 #define TARGET_UNIFIED_ASM TARGET_THUMB2
503
504-/* Nonzero if this chip provides the DMB instruction. */
505-#define TARGET_HAVE_DMB (arm_arch7)
506-
507-/* Nonzero if this chip implements a memory barrier via CP15. */
508-#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB)
509-
510-/* Nonzero if this chip implements a memory barrier instruction. */
511-#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
512-
513-/* Nonzero if this chip supports ldrex and strex */
514-#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
515-
516-/* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */
517-#define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7)
518
519 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
520 then TARGET_AAPCS_BASED must be true -- but the converse does not
521@@ -437,12 +405,6 @@ extern int arm_arch5e;
522 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
523 extern int arm_arch6;
524
525-/* Nonzero if this chip supports the ARM Architecture 6k extensions. */
526-extern int arm_arch6k;
527-
528-/* Nonzero if this chip supports the ARM Architecture 7 extensions. */
529-extern int arm_arch7;
530-
531 /* Nonzero if instructions not present in the 'M' profile can be used. */
532 extern int arm_arch_notm;
533
534Index: gcc-4.5/gcc/config/arm/arm.md
535===================================================================
536--- gcc-4.5.orig/gcc/config/arm/arm.md
537+++ gcc-4.5/gcc/config/arm/arm.md
538@@ -103,7 +103,6 @@
539 (UNSPEC_RBIT 26) ; rbit operation.
540 (UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from
541 ; another symbolic address.
542- (UNSPEC_MEMORY_BARRIER 28) ; Represent a memory barrier.
543 ]
544 )
545
546@@ -140,11 +139,6 @@
547 (VUNSPEC_ALIGN32 16) ; Used to force 32-byte alignment.
548 (VUNSPEC_EH_RETURN 20); Use to override the return address for exception
549 ; handling.
550- (VUNSPEC_SYNC_COMPARE_AND_SWAP 21) ; Represent an atomic compare swap.
551- (VUNSPEC_SYNC_LOCK 22) ; Represent a sync_lock_test_and_set.
552- (VUNSPEC_SYNC_OP 23) ; Represent a sync_<op>
553- (VUNSPEC_SYNC_NEW_OP 24) ; Represent a sync_new_<op>
554- (VUNSPEC_SYNC_OLD_OP 25) ; Represent a sync_old_<op>
555 ]
556 )
557
558@@ -169,21 +163,8 @@
559 (define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp"
560 (const (symbol_ref "arm_fpu_attr")))
561
562-(define_attr "sync_result" "none,0,1,2,3,4,5" (const_string "none"))
563-(define_attr "sync_memory" "none,0,1,2,3,4,5" (const_string "none"))
564-(define_attr "sync_required_value" "none,0,1,2,3,4,5" (const_string "none"))
565-(define_attr "sync_new_value" "none,0,1,2,3,4,5" (const_string "none"))
566-(define_attr "sync_t1" "none,0,1,2,3,4,5" (const_string "none"))
567-(define_attr "sync_t2" "none,0,1,2,3,4,5" (const_string "none"))
568-(define_attr "sync_release_barrier" "yes,no" (const_string "yes"))
569-(define_attr "sync_op" "none,add,sub,ior,xor,and,nand"
570- (const_string "none"))
571-
572 ; LENGTH of an instruction (in bytes)
573-(define_attr "length" ""
574- (cond [(not (eq_attr "sync_memory" "none"))
575- (symbol_ref "arm_sync_loop_insns (insn, operands) * 4")
576- ] (const_int 4)))
577+(define_attr "length" "" (const_int 4))
578
579 ; POOL_RANGE is how far away from a constant pool entry that this insn
580 ; can be placed. If the distance is zero, then this insn will never
581@@ -11568,5 +11549,4 @@
582 (include "thumb2.md")
583 ;; Neon patterns
584 (include "neon.md")
585-;; Synchronization Primitives
586-(include "sync.md")
587+
588Index: gcc-4.5/gcc/config/arm/predicates.md
589===================================================================
590--- gcc-4.5.orig/gcc/config/arm/predicates.md
591+++ gcc-4.5/gcc/config/arm/predicates.md
592@@ -573,11 +573,6 @@
593 (and (match_test "TARGET_32BIT")
594 (match_operand 0 "arm_di_operand"))))
595
596-;; True if the operand is memory reference suitable for a ldrex/strex.
597-(define_predicate "arm_sync_memory_operand"
598- (and (match_operand 0 "memory_operand")
599- (match_code "reg" "0")))
600-
601 ;; Predicates for parallel expanders based on mode.
602 (define_special_predicate "vect_par_constant_high"
603 (match_code "parallel")
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-10-04 15:11:54 +0000