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-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106825.patch124
1 files changed, 0 insertions, 124 deletions
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106825.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106825.patch
deleted file mode 100644
index 13e6fd26e5..0000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106825.patch
+++ /dev/null
@@ -1,124 +0,0 @@
12011-10-13 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from mainline:
4
5 2011-10-07 Andrew Stubbs <ams@codesourcery.com>
6
7 gcc/
8 * config/arm/predicates.md (shift_amount_operand): Remove constant
9 range check.
10 (shift_operator): Check range of constants for all shift operators.
11
12 gcc/testsuite/
13 * gcc.dg/pr50193-1.c: New file.
14 * gcc.target/arm/shiftable.c: New file.
15
16=== modified file 'gcc/config/arm/predicates.md'
17--- old/gcc/config/arm/predicates.md 2011-10-03 09:47:33 +0000
18+++ new/gcc/config/arm/predicates.md 2011-10-10 11:43:28 +0000
19@@ -129,11 +129,12 @@
20 (ior (match_operand 0 "arm_rhs_operand")
21 (match_operand 0 "memory_operand")))
22
23+;; This doesn't have to do much because the constant is already checked
24+;; in the shift_operator predicate.
25 (define_predicate "shift_amount_operand"
26 (ior (and (match_test "TARGET_ARM")
27 (match_operand 0 "s_register_operand"))
28- (and (match_operand 0 "const_int_operand")
29- (match_test "INTVAL (op) > 0"))))
30+ (match_operand 0 "const_int_operand")))
31
32 (define_predicate "arm_add_operand"
33 (ior (match_operand 0 "arm_rhs_operand")
34@@ -219,13 +220,20 @@
35 (match_test "mode == GET_MODE (op)")))
36
37 ;; True for shift operators.
38+;; Notes:
39+;; * mult is only permitted with a constant shift amount
40+;; * patterns that permit register shift amounts only in ARM mode use
41+;; shift_amount_operand, patterns that always allow registers do not,
42+;; so we don't have to worry about that sort of thing here.
43 (define_special_predicate "shift_operator"
44 (and (ior (ior (and (match_code "mult")
45 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
46 (and (match_code "rotate")
47 (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
48 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
49- (match_code "ashift,ashiftrt,lshiftrt,rotatert"))
50+ (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
51+ (match_test "GET_CODE (XEXP (op, 1)) != CONST_INT
52+ || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
53 (match_test "mode == GET_MODE (op)")))
54
55 ;; True for MULT, to identify which variant of shift_operator is in use.
56
57=== added file 'gcc/testsuite/gcc.target/arm/shiftable.c'
58--- old/gcc/testsuite/gcc.target/arm/shiftable.c 1970-01-01 00:00:00 +0000
59+++ new/gcc/testsuite/gcc.target/arm/shiftable.c 2011-10-10 11:43:28 +0000
60@@ -0,0 +1,63 @@
61+/* { dg-do compile } */
62+/* { dg-options "-O2" } */
63+/* { dg-require-effective-target arm32 } */
64+
65+/* ARM has shift-and-alu insns. Depending on the ALU op GCC represents some
66+ of these as a left shift, others as a multiply. Check that we match the
67+ right one. */
68+
69+int
70+plus (int a, int b)
71+{
72+ return (a * 64) + b;
73+}
74+
75+/* { dg-final { scan-assembler "add.*\[al]sl #6" } } */
76+
77+int
78+minus (int a, int b)
79+{
80+ return a - (b * 64);
81+}
82+
83+/* { dg-final { scan-assembler "sub.*\[al]sl #6" } } */
84+
85+int
86+ior (int a, int b)
87+{
88+ return (a * 64) | b;
89+}
90+
91+/* { dg-final { scan-assembler "orr.*\[al]sl #6" } } */
92+
93+int
94+xor (int a, int b)
95+{
96+ return (a * 64) ^ b;
97+}
98+
99+/* { dg-final { scan-assembler "eor.*\[al]sl #6" } } */
100+
101+int
102+and (int a, int b)
103+{
104+ return (a * 64) & b;
105+}
106+
107+/* { dg-final { scan-assembler "and.*\[al]sl #6" } } */
108+
109+int
110+rsb (int a, int b)
111+{
112+ return (a * 64) - b;
113+}
114+
115+/* { dg-final { scan-assembler "rsb.*\[al]sl #6" } } */
116+
117+int
118+mvn (int a, int b)
119+{
120+ return ~(a * 64);
121+}
122+
123+/* { dg-final { scan-assembler "mvn.*\[al]sl #6" } } */
124