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| author | Nathan Rossi <nathan.rossi@xilinx.com> | 2015-04-13 15:52:27 +1000 |
|---|---|---|
| committer | Nathan Rossi <nathan.rossi@xilinx.com> | 2015-04-14 14:00:44 +1000 |
| commit | 684e1f46c8462a64b183a72b728bf8a0960d8a2d (patch) | |
| tree | 38d6eb4068bd0bdb3b5a479179cf1181ac789bc3 | |
| parent | cf91f7395b6fee681225c681b46df6b6b08f0395 (diff) | |
| download | meta-xilinx-684e1f46c8462a64b183a72b728bf8a0960d8a2d.tar.gz | |
platform-init: Add recipe for local platform init files
* Add local recipe for providing platform info files (ps7_init_gpl.[ch])
* Add local files for the zybo-zynq7 board
Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
3 files changed, 12119 insertions, 0 deletions
diff --git a/recipes-bsp/platform-init/platform-init.bb b/recipes-bsp/platform-init/platform-init.bb new file mode 100644 index 00000000..254a5566 --- /dev/null +++ b/recipes-bsp/platform-init/platform-init.bb | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | SUMMARY = "Xilinx Platform Headers" | ||
| 2 | DESCRPTION = "Xilinx ps7_init_gpl.c/h platform headers, used for building u-boot-spl and fsbl" | ||
| 3 | HOMEPAGE = "http://www.xilinx.com" | ||
| 4 | SECTION = "bsp" | ||
| 5 | |||
| 6 | include zynq7-platform-init.inc | ||
| 7 | |||
| 8 | COMPATIBLE_MACHINE = "$^" | ||
| 9 | COMPATIBLE_MACHINE_zybo-zynq7 = "zybo-zynq7" | ||
| 10 | |||
| 11 | LICENSE = "GPLv2+" | ||
| 12 | LIC_FILES_CHKSUM = "files://${COREBASE}/meta/files/common-licenses/GPL-2.0;md5=801f80980d171dd6425610833a22dbe6" | ||
| 13 | |||
| 14 | SRC_URI = "file://ps7_init_gpl.c file://ps7_init_gpl.h" | ||
| 15 | |||
| 16 | S = "${WORKDIR}" | ||
| 17 | |||
| 18 | do_install_append() { | ||
| 19 | install -m 0644 ${S}/ps7_init_gpl.c ${D}${PLATFORM_INIT_DIR}/ | ||
| 20 | install -m 0644 ${S}/ps7_init_gpl.h ${D}${PLATFORM_INIT_DIR}/ | ||
| 21 | } | ||
| 22 | |||
diff --git a/recipes-bsp/platform-init/platform-init/zybo-zynq7/ps7_init_gpl.c b/recipes-bsp/platform-init/platform-init/zybo-zynq7/ps7_init_gpl.c new file mode 100644 index 00000000..156c930c --- /dev/null +++ b/recipes-bsp/platform-init/platform-init/zybo-zynq7/ps7_init_gpl.c | |||
| @@ -0,0 +1,11967 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, see <http://www.gnu.org/licenses/> | ||
| 16 | * | ||
| 17 | * | ||
| 18 | ******************************************************************************/ | ||
| 19 | /****************************************************************************/ | ||
| 20 | /** | ||
| 21 | * | ||
| 22 | * @file ps7_init_gpl.c | ||
| 23 | * | ||
| 24 | * This file is automatically generated | ||
| 25 | * | ||
| 26 | *****************************************************************************/ | ||
| 27 | |||
| 28 | #include "ps7_init_gpl.h" | ||
| 29 | |||
| 30 | unsigned long ps7_pll_init_data_3_0[] = { | ||
| 31 | // START: top | ||
| 32 | // .. START: SLCR SETTINGS | ||
| 33 | // .. UNLOCK_KEY = 0XDF0D | ||
| 34 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
| 35 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
| 36 | // .. | ||
| 37 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
| 38 | // .. FINISH: SLCR SETTINGS | ||
| 39 | // .. START: PLL SLCR REGISTERS | ||
| 40 | // .. .. START: ARM PLL INIT | ||
| 41 | // .. .. PLL_RES = 0xc | ||
| 42 | // .. .. ==> 0XF8000110[7:4] = 0x0000000CU | ||
| 43 | // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U | ||
| 44 | // .. .. PLL_CP = 0x2 | ||
| 45 | // .. .. ==> 0XF8000110[11:8] = 0x00000002U | ||
| 46 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
| 47 | // .. .. LOCK_CNT = 0x177 | ||
| 48 | // .. .. ==> 0XF8000110[21:12] = 0x00000177U | ||
| 49 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U | ||
| 50 | // .. .. | ||
| 51 | EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U), | ||
| 52 | // .. .. .. START: UPDATE FB_DIV | ||
| 53 | // .. .. .. PLL_FDIV = 0x1a | ||
| 54 | // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU | ||
| 55 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U | ||
| 56 | // .. .. .. | ||
| 57 | EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U), | ||
| 58 | // .. .. .. FINISH: UPDATE FB_DIV | ||
| 59 | // .. .. .. START: BY PASS PLL | ||
| 60 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
| 61 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U | ||
| 62 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 63 | // .. .. .. | ||
| 64 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), | ||
| 65 | // .. .. .. FINISH: BY PASS PLL | ||
| 66 | // .. .. .. START: ASSERT RESET | ||
| 67 | // .. .. .. PLL_RESET = 1 | ||
| 68 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U | ||
| 69 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 70 | // .. .. .. | ||
| 71 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), | ||
| 72 | // .. .. .. FINISH: ASSERT RESET | ||
| 73 | // .. .. .. START: DEASSERT RESET | ||
| 74 | // .. .. .. PLL_RESET = 0 | ||
| 75 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U | ||
| 76 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 77 | // .. .. .. | ||
| 78 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), | ||
| 79 | // .. .. .. FINISH: DEASSERT RESET | ||
| 80 | // .. .. .. START: CHECK PLL STATUS | ||
| 81 | // .. .. .. ARM_PLL_LOCK = 1 | ||
| 82 | // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U | ||
| 83 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 84 | // .. .. .. | ||
| 85 | EMIT_MASKPOLL(0XF800010C, 0x00000001U), | ||
| 86 | // .. .. .. FINISH: CHECK PLL STATUS | ||
| 87 | // .. .. .. START: REMOVE PLL BY PASS | ||
| 88 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
| 89 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U | ||
| 90 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 91 | // .. .. .. | ||
| 92 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), | ||
| 93 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
| 94 | // .. .. .. SRCSEL = 0x0 | ||
| 95 | // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U | ||
| 96 | // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 97 | // .. .. .. DIVISOR = 0x2 | ||
| 98 | // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U | ||
| 99 | // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U | ||
| 100 | // .. .. .. CPU_6OR4XCLKACT = 0x1 | ||
| 101 | // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U | ||
| 102 | // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U | ||
| 103 | // .. .. .. CPU_3OR2XCLKACT = 0x1 | ||
| 104 | // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U | ||
| 105 | // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U | ||
| 106 | // .. .. .. CPU_2XCLKACT = 0x1 | ||
| 107 | // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U | ||
| 108 | // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | ||
| 109 | // .. .. .. CPU_1XCLKACT = 0x1 | ||
| 110 | // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U | ||
| 111 | // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | ||
| 112 | // .. .. .. CPU_PERI_CLKACT = 0x1 | ||
| 113 | // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U | ||
| 114 | // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | ||
| 115 | // .. .. .. | ||
| 116 | EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), | ||
| 117 | // .. .. FINISH: ARM PLL INIT | ||
| 118 | // .. .. START: DDR PLL INIT | ||
| 119 | // .. .. PLL_RES = 0xc | ||
| 120 | // .. .. ==> 0XF8000114[7:4] = 0x0000000CU | ||
| 121 | // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U | ||
| 122 | // .. .. PLL_CP = 0x2 | ||
| 123 | // .. .. ==> 0XF8000114[11:8] = 0x00000002U | ||
| 124 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
| 125 | // .. .. LOCK_CNT = 0x1db | ||
| 126 | // .. .. ==> 0XF8000114[21:12] = 0x000001DBU | ||
| 127 | // .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U | ||
| 128 | // .. .. | ||
| 129 | EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U), | ||
| 130 | // .. .. .. START: UPDATE FB_DIV | ||
| 131 | // .. .. .. PLL_FDIV = 0x15 | ||
| 132 | // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U | ||
| 133 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U | ||
| 134 | // .. .. .. | ||
| 135 | EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U), | ||
| 136 | // .. .. .. FINISH: UPDATE FB_DIV | ||
| 137 | // .. .. .. START: BY PASS PLL | ||
| 138 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
| 139 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U | ||
| 140 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 141 | // .. .. .. | ||
| 142 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), | ||
| 143 | // .. .. .. FINISH: BY PASS PLL | ||
| 144 | // .. .. .. START: ASSERT RESET | ||
| 145 | // .. .. .. PLL_RESET = 1 | ||
| 146 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U | ||
| 147 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 148 | // .. .. .. | ||
| 149 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), | ||
| 150 | // .. .. .. FINISH: ASSERT RESET | ||
| 151 | // .. .. .. START: DEASSERT RESET | ||
| 152 | // .. .. .. PLL_RESET = 0 | ||
| 153 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U | ||
| 154 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 155 | // .. .. .. | ||
| 156 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), | ||
| 157 | // .. .. .. FINISH: DEASSERT RESET | ||
| 158 | // .. .. .. START: CHECK PLL STATUS | ||
| 159 | // .. .. .. DDR_PLL_LOCK = 1 | ||
| 160 | // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U | ||
| 161 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 162 | // .. .. .. | ||
| 163 | EMIT_MASKPOLL(0XF800010C, 0x00000002U), | ||
| 164 | // .. .. .. FINISH: CHECK PLL STATUS | ||
| 165 | // .. .. .. START: REMOVE PLL BY PASS | ||
| 166 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
| 167 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U | ||
| 168 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 169 | // .. .. .. | ||
| 170 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), | ||
| 171 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
| 172 | // .. .. .. DDR_3XCLKACT = 0x1 | ||
| 173 | // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U | ||
| 174 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 175 | // .. .. .. DDR_2XCLKACT = 0x1 | ||
| 176 | // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U | ||
| 177 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 178 | // .. .. .. DDR_3XCLK_DIVISOR = 0x2 | ||
| 179 | // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U | ||
| 180 | // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U | ||
| 181 | // .. .. .. DDR_2XCLK_DIVISOR = 0x3 | ||
| 182 | // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U | ||
| 183 | // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U | ||
| 184 | // .. .. .. | ||
| 185 | EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), | ||
| 186 | // .. .. FINISH: DDR PLL INIT | ||
| 187 | // .. .. START: IO PLL INIT | ||
| 188 | // .. .. PLL_RES = 0xc | ||
| 189 | // .. .. ==> 0XF8000118[7:4] = 0x0000000CU | ||
| 190 | // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U | ||
| 191 | // .. .. PLL_CP = 0x2 | ||
| 192 | // .. .. ==> 0XF8000118[11:8] = 0x00000002U | ||
| 193 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
| 194 | // .. .. LOCK_CNT = 0x1f4 | ||
| 195 | // .. .. ==> 0XF8000118[21:12] = 0x000001F4U | ||
| 196 | // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U | ||
| 197 | // .. .. | ||
| 198 | EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U), | ||
| 199 | // .. .. .. START: UPDATE FB_DIV | ||
| 200 | // .. .. .. PLL_FDIV = 0x14 | ||
| 201 | // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U | ||
| 202 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U | ||
| 203 | // .. .. .. | ||
| 204 | EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U), | ||
| 205 | // .. .. .. FINISH: UPDATE FB_DIV | ||
| 206 | // .. .. .. START: BY PASS PLL | ||
| 207 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
| 208 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U | ||
| 209 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 210 | // .. .. .. | ||
| 211 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), | ||
| 212 | // .. .. .. FINISH: BY PASS PLL | ||
| 213 | // .. .. .. START: ASSERT RESET | ||
| 214 | // .. .. .. PLL_RESET = 1 | ||
| 215 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U | ||
| 216 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 217 | // .. .. .. | ||
| 218 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), | ||
| 219 | // .. .. .. FINISH: ASSERT RESET | ||
| 220 | // .. .. .. START: DEASSERT RESET | ||
| 221 | // .. .. .. PLL_RESET = 0 | ||
| 222 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U | ||
| 223 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 224 | // .. .. .. | ||
| 225 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), | ||
| 226 | // .. .. .. FINISH: DEASSERT RESET | ||
| 227 | // .. .. .. START: CHECK PLL STATUS | ||
| 228 | // .. .. .. IO_PLL_LOCK = 1 | ||
| 229 | // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U | ||
| 230 | // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 231 | // .. .. .. | ||
| 232 | EMIT_MASKPOLL(0XF800010C, 0x00000004U), | ||
| 233 | // .. .. .. FINISH: CHECK PLL STATUS | ||
| 234 | // .. .. .. START: REMOVE PLL BY PASS | ||
| 235 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
| 236 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U | ||
| 237 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 238 | // .. .. .. | ||
| 239 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), | ||
| 240 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
| 241 | // .. .. FINISH: IO PLL INIT | ||
| 242 | // .. FINISH: PLL SLCR REGISTERS | ||
| 243 | // .. START: LOCK IT BACK | ||
| 244 | // .. LOCK_KEY = 0X767B | ||
| 245 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
| 246 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
| 247 | // .. | ||
| 248 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
| 249 | // .. FINISH: LOCK IT BACK | ||
| 250 | // FINISH: top | ||
| 251 | // | ||
| 252 | EMIT_EXIT(), | ||
| 253 | |||
| 254 | // | ||
| 255 | }; | ||
| 256 | |||
| 257 | unsigned long ps7_clock_init_data_3_0[] = { | ||
| 258 | // START: top | ||
| 259 | // .. START: SLCR SETTINGS | ||
| 260 | // .. UNLOCK_KEY = 0XDF0D | ||
| 261 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
| 262 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
| 263 | // .. | ||
| 264 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
| 265 | // .. FINISH: SLCR SETTINGS | ||
| 266 | // .. START: CLOCK CONTROL SLCR REGISTERS | ||
| 267 | // .. CLKACT = 0x1 | ||
| 268 | // .. ==> 0XF8000128[0:0] = 0x00000001U | ||
| 269 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 270 | // .. DIVISOR0 = 0x34 | ||
| 271 | // .. ==> 0XF8000128[13:8] = 0x00000034U | ||
| 272 | // .. ==> MASK : 0x00003F00U VAL : 0x00003400U | ||
| 273 | // .. DIVISOR1 = 0x2 | ||
| 274 | // .. ==> 0XF8000128[25:20] = 0x00000002U | ||
| 275 | // .. ==> MASK : 0x03F00000U VAL : 0x00200000U | ||
| 276 | // .. | ||
| 277 | EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U), | ||
| 278 | // .. CLKACT = 0x1 | ||
| 279 | // .. ==> 0XF8000138[0:0] = 0x00000001U | ||
| 280 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 281 | // .. SRCSEL = 0x0 | ||
| 282 | // .. ==> 0XF8000138[4:4] = 0x00000000U | ||
| 283 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 284 | // .. | ||
| 285 | EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), | ||
| 286 | // .. CLKACT = 0x1 | ||
| 287 | // .. ==> 0XF8000140[0:0] = 0x00000001U | ||
| 288 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 289 | // .. SRCSEL = 0x0 | ||
| 290 | // .. ==> 0XF8000140[6:4] = 0x00000000U | ||
| 291 | // .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
| 292 | // .. DIVISOR = 0x8 | ||
| 293 | // .. ==> 0XF8000140[13:8] = 0x00000008U | ||
| 294 | // .. ==> MASK : 0x00003F00U VAL : 0x00000800U | ||
| 295 | // .. DIVISOR1 = 0x1 | ||
| 296 | // .. ==> 0XF8000140[25:20] = 0x00000001U | ||
| 297 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
| 298 | // .. | ||
| 299 | EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), | ||
| 300 | // .. CLKACT = 0x1 | ||
| 301 | // .. ==> 0XF800014C[0:0] = 0x00000001U | ||
| 302 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 303 | // .. SRCSEL = 0x0 | ||
| 304 | // .. ==> 0XF800014C[5:4] = 0x00000000U | ||
| 305 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 306 | // .. DIVISOR = 0x5 | ||
| 307 | // .. ==> 0XF800014C[13:8] = 0x00000005U | ||
| 308 | // .. ==> MASK : 0x00003F00U VAL : 0x00000500U | ||
| 309 | // .. | ||
| 310 | EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), | ||
| 311 | // .. CLKACT0 = 0x1 | ||
| 312 | // .. ==> 0XF8000150[0:0] = 0x00000001U | ||
| 313 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 314 | // .. CLKACT1 = 0x0 | ||
| 315 | // .. ==> 0XF8000150[1:1] = 0x00000000U | ||
| 316 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 317 | // .. SRCSEL = 0x0 | ||
| 318 | // .. ==> 0XF8000150[5:4] = 0x00000000U | ||
| 319 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 320 | // .. DIVISOR = 0x14 | ||
| 321 | // .. ==> 0XF8000150[13:8] = 0x00000014U | ||
| 322 | // .. ==> MASK : 0x00003F00U VAL : 0x00001400U | ||
| 323 | // .. | ||
| 324 | EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), | ||
| 325 | // .. CLKACT0 = 0x0 | ||
| 326 | // .. ==> 0XF8000154[0:0] = 0x00000000U | ||
| 327 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 328 | // .. CLKACT1 = 0x1 | ||
| 329 | // .. ==> 0XF8000154[1:1] = 0x00000001U | ||
| 330 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 331 | // .. SRCSEL = 0x0 | ||
| 332 | // .. ==> 0XF8000154[5:4] = 0x00000000U | ||
| 333 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 334 | // .. DIVISOR = 0x14 | ||
| 335 | // .. ==> 0XF8000154[13:8] = 0x00000014U | ||
| 336 | // .. ==> MASK : 0x00003F00U VAL : 0x00001400U | ||
| 337 | // .. | ||
| 338 | EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), | ||
| 339 | // .. .. START: TRACE CLOCK | ||
| 340 | // .. .. FINISH: TRACE CLOCK | ||
| 341 | // .. .. CLKACT = 0x1 | ||
| 342 | // .. .. ==> 0XF8000168[0:0] = 0x00000001U | ||
| 343 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 344 | // .. .. SRCSEL = 0x0 | ||
| 345 | // .. .. ==> 0XF8000168[5:4] = 0x00000000U | ||
| 346 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 347 | // .. .. DIVISOR = 0x5 | ||
| 348 | // .. .. ==> 0XF8000168[13:8] = 0x00000005U | ||
| 349 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U | ||
| 350 | // .. .. | ||
| 351 | EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), | ||
| 352 | // .. .. SRCSEL = 0x0 | ||
| 353 | // .. .. ==> 0XF8000170[5:4] = 0x00000000U | ||
| 354 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 355 | // .. .. DIVISOR0 = 0xa | ||
| 356 | // .. .. ==> 0XF8000170[13:8] = 0x0000000AU | ||
| 357 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | ||
| 358 | // .. .. DIVISOR1 = 0x1 | ||
| 359 | // .. .. ==> 0XF8000170[25:20] = 0x00000001U | ||
| 360 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
| 361 | // .. .. | ||
| 362 | EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), | ||
| 363 | // .. .. SRCSEL = 0x3 | ||
| 364 | // .. .. ==> 0XF8000180[5:4] = 0x00000003U | ||
| 365 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000030U | ||
| 366 | // .. .. DIVISOR0 = 0x6 | ||
| 367 | // .. .. ==> 0XF8000180[13:8] = 0x00000006U | ||
| 368 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U | ||
| 369 | // .. .. DIVISOR1 = 0x1 | ||
| 370 | // .. .. ==> 0XF8000180[25:20] = 0x00000001U | ||
| 371 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
| 372 | // .. .. | ||
| 373 | EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100630U), | ||
| 374 | // .. .. SRCSEL = 0x2 | ||
| 375 | // .. .. ==> 0XF8000190[5:4] = 0x00000002U | ||
| 376 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000020U | ||
| 377 | // .. .. DIVISOR0 = 0x35 | ||
| 378 | // .. .. ==> 0XF8000190[13:8] = 0x00000035U | ||
| 379 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U | ||
| 380 | // .. .. DIVISOR1 = 0x2 | ||
| 381 | // .. .. ==> 0XF8000190[25:20] = 0x00000002U | ||
| 382 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U | ||
| 383 | // .. .. | ||
| 384 | EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00203520U), | ||
| 385 | // .. .. SRCSEL = 0x0 | ||
| 386 | // .. .. ==> 0XF80001A0[5:4] = 0x00000000U | ||
| 387 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 388 | // .. .. DIVISOR0 = 0xa | ||
| 389 | // .. .. ==> 0XF80001A0[13:8] = 0x0000000AU | ||
| 390 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | ||
| 391 | // .. .. DIVISOR1 = 0x1 | ||
| 392 | // .. .. ==> 0XF80001A0[25:20] = 0x00000001U | ||
| 393 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
| 394 | // .. .. | ||
| 395 | EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100A00U), | ||
| 396 | // .. .. CLK_621_TRUE = 0x1 | ||
| 397 | // .. .. ==> 0XF80001C4[0:0] = 0x00000001U | ||
| 398 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 399 | // .. .. | ||
| 400 | EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), | ||
| 401 | // .. .. DMA_CPU_2XCLKACT = 0x1 | ||
| 402 | // .. .. ==> 0XF800012C[0:0] = 0x00000001U | ||
| 403 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 404 | // .. .. USB0_CPU_1XCLKACT = 0x1 | ||
| 405 | // .. .. ==> 0XF800012C[2:2] = 0x00000001U | ||
| 406 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 407 | // .. .. USB1_CPU_1XCLKACT = 0x1 | ||
| 408 | // .. .. ==> 0XF800012C[3:3] = 0x00000001U | ||
| 409 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U | ||
| 410 | // .. .. GEM0_CPU_1XCLKACT = 0x1 | ||
| 411 | // .. .. ==> 0XF800012C[6:6] = 0x00000001U | ||
| 412 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U | ||
| 413 | // .. .. GEM1_CPU_1XCLKACT = 0x0 | ||
| 414 | // .. .. ==> 0XF800012C[7:7] = 0x00000000U | ||
| 415 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 416 | // .. .. SDI0_CPU_1XCLKACT = 0x1 | ||
| 417 | // .. .. ==> 0XF800012C[10:10] = 0x00000001U | ||
| 418 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U | ||
| 419 | // .. .. SDI1_CPU_1XCLKACT = 0x0 | ||
| 420 | // .. .. ==> 0XF800012C[11:11] = 0x00000000U | ||
| 421 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 422 | // .. .. SPI0_CPU_1XCLKACT = 0x0 | ||
| 423 | // .. .. ==> 0XF800012C[14:14] = 0x00000000U | ||
| 424 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
| 425 | // .. .. SPI1_CPU_1XCLKACT = 0x0 | ||
| 426 | // .. .. ==> 0XF800012C[15:15] = 0x00000000U | ||
| 427 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
| 428 | // .. .. CAN0_CPU_1XCLKACT = 0x0 | ||
| 429 | // .. .. ==> 0XF800012C[16:16] = 0x00000000U | ||
| 430 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 431 | // .. .. CAN1_CPU_1XCLKACT = 0x0 | ||
| 432 | // .. .. ==> 0XF800012C[17:17] = 0x00000000U | ||
| 433 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 434 | // .. .. I2C0_CPU_1XCLKACT = 0x1 | ||
| 435 | // .. .. ==> 0XF800012C[18:18] = 0x00000001U | ||
| 436 | // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U | ||
| 437 | // .. .. I2C1_CPU_1XCLKACT = 0x1 | ||
| 438 | // .. .. ==> 0XF800012C[19:19] = 0x00000001U | ||
| 439 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
| 440 | // .. .. UART0_CPU_1XCLKACT = 0x0 | ||
| 441 | // .. .. ==> 0XF800012C[20:20] = 0x00000000U | ||
| 442 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
| 443 | // .. .. UART1_CPU_1XCLKACT = 0x1 | ||
| 444 | // .. .. ==> 0XF800012C[21:21] = 0x00000001U | ||
| 445 | // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U | ||
| 446 | // .. .. GPIO_CPU_1XCLKACT = 0x1 | ||
| 447 | // .. .. ==> 0XF800012C[22:22] = 0x00000001U | ||
| 448 | // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U | ||
| 449 | // .. .. LQSPI_CPU_1XCLKACT = 0x1 | ||
| 450 | // .. .. ==> 0XF800012C[23:23] = 0x00000001U | ||
| 451 | // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U | ||
| 452 | // .. .. SMC_CPU_1XCLKACT = 0x1 | ||
| 453 | // .. .. ==> 0XF800012C[24:24] = 0x00000001U | ||
| 454 | // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U | ||
| 455 | // .. .. | ||
| 456 | EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), | ||
| 457 | // .. FINISH: CLOCK CONTROL SLCR REGISTERS | ||
| 458 | // .. START: THIS SHOULD BE BLANK | ||
| 459 | // .. FINISH: THIS SHOULD BE BLANK | ||
| 460 | // .. START: LOCK IT BACK | ||
| 461 | // .. LOCK_KEY = 0X767B | ||
| 462 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
| 463 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
| 464 | // .. | ||
| 465 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
| 466 | // .. FINISH: LOCK IT BACK | ||
| 467 | // FINISH: top | ||
| 468 | // | ||
| 469 | EMIT_EXIT(), | ||
| 470 | |||
| 471 | // | ||
| 472 | }; | ||
| 473 | |||
| 474 | unsigned long ps7_ddr_init_data_3_0[] = { | ||
| 475 | // START: top | ||
| 476 | // .. START: DDR INITIALIZATION | ||
| 477 | // .. .. START: LOCK DDR | ||
| 478 | // .. .. reg_ddrc_soft_rstb = 0 | ||
| 479 | // .. .. ==> 0XF8006000[0:0] = 0x00000000U | ||
| 480 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 481 | // .. .. reg_ddrc_powerdown_en = 0x0 | ||
| 482 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | ||
| 483 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 484 | // .. .. reg_ddrc_data_bus_width = 0x0 | ||
| 485 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | ||
| 486 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | ||
| 487 | // .. .. reg_ddrc_burst8_refresh = 0x0 | ||
| 488 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | ||
| 489 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
| 490 | // .. .. reg_ddrc_rdwr_idle_gap = 0x1 | ||
| 491 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | ||
| 492 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | ||
| 493 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | ||
| 494 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | ||
| 495 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
| 496 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | ||
| 497 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | ||
| 498 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
| 499 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | ||
| 500 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | ||
| 501 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 502 | // .. .. | ||
| 503 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), | ||
| 504 | // .. .. FINISH: LOCK DDR | ||
| 505 | // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f | ||
| 506 | // .. .. ==> 0XF8006004[11:0] = 0x0000007FU | ||
| 507 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU | ||
| 508 | // .. .. reserved_reg_ddrc_active_ranks = 0x1 | ||
| 509 | // .. .. ==> 0XF8006004[13:12] = 0x00000001U | ||
| 510 | // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U | ||
| 511 | // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 | ||
| 512 | // .. .. ==> 0XF8006004[18:14] = 0x00000000U | ||
| 513 | // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U | ||
| 514 | // .. .. | ||
| 515 | EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x0000107FU), | ||
| 516 | // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf | ||
| 517 | // .. .. ==> 0XF8006008[10:0] = 0x0000000FU | ||
| 518 | // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU | ||
| 519 | // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf | ||
| 520 | // .. .. ==> 0XF8006008[21:11] = 0x0000000FU | ||
| 521 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U | ||
| 522 | // .. .. reg_ddrc_hpr_xact_run_length = 0xf | ||
| 523 | // .. .. ==> 0XF8006008[25:22] = 0x0000000FU | ||
| 524 | // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U | ||
| 525 | // .. .. | ||
| 526 | EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), | ||
| 527 | // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 | ||
| 528 | // .. .. ==> 0XF800600C[10:0] = 0x00000001U | ||
| 529 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | ||
| 530 | // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 | ||
| 531 | // .. .. ==> 0XF800600C[21:11] = 0x00000002U | ||
| 532 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U | ||
| 533 | // .. .. reg_ddrc_lpr_xact_run_length = 0x8 | ||
| 534 | // .. .. ==> 0XF800600C[25:22] = 0x00000008U | ||
| 535 | // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U | ||
| 536 | // .. .. | ||
| 537 | EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), | ||
| 538 | // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 | ||
| 539 | // .. .. ==> 0XF8006010[10:0] = 0x00000001U | ||
| 540 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | ||
| 541 | // .. .. reg_ddrc_w_xact_run_length = 0x8 | ||
| 542 | // .. .. ==> 0XF8006010[14:11] = 0x00000008U | ||
| 543 | // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U | ||
| 544 | // .. .. reg_ddrc_w_max_starve_x32 = 0x2 | ||
| 545 | // .. .. ==> 0XF8006010[25:15] = 0x00000002U | ||
| 546 | // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U | ||
| 547 | // .. .. | ||
| 548 | EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), | ||
| 549 | // .. .. reg_ddrc_t_rc = 0x1a | ||
| 550 | // .. .. ==> 0XF8006014[5:0] = 0x0000001AU | ||
| 551 | // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU | ||
| 552 | // .. .. reg_ddrc_t_rfc_min = 0x54 | ||
| 553 | // .. .. ==> 0XF8006014[13:6] = 0x00000054U | ||
| 554 | // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U | ||
| 555 | // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 | ||
| 556 | // .. .. ==> 0XF8006014[20:14] = 0x00000010U | ||
| 557 | // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U | ||
| 558 | // .. .. | ||
| 559 | EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU), | ||
| 560 | // .. .. reg_ddrc_wr2pre = 0x12 | ||
| 561 | // .. .. ==> 0XF8006018[4:0] = 0x00000012U | ||
| 562 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U | ||
| 563 | // .. .. reg_ddrc_powerdown_to_x32 = 0x6 | ||
| 564 | // .. .. ==> 0XF8006018[9:5] = 0x00000006U | ||
| 565 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U | ||
| 566 | // .. .. reg_ddrc_t_faw = 0x15 | ||
| 567 | // .. .. ==> 0XF8006018[15:10] = 0x00000015U | ||
| 568 | // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U | ||
| 569 | // .. .. reg_ddrc_t_ras_max = 0x23 | ||
| 570 | // .. .. ==> 0XF8006018[21:16] = 0x00000023U | ||
| 571 | // .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U | ||
| 572 | // .. .. reg_ddrc_t_ras_min = 0x13 | ||
| 573 | // .. .. ==> 0XF8006018[26:22] = 0x00000013U | ||
| 574 | // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U | ||
| 575 | // .. .. reg_ddrc_t_cke = 0x4 | ||
| 576 | // .. .. ==> 0XF8006018[31:28] = 0x00000004U | ||
| 577 | // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U | ||
| 578 | // .. .. | ||
| 579 | EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U), | ||
| 580 | // .. .. reg_ddrc_write_latency = 0x5 | ||
| 581 | // .. .. ==> 0XF800601C[4:0] = 0x00000005U | ||
| 582 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U | ||
| 583 | // .. .. reg_ddrc_rd2wr = 0x7 | ||
| 584 | // .. .. ==> 0XF800601C[9:5] = 0x00000007U | ||
| 585 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U | ||
| 586 | // .. .. reg_ddrc_wr2rd = 0xe | ||
| 587 | // .. .. ==> 0XF800601C[14:10] = 0x0000000EU | ||
| 588 | // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U | ||
| 589 | // .. .. reg_ddrc_t_xp = 0x4 | ||
| 590 | // .. .. ==> 0XF800601C[19:15] = 0x00000004U | ||
| 591 | // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U | ||
| 592 | // .. .. reg_ddrc_pad_pd = 0x0 | ||
| 593 | // .. .. ==> 0XF800601C[22:20] = 0x00000000U | ||
| 594 | // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U | ||
| 595 | // .. .. reg_ddrc_rd2pre = 0x4 | ||
| 596 | // .. .. ==> 0XF800601C[27:23] = 0x00000004U | ||
| 597 | // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U | ||
| 598 | // .. .. reg_ddrc_t_rcd = 0x7 | ||
| 599 | // .. .. ==> 0XF800601C[31:28] = 0x00000007U | ||
| 600 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | ||
| 601 | // .. .. | ||
| 602 | EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), | ||
| 603 | // .. .. reg_ddrc_t_ccd = 0x4 | ||
| 604 | // .. .. ==> 0XF8006020[4:2] = 0x00000004U | ||
| 605 | // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U | ||
| 606 | // .. .. reg_ddrc_t_rrd = 0x6 | ||
| 607 | // .. .. ==> 0XF8006020[7:5] = 0x00000006U | ||
| 608 | // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U | ||
| 609 | // .. .. reg_ddrc_refresh_margin = 0x2 | ||
| 610 | // .. .. ==> 0XF8006020[11:8] = 0x00000002U | ||
| 611 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
| 612 | // .. .. reg_ddrc_t_rp = 0x7 | ||
| 613 | // .. .. ==> 0XF8006020[15:12] = 0x00000007U | ||
| 614 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U | ||
| 615 | // .. .. reg_ddrc_refresh_to_x32 = 0x8 | ||
| 616 | // .. .. ==> 0XF8006020[20:16] = 0x00000008U | ||
| 617 | // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U | ||
| 618 | // .. .. reg_ddrc_mobile = 0x0 | ||
| 619 | // .. .. ==> 0XF8006020[22:22] = 0x00000000U | ||
| 620 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
| 621 | // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 | ||
| 622 | // .. .. ==> 0XF8006020[23:23] = 0x00000000U | ||
| 623 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
| 624 | // .. .. reg_ddrc_read_latency = 0x7 | ||
| 625 | // .. .. ==> 0XF8006020[28:24] = 0x00000007U | ||
| 626 | // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U | ||
| 627 | // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 | ||
| 628 | // .. .. ==> 0XF8006020[29:29] = 0x00000001U | ||
| 629 | // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U | ||
| 630 | // .. .. reg_ddrc_dis_pad_pd = 0x0 | ||
| 631 | // .. .. ==> 0XF8006020[30:30] = 0x00000000U | ||
| 632 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | ||
| 633 | // .. .. | ||
| 634 | EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), | ||
| 635 | // .. .. reg_ddrc_en_2t_timing_mode = 0x0 | ||
| 636 | // .. .. ==> 0XF8006024[0:0] = 0x00000000U | ||
| 637 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 638 | // .. .. reg_ddrc_prefer_write = 0x0 | ||
| 639 | // .. .. ==> 0XF8006024[1:1] = 0x00000000U | ||
| 640 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 641 | // .. .. reg_ddrc_mr_wr = 0x0 | ||
| 642 | // .. .. ==> 0XF8006024[6:6] = 0x00000000U | ||
| 643 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U | ||
| 644 | // .. .. reg_ddrc_mr_addr = 0x0 | ||
| 645 | // .. .. ==> 0XF8006024[8:7] = 0x00000000U | ||
| 646 | // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U | ||
| 647 | // .. .. reg_ddrc_mr_data = 0x0 | ||
| 648 | // .. .. ==> 0XF8006024[24:9] = 0x00000000U | ||
| 649 | // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U | ||
| 650 | // .. .. ddrc_reg_mr_wr_busy = 0x0 | ||
| 651 | // .. .. ==> 0XF8006024[25:25] = 0x00000000U | ||
| 652 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
| 653 | // .. .. reg_ddrc_mr_type = 0x0 | ||
| 654 | // .. .. ==> 0XF8006024[26:26] = 0x00000000U | ||
| 655 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | ||
| 656 | // .. .. reg_ddrc_mr_rdata_valid = 0x0 | ||
| 657 | // .. .. ==> 0XF8006024[27:27] = 0x00000000U | ||
| 658 | // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U | ||
| 659 | // .. .. | ||
| 660 | EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), | ||
| 661 | // .. .. reg_ddrc_final_wait_x32 = 0x7 | ||
| 662 | // .. .. ==> 0XF8006028[6:0] = 0x00000007U | ||
| 663 | // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U | ||
| 664 | // .. .. reg_ddrc_pre_ocd_x32 = 0x0 | ||
| 665 | // .. .. ==> 0XF8006028[10:7] = 0x00000000U | ||
| 666 | // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U | ||
| 667 | // .. .. reg_ddrc_t_mrd = 0x4 | ||
| 668 | // .. .. ==> 0XF8006028[13:11] = 0x00000004U | ||
| 669 | // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U | ||
| 670 | // .. .. | ||
| 671 | EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), | ||
| 672 | // .. .. reg_ddrc_emr2 = 0x8 | ||
| 673 | // .. .. ==> 0XF800602C[15:0] = 0x00000008U | ||
| 674 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U | ||
| 675 | // .. .. reg_ddrc_emr3 = 0x0 | ||
| 676 | // .. .. ==> 0XF800602C[31:16] = 0x00000000U | ||
| 677 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U | ||
| 678 | // .. .. | ||
| 679 | EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), | ||
| 680 | // .. .. reg_ddrc_mr = 0x930 | ||
| 681 | // .. .. ==> 0XF8006030[15:0] = 0x00000930U | ||
| 682 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U | ||
| 683 | // .. .. reg_ddrc_emr = 0x4 | ||
| 684 | // .. .. ==> 0XF8006030[31:16] = 0x00000004U | ||
| 685 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U | ||
| 686 | // .. .. | ||
| 687 | EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), | ||
| 688 | // .. .. reg_ddrc_burst_rdwr = 0x4 | ||
| 689 | // .. .. ==> 0XF8006034[3:0] = 0x00000004U | ||
| 690 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U | ||
| 691 | // .. .. reg_ddrc_pre_cke_x1024 = 0x101 | ||
| 692 | // .. .. ==> 0XF8006034[13:4] = 0x00000101U | ||
| 693 | // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U | ||
| 694 | // .. .. reg_ddrc_post_cke_x1024 = 0x1 | ||
| 695 | // .. .. ==> 0XF8006034[25:16] = 0x00000001U | ||
| 696 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U | ||
| 697 | // .. .. reg_ddrc_burstchop = 0x0 | ||
| 698 | // .. .. ==> 0XF8006034[28:28] = 0x00000000U | ||
| 699 | // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U | ||
| 700 | // .. .. | ||
| 701 | EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011014U), | ||
| 702 | // .. .. reg_ddrc_force_low_pri_n = 0x0 | ||
| 703 | // .. .. ==> 0XF8006038[0:0] = 0x00000000U | ||
| 704 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 705 | // .. .. reg_ddrc_dis_dq = 0x0 | ||
| 706 | // .. .. ==> 0XF8006038[1:1] = 0x00000000U | ||
| 707 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 708 | // .. .. | ||
| 709 | EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), | ||
| 710 | // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 | ||
| 711 | // .. .. ==> 0XF800603C[3:0] = 0x00000007U | ||
| 712 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U | ||
| 713 | // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 | ||
| 714 | // .. .. ==> 0XF800603C[7:4] = 0x00000007U | ||
| 715 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U | ||
| 716 | // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 | ||
| 717 | // .. .. ==> 0XF800603C[11:8] = 0x00000007U | ||
| 718 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U | ||
| 719 | // .. .. reg_ddrc_addrmap_col_b5 = 0x0 | ||
| 720 | // .. .. ==> 0XF800603C[15:12] = 0x00000000U | ||
| 721 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | ||
| 722 | // .. .. reg_ddrc_addrmap_col_b6 = 0x0 | ||
| 723 | // .. .. ==> 0XF800603C[19:16] = 0x00000000U | ||
| 724 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | ||
| 725 | // .. .. | ||
| 726 | EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), | ||
| 727 | // .. .. reg_ddrc_addrmap_col_b2 = 0x0 | ||
| 728 | // .. .. ==> 0XF8006040[3:0] = 0x00000000U | ||
| 729 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
| 730 | // .. .. reg_ddrc_addrmap_col_b3 = 0x0 | ||
| 731 | // .. .. ==> 0XF8006040[7:4] = 0x00000000U | ||
| 732 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
| 733 | // .. .. reg_ddrc_addrmap_col_b4 = 0x0 | ||
| 734 | // .. .. ==> 0XF8006040[11:8] = 0x00000000U | ||
| 735 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | ||
| 736 | // .. .. reg_ddrc_addrmap_col_b7 = 0x0 | ||
| 737 | // .. .. ==> 0XF8006040[15:12] = 0x00000000U | ||
| 738 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | ||
| 739 | // .. .. reg_ddrc_addrmap_col_b8 = 0x0 | ||
| 740 | // .. .. ==> 0XF8006040[19:16] = 0x00000000U | ||
| 741 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | ||
| 742 | // .. .. reg_ddrc_addrmap_col_b9 = 0xf | ||
| 743 | // .. .. ==> 0XF8006040[23:20] = 0x0000000FU | ||
| 744 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U | ||
| 745 | // .. .. reg_ddrc_addrmap_col_b10 = 0xf | ||
| 746 | // .. .. ==> 0XF8006040[27:24] = 0x0000000FU | ||
| 747 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | ||
| 748 | // .. .. reg_ddrc_addrmap_col_b11 = 0xf | ||
| 749 | // .. .. ==> 0XF8006040[31:28] = 0x0000000FU | ||
| 750 | // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U | ||
| 751 | // .. .. | ||
| 752 | EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), | ||
| 753 | // .. .. reg_ddrc_addrmap_row_b0 = 0x6 | ||
| 754 | // .. .. ==> 0XF8006044[3:0] = 0x00000006U | ||
| 755 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U | ||
| 756 | // .. .. reg_ddrc_addrmap_row_b1 = 0x6 | ||
| 757 | // .. .. ==> 0XF8006044[7:4] = 0x00000006U | ||
| 758 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U | ||
| 759 | // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 | ||
| 760 | // .. .. ==> 0XF8006044[11:8] = 0x00000006U | ||
| 761 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U | ||
| 762 | // .. .. reg_ddrc_addrmap_row_b12 = 0x6 | ||
| 763 | // .. .. ==> 0XF8006044[15:12] = 0x00000006U | ||
| 764 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U | ||
| 765 | // .. .. reg_ddrc_addrmap_row_b13 = 0x6 | ||
| 766 | // .. .. ==> 0XF8006044[19:16] = 0x00000006U | ||
| 767 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U | ||
| 768 | // .. .. reg_ddrc_addrmap_row_b14 = 0xf | ||
| 769 | // .. .. ==> 0XF8006044[23:20] = 0x0000000FU | ||
| 770 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U | ||
| 771 | // .. .. reg_ddrc_addrmap_row_b15 = 0xf | ||
| 772 | // .. .. ==> 0XF8006044[27:24] = 0x0000000FU | ||
| 773 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | ||
| 774 | // .. .. | ||
| 775 | EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U), | ||
| 776 | // .. .. reg_phy_rd_local_odt = 0x0 | ||
| 777 | // .. .. ==> 0XF8006048[13:12] = 0x00000000U | ||
| 778 | // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U | ||
| 779 | // .. .. reg_phy_wr_local_odt = 0x3 | ||
| 780 | // .. .. ==> 0XF8006048[15:14] = 0x00000003U | ||
| 781 | // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U | ||
| 782 | // .. .. reg_phy_idle_local_odt = 0x3 | ||
| 783 | // .. .. ==> 0XF8006048[17:16] = 0x00000003U | ||
| 784 | // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U | ||
| 785 | // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 | ||
| 786 | // .. .. ==> 0XF8006048[5:3] = 0x00000001U | ||
| 787 | // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U | ||
| 788 | // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 | ||
| 789 | // .. .. ==> 0XF8006048[2:0] = 0x00000000U | ||
| 790 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | ||
| 791 | // .. .. | ||
| 792 | EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), | ||
| 793 | // .. .. reg_phy_rd_cmd_to_data = 0x0 | ||
| 794 | // .. .. ==> 0XF8006050[3:0] = 0x00000000U | ||
| 795 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
| 796 | // .. .. reg_phy_wr_cmd_to_data = 0x0 | ||
| 797 | // .. .. ==> 0XF8006050[7:4] = 0x00000000U | ||
| 798 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
| 799 | // .. .. reg_phy_rdc_we_to_re_delay = 0x8 | ||
| 800 | // .. .. ==> 0XF8006050[11:8] = 0x00000008U | ||
| 801 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U | ||
| 802 | // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 | ||
| 803 | // .. .. ==> 0XF8006050[15:15] = 0x00000000U | ||
| 804 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
| 805 | // .. .. reg_phy_use_fixed_re = 0x1 | ||
| 806 | // .. .. ==> 0XF8006050[16:16] = 0x00000001U | ||
| 807 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | ||
| 808 | // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 | ||
| 809 | // .. .. ==> 0XF8006050[17:17] = 0x00000000U | ||
| 810 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 811 | // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 | ||
| 812 | // .. .. ==> 0XF8006050[18:18] = 0x00000000U | ||
| 813 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 814 | // .. .. reg_phy_clk_stall_level = 0x0 | ||
| 815 | // .. .. ==> 0XF8006050[19:19] = 0x00000000U | ||
| 816 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
| 817 | // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 | ||
| 818 | // .. .. ==> 0XF8006050[27:24] = 0x00000007U | ||
| 819 | // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U | ||
| 820 | // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 | ||
| 821 | // .. .. ==> 0XF8006050[31:28] = 0x00000007U | ||
| 822 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | ||
| 823 | // .. .. | ||
| 824 | EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), | ||
| 825 | // .. .. reg_ddrc_dis_dll_calib = 0x0 | ||
| 826 | // .. .. ==> 0XF8006058[16:16] = 0x00000000U | ||
| 827 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 828 | // .. .. | ||
| 829 | EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), | ||
| 830 | // .. .. reg_ddrc_rd_odt_delay = 0x3 | ||
| 831 | // .. .. ==> 0XF800605C[3:0] = 0x00000003U | ||
| 832 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U | ||
| 833 | // .. .. reg_ddrc_wr_odt_delay = 0x0 | ||
| 834 | // .. .. ==> 0XF800605C[7:4] = 0x00000000U | ||
| 835 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
| 836 | // .. .. reg_ddrc_rd_odt_hold = 0x0 | ||
| 837 | // .. .. ==> 0XF800605C[11:8] = 0x00000000U | ||
| 838 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | ||
| 839 | // .. .. reg_ddrc_wr_odt_hold = 0x5 | ||
| 840 | // .. .. ==> 0XF800605C[15:12] = 0x00000005U | ||
| 841 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U | ||
| 842 | // .. .. | ||
| 843 | EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), | ||
| 844 | // .. .. reg_ddrc_pageclose = 0x0 | ||
| 845 | // .. .. ==> 0XF8006060[0:0] = 0x00000000U | ||
| 846 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 847 | // .. .. reg_ddrc_lpr_num_entries = 0x1f | ||
| 848 | // .. .. ==> 0XF8006060[6:1] = 0x0000001FU | ||
| 849 | // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU | ||
| 850 | // .. .. reg_ddrc_auto_pre_en = 0x0 | ||
| 851 | // .. .. ==> 0XF8006060[7:7] = 0x00000000U | ||
| 852 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 853 | // .. .. reg_ddrc_refresh_update_level = 0x0 | ||
| 854 | // .. .. ==> 0XF8006060[8:8] = 0x00000000U | ||
| 855 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 856 | // .. .. reg_ddrc_dis_wc = 0x0 | ||
| 857 | // .. .. ==> 0XF8006060[9:9] = 0x00000000U | ||
| 858 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
| 859 | // .. .. reg_ddrc_dis_collision_page_opt = 0x0 | ||
| 860 | // .. .. ==> 0XF8006060[10:10] = 0x00000000U | ||
| 861 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 862 | // .. .. reg_ddrc_selfref_en = 0x0 | ||
| 863 | // .. .. ==> 0XF8006060[12:12] = 0x00000000U | ||
| 864 | // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 865 | // .. .. | ||
| 866 | EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), | ||
| 867 | // .. .. reg_ddrc_go2critical_hysteresis = 0x0 | ||
| 868 | // .. .. ==> 0XF8006064[12:5] = 0x00000000U | ||
| 869 | // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U | ||
| 870 | // .. .. reg_arb_go2critical_en = 0x1 | ||
| 871 | // .. .. ==> 0XF8006064[17:17] = 0x00000001U | ||
| 872 | // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U | ||
| 873 | // .. .. | ||
| 874 | EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), | ||
| 875 | // .. .. reg_ddrc_wrlvl_ww = 0x41 | ||
| 876 | // .. .. ==> 0XF8006068[7:0] = 0x00000041U | ||
| 877 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U | ||
| 878 | // .. .. reg_ddrc_rdlvl_rr = 0x41 | ||
| 879 | // .. .. ==> 0XF8006068[15:8] = 0x00000041U | ||
| 880 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U | ||
| 881 | // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 | ||
| 882 | // .. .. ==> 0XF8006068[25:16] = 0x00000028U | ||
| 883 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U | ||
| 884 | // .. .. | ||
| 885 | EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), | ||
| 886 | // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 | ||
| 887 | // .. .. ==> 0XF800606C[7:0] = 0x00000010U | ||
| 888 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U | ||
| 889 | // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 | ||
| 890 | // .. .. ==> 0XF800606C[15:8] = 0x00000016U | ||
| 891 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U | ||
| 892 | // .. .. | ||
| 893 | EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), | ||
| 894 | // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 | ||
| 895 | // .. .. ==> 0XF8006078[3:0] = 0x00000001U | ||
| 896 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U | ||
| 897 | // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 | ||
| 898 | // .. .. ==> 0XF8006078[7:4] = 0x00000001U | ||
| 899 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U | ||
| 900 | // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 | ||
| 901 | // .. .. ==> 0XF8006078[11:8] = 0x00000001U | ||
| 902 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U | ||
| 903 | // .. .. reg_ddrc_t_cksre = 0x6 | ||
| 904 | // .. .. ==> 0XF8006078[15:12] = 0x00000006U | ||
| 905 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U | ||
| 906 | // .. .. reg_ddrc_t_cksrx = 0x6 | ||
| 907 | // .. .. ==> 0XF8006078[19:16] = 0x00000006U | ||
| 908 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U | ||
| 909 | // .. .. reg_ddrc_t_ckesr = 0x4 | ||
| 910 | // .. .. ==> 0XF8006078[25:20] = 0x00000004U | ||
| 911 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U | ||
| 912 | // .. .. | ||
| 913 | EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), | ||
| 914 | // .. .. reg_ddrc_t_ckpde = 0x2 | ||
| 915 | // .. .. ==> 0XF800607C[3:0] = 0x00000002U | ||
| 916 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U | ||
| 917 | // .. .. reg_ddrc_t_ckpdx = 0x2 | ||
| 918 | // .. .. ==> 0XF800607C[7:4] = 0x00000002U | ||
| 919 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U | ||
| 920 | // .. .. reg_ddrc_t_ckdpde = 0x2 | ||
| 921 | // .. .. ==> 0XF800607C[11:8] = 0x00000002U | ||
| 922 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
| 923 | // .. .. reg_ddrc_t_ckdpdx = 0x2 | ||
| 924 | // .. .. ==> 0XF800607C[15:12] = 0x00000002U | ||
| 925 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U | ||
| 926 | // .. .. reg_ddrc_t_ckcsx = 0x3 | ||
| 927 | // .. .. ==> 0XF800607C[19:16] = 0x00000003U | ||
| 928 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U | ||
| 929 | // .. .. | ||
| 930 | EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), | ||
| 931 | // .. .. reg_ddrc_dis_auto_zq = 0x0 | ||
| 932 | // .. .. ==> 0XF80060A4[0:0] = 0x00000000U | ||
| 933 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 934 | // .. .. reg_ddrc_ddr3 = 0x1 | ||
| 935 | // .. .. ==> 0XF80060A4[1:1] = 0x00000001U | ||
| 936 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 937 | // .. .. reg_ddrc_t_mod = 0x200 | ||
| 938 | // .. .. ==> 0XF80060A4[11:2] = 0x00000200U | ||
| 939 | // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U | ||
| 940 | // .. .. reg_ddrc_t_zq_long_nop = 0x200 | ||
| 941 | // .. .. ==> 0XF80060A4[21:12] = 0x00000200U | ||
| 942 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U | ||
| 943 | // .. .. reg_ddrc_t_zq_short_nop = 0x40 | ||
| 944 | // .. .. ==> 0XF80060A4[31:22] = 0x00000040U | ||
| 945 | // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U | ||
| 946 | // .. .. | ||
| 947 | EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), | ||
| 948 | // .. .. t_zq_short_interval_x1024 = 0xc845 | ||
| 949 | // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U | ||
| 950 | // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U | ||
| 951 | // .. .. dram_rstn_x1024 = 0x67 | ||
| 952 | // .. .. ==> 0XF80060A8[27:20] = 0x00000067U | ||
| 953 | // .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U | ||
| 954 | // .. .. | ||
| 955 | EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U), | ||
| 956 | // .. .. deeppowerdown_en = 0x0 | ||
| 957 | // .. .. ==> 0XF80060AC[0:0] = 0x00000000U | ||
| 958 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 959 | // .. .. deeppowerdown_to_x1024 = 0xff | ||
| 960 | // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU | ||
| 961 | // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU | ||
| 962 | // .. .. | ||
| 963 | EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), | ||
| 964 | // .. .. dfi_wrlvl_max_x1024 = 0xfff | ||
| 965 | // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU | ||
| 966 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU | ||
| 967 | // .. .. dfi_rdlvl_max_x1024 = 0xfff | ||
| 968 | // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU | ||
| 969 | // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U | ||
| 970 | // .. .. ddrc_reg_twrlvl_max_error = 0x0 | ||
| 971 | // .. .. ==> 0XF80060B0[24:24] = 0x00000000U | ||
| 972 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
| 973 | // .. .. ddrc_reg_trdlvl_max_error = 0x0 | ||
| 974 | // .. .. ==> 0XF80060B0[25:25] = 0x00000000U | ||
| 975 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
| 976 | // .. .. reg_ddrc_dfi_wr_level_en = 0x1 | ||
| 977 | // .. .. ==> 0XF80060B0[26:26] = 0x00000001U | ||
| 978 | // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | ||
| 979 | // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 | ||
| 980 | // .. .. ==> 0XF80060B0[27:27] = 0x00000001U | ||
| 981 | // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | ||
| 982 | // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 | ||
| 983 | // .. .. ==> 0XF80060B0[28:28] = 0x00000001U | ||
| 984 | // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | ||
| 985 | // .. .. | ||
| 986 | EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), | ||
| 987 | // .. .. reg_ddrc_skip_ocd = 0x1 | ||
| 988 | // .. .. ==> 0XF80060B4[9:9] = 0x00000001U | ||
| 989 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U | ||
| 990 | // .. .. | ||
| 991 | EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), | ||
| 992 | // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 | ||
| 993 | // .. .. ==> 0XF80060B8[4:0] = 0x00000006U | ||
| 994 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U | ||
| 995 | // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 | ||
| 996 | // .. .. ==> 0XF80060B8[14:5] = 0x00000003U | ||
| 997 | // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U | ||
| 998 | // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 | ||
| 999 | // .. .. ==> 0XF80060B8[24:15] = 0x00000040U | ||
| 1000 | // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U | ||
| 1001 | // .. .. | ||
| 1002 | EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), | ||
| 1003 | // .. .. START: RESET ECC ERROR | ||
| 1004 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 | ||
| 1005 | // .. .. ==> 0XF80060C4[0:0] = 0x00000001U | ||
| 1006 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 1007 | // .. .. Clear_Correctable_DRAM_ECC_error = 1 | ||
| 1008 | // .. .. ==> 0XF80060C4[1:1] = 0x00000001U | ||
| 1009 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 1010 | // .. .. | ||
| 1011 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), | ||
| 1012 | // .. .. FINISH: RESET ECC ERROR | ||
| 1013 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 | ||
| 1014 | // .. .. ==> 0XF80060C4[0:0] = 0x00000000U | ||
| 1015 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 1016 | // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 | ||
| 1017 | // .. .. ==> 0XF80060C4[1:1] = 0x00000000U | ||
| 1018 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 1019 | // .. .. | ||
| 1020 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), | ||
| 1021 | // .. .. CORR_ECC_LOG_VALID = 0x0 | ||
| 1022 | // .. .. ==> 0XF80060C8[0:0] = 0x00000000U | ||
| 1023 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 1024 | // .. .. ECC_CORRECTED_BIT_NUM = 0x0 | ||
| 1025 | // .. .. ==> 0XF80060C8[7:1] = 0x00000000U | ||
| 1026 | // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U | ||
| 1027 | // .. .. | ||
| 1028 | EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), | ||
| 1029 | // .. .. UNCORR_ECC_LOG_VALID = 0x0 | ||
| 1030 | // .. .. ==> 0XF80060DC[0:0] = 0x00000000U | ||
| 1031 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 1032 | // .. .. | ||
| 1033 | EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), | ||
| 1034 | // .. .. STAT_NUM_CORR_ERR = 0x0 | ||
| 1035 | // .. .. ==> 0XF80060F0[15:8] = 0x00000000U | ||
| 1036 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U | ||
| 1037 | // .. .. STAT_NUM_UNCORR_ERR = 0x0 | ||
| 1038 | // .. .. ==> 0XF80060F0[7:0] = 0x00000000U | ||
| 1039 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U | ||
| 1040 | // .. .. | ||
| 1041 | EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), | ||
| 1042 | // .. .. reg_ddrc_ecc_mode = 0x0 | ||
| 1043 | // .. .. ==> 0XF80060F4[2:0] = 0x00000000U | ||
| 1044 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | ||
| 1045 | // .. .. reg_ddrc_dis_scrub = 0x1 | ||
| 1046 | // .. .. ==> 0XF80060F4[3:3] = 0x00000001U | ||
| 1047 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U | ||
| 1048 | // .. .. | ||
| 1049 | EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), | ||
| 1050 | // .. .. reg_phy_dif_on = 0x0 | ||
| 1051 | // .. .. ==> 0XF8006114[3:0] = 0x00000000U | ||
| 1052 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
| 1053 | // .. .. reg_phy_dif_off = 0x0 | ||
| 1054 | // .. .. ==> 0XF8006114[7:4] = 0x00000000U | ||
| 1055 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
| 1056 | // .. .. | ||
| 1057 | EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), | ||
| 1058 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
| 1059 | // .. .. ==> 0XF8006118[0:0] = 0x00000001U | ||
| 1060 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 1061 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
| 1062 | // .. .. ==> 0XF8006118[1:1] = 0x00000000U | ||
| 1063 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 1064 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
| 1065 | // .. .. ==> 0XF8006118[2:2] = 0x00000000U | ||
| 1066 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 1067 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
| 1068 | // .. .. ==> 0XF8006118[3:3] = 0x00000000U | ||
| 1069 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 1070 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
| 1071 | // .. .. ==> 0XF8006118[14:6] = 0x00000000U | ||
| 1072 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
| 1073 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
| 1074 | // .. .. ==> 0XF8006118[23:15] = 0x00000000U | ||
| 1075 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
| 1076 | // .. .. reg_phy_dq_offset = 0x40 | ||
| 1077 | // .. .. ==> 0XF8006118[30:24] = 0x00000040U | ||
| 1078 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
| 1079 | // .. .. | ||
| 1080 | EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), | ||
| 1081 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
| 1082 | // .. .. ==> 0XF800611C[0:0] = 0x00000001U | ||
| 1083 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 1084 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
| 1085 | // .. .. ==> 0XF800611C[1:1] = 0x00000000U | ||
| 1086 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 1087 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
| 1088 | // .. .. ==> 0XF800611C[2:2] = 0x00000000U | ||
| 1089 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 1090 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
| 1091 | // .. .. ==> 0XF800611C[3:3] = 0x00000000U | ||
| 1092 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 1093 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
| 1094 | // .. .. ==> 0XF800611C[14:6] = 0x00000000U | ||
| 1095 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
| 1096 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
| 1097 | // .. .. ==> 0XF800611C[23:15] = 0x00000000U | ||
| 1098 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
| 1099 | // .. .. reg_phy_dq_offset = 0x40 | ||
| 1100 | // .. .. ==> 0XF800611C[30:24] = 0x00000040U | ||
| 1101 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
| 1102 | // .. .. | ||
| 1103 | EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), | ||
| 1104 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
| 1105 | // .. .. ==> 0XF8006120[0:0] = 0x00000001U | ||
| 1106 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 1107 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
| 1108 | // .. .. ==> 0XF8006120[1:1] = 0x00000000U | ||
| 1109 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 1110 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
| 1111 | // .. .. ==> 0XF8006120[2:2] = 0x00000000U | ||
| 1112 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 1113 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
| 1114 | // .. .. ==> 0XF8006120[3:3] = 0x00000000U | ||
| 1115 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 1116 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
| 1117 | // .. .. ==> 0XF8006120[14:6] = 0x00000000U | ||
| 1118 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
| 1119 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
| 1120 | // .. .. ==> 0XF8006120[23:15] = 0x00000000U | ||
| 1121 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
| 1122 | // .. .. reg_phy_dq_offset = 0x40 | ||
| 1123 | // .. .. ==> 0XF8006120[30:24] = 0x00000040U | ||
| 1124 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
| 1125 | // .. .. | ||
| 1126 | EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), | ||
| 1127 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
| 1128 | // .. .. ==> 0XF8006124[0:0] = 0x00000001U | ||
| 1129 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 1130 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
| 1131 | // .. .. ==> 0XF8006124[1:1] = 0x00000000U | ||
| 1132 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 1133 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
| 1134 | // .. .. ==> 0XF8006124[2:2] = 0x00000000U | ||
| 1135 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 1136 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
| 1137 | // .. .. ==> 0XF8006124[3:3] = 0x00000000U | ||
| 1138 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 1139 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
| 1140 | // .. .. ==> 0XF8006124[14:6] = 0x00000000U | ||
| 1141 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
| 1142 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
| 1143 | // .. .. ==> 0XF8006124[23:15] = 0x00000000U | ||
| 1144 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
| 1145 | // .. .. reg_phy_dq_offset = 0x40 | ||
| 1146 | // .. .. ==> 0XF8006124[30:24] = 0x00000040U | ||
| 1147 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
| 1148 | // .. .. | ||
| 1149 | EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), | ||
| 1150 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
| 1151 | // .. .. ==> 0XF800612C[9:0] = 0x00000000U | ||
| 1152 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
| 1153 | // .. .. reg_phy_gatelvl_init_ratio = 0x8f | ||
| 1154 | // .. .. ==> 0XF800612C[19:10] = 0x0000008FU | ||
| 1155 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U | ||
| 1156 | // .. .. | ||
| 1157 | EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U), | ||
| 1158 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
| 1159 | // .. .. ==> 0XF8006130[9:0] = 0x00000000U | ||
| 1160 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
| 1161 | // .. .. reg_phy_gatelvl_init_ratio = 0x8a | ||
| 1162 | // .. .. ==> 0XF8006130[19:10] = 0x0000008AU | ||
| 1163 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U | ||
| 1164 | // .. .. | ||
| 1165 | EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U), | ||
| 1166 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
| 1167 | // .. .. ==> 0XF8006134[9:0] = 0x00000000U | ||
| 1168 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
| 1169 | // .. .. reg_phy_gatelvl_init_ratio = 0x8b | ||
| 1170 | // .. .. ==> 0XF8006134[19:10] = 0x0000008BU | ||
| 1171 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U | ||
| 1172 | // .. .. | ||
| 1173 | EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U), | ||
| 1174 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
| 1175 | // .. .. ==> 0XF8006138[9:0] = 0x00000000U | ||
| 1176 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
| 1177 | // .. .. reg_phy_gatelvl_init_ratio = 0x92 | ||
| 1178 | // .. .. ==> 0XF8006138[19:10] = 0x00000092U | ||
| 1179 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U | ||
| 1180 | // .. .. | ||
| 1181 | EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U), | ||
| 1182 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
| 1183 | // .. .. ==> 0XF8006140[9:0] = 0x00000035U | ||
| 1184 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
| 1185 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
| 1186 | // .. .. ==> 0XF8006140[10:10] = 0x00000000U | ||
| 1187 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 1188 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
| 1189 | // .. .. ==> 0XF8006140[19:11] = 0x00000000U | ||
| 1190 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 1191 | // .. .. | ||
| 1192 | EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), | ||
| 1193 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
| 1194 | // .. .. ==> 0XF8006144[9:0] = 0x00000035U | ||
| 1195 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
| 1196 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
| 1197 | // .. .. ==> 0XF8006144[10:10] = 0x00000000U | ||
| 1198 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 1199 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
| 1200 | // .. .. ==> 0XF8006144[19:11] = 0x00000000U | ||
| 1201 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 1202 | // .. .. | ||
| 1203 | EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), | ||
| 1204 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
| 1205 | // .. .. ==> 0XF8006148[9:0] = 0x00000035U | ||
| 1206 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
| 1207 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
| 1208 | // .. .. ==> 0XF8006148[10:10] = 0x00000000U | ||
| 1209 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 1210 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
| 1211 | // .. .. ==> 0XF8006148[19:11] = 0x00000000U | ||
| 1212 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 1213 | // .. .. | ||
| 1214 | EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), | ||
| 1215 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
| 1216 | // .. .. ==> 0XF800614C[9:0] = 0x00000035U | ||
| 1217 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
| 1218 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
| 1219 | // .. .. ==> 0XF800614C[10:10] = 0x00000000U | ||
| 1220 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 1221 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
| 1222 | // .. .. ==> 0XF800614C[19:11] = 0x00000000U | ||
| 1223 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 1224 | // .. .. | ||
| 1225 | EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), | ||
| 1226 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 | ||
| 1227 | // .. .. ==> 0XF8006154[9:0] = 0x00000077U | ||
| 1228 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U | ||
| 1229 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
| 1230 | // .. .. ==> 0XF8006154[10:10] = 0x00000000U | ||
| 1231 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 1232 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
| 1233 | // .. .. ==> 0XF8006154[19:11] = 0x00000000U | ||
| 1234 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 1235 | // .. .. | ||
| 1236 | EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U), | ||
| 1237 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c | ||
| 1238 | // .. .. ==> 0XF8006158[9:0] = 0x0000007CU | ||
| 1239 | // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU | ||
| 1240 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
| 1241 | // .. .. ==> 0XF8006158[10:10] = 0x00000000U | ||
| 1242 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 1243 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
| 1244 | // .. .. ==> 0XF8006158[19:11] = 0x00000000U | ||
| 1245 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 1246 | // .. .. | ||
| 1247 | EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), | ||
| 1248 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c | ||
| 1249 | // .. .. ==> 0XF800615C[9:0] = 0x0000007CU | ||
| 1250 | // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU | ||
| 1251 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
| 1252 | // .. .. ==> 0XF800615C[10:10] = 0x00000000U | ||
| 1253 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 1254 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
| 1255 | // .. .. ==> 0XF800615C[19:11] = 0x00000000U | ||
| 1256 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 1257 | // .. .. | ||
| 1258 | EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU), | ||
| 1259 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x75 | ||
| 1260 | // .. .. ==> 0XF8006160[9:0] = 0x00000075U | ||
| 1261 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U | ||
| 1262 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
| 1263 | // .. .. ==> 0XF8006160[10:10] = 0x00000000U | ||
| 1264 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 1265 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
| 1266 | // .. .. ==> 0XF8006160[19:11] = 0x00000000U | ||
| 1267 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 1268 | // .. .. | ||
| 1269 | EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U), | ||
| 1270 | // .. .. reg_phy_fifo_we_slave_ratio = 0xe4 | ||
| 1271 | // .. .. ==> 0XF8006168[10:0] = 0x000000E4U | ||
| 1272 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U | ||
| 1273 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
| 1274 | // .. .. ==> 0XF8006168[11:11] = 0x00000000U | ||
| 1275 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 1276 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
| 1277 | // .. .. ==> 0XF8006168[20:12] = 0x00000000U | ||
| 1278 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
| 1279 | // .. .. | ||
| 1280 | EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U), | ||
| 1281 | // .. .. reg_phy_fifo_we_slave_ratio = 0xdf | ||
| 1282 | // .. .. ==> 0XF800616C[10:0] = 0x000000DFU | ||
| 1283 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU | ||
| 1284 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
| 1285 | // .. .. ==> 0XF800616C[11:11] = 0x00000000U | ||
| 1286 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 1287 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
| 1288 | // .. .. ==> 0XF800616C[20:12] = 0x00000000U | ||
| 1289 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
| 1290 | // .. .. | ||
| 1291 | EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU), | ||
| 1292 | // .. .. reg_phy_fifo_we_slave_ratio = 0xe0 | ||
| 1293 | // .. .. ==> 0XF8006170[10:0] = 0x000000E0U | ||
| 1294 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U | ||
| 1295 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
| 1296 | // .. .. ==> 0XF8006170[11:11] = 0x00000000U | ||
| 1297 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 1298 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
| 1299 | // .. .. ==> 0XF8006170[20:12] = 0x00000000U | ||
| 1300 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
| 1301 | // .. .. | ||
| 1302 | EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U), | ||
| 1303 | // .. .. reg_phy_fifo_we_slave_ratio = 0xe7 | ||
| 1304 | // .. .. ==> 0XF8006174[10:0] = 0x000000E7U | ||
| 1305 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U | ||
| 1306 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
| 1307 | // .. .. ==> 0XF8006174[11:11] = 0x00000000U | ||
| 1308 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 1309 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
| 1310 | // .. .. ==> 0XF8006174[20:12] = 0x00000000U | ||
| 1311 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
| 1312 | // .. .. | ||
| 1313 | EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U), | ||
| 1314 | // .. .. reg_phy_wr_data_slave_ratio = 0xb7 | ||
| 1315 | // .. .. ==> 0XF800617C[9:0] = 0x000000B7U | ||
| 1316 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U | ||
| 1317 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
| 1318 | // .. .. ==> 0XF800617C[10:10] = 0x00000000U | ||
| 1319 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 1320 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
| 1321 | // .. .. ==> 0XF800617C[19:11] = 0x00000000U | ||
| 1322 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 1323 | // .. .. | ||
| 1324 | EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U), | ||
| 1325 | // .. .. reg_phy_wr_data_slave_ratio = 0xbc | ||
| 1326 | // .. .. ==> 0XF8006180[9:0] = 0x000000BCU | ||
| 1327 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU | ||
| 1328 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
| 1329 | // .. .. ==> 0XF8006180[10:10] = 0x00000000U | ||
| 1330 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 1331 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
| 1332 | // .. .. ==> 0XF8006180[19:11] = 0x00000000U | ||
| 1333 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 1334 | // .. .. | ||
| 1335 | EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), | ||
| 1336 | // .. .. reg_phy_wr_data_slave_ratio = 0xbc | ||
| 1337 | // .. .. ==> 0XF8006184[9:0] = 0x000000BCU | ||
| 1338 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU | ||
| 1339 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
| 1340 | // .. .. ==> 0XF8006184[10:10] = 0x00000000U | ||
| 1341 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 1342 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
| 1343 | // .. .. ==> 0XF8006184[19:11] = 0x00000000U | ||
| 1344 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 1345 | // .. .. | ||
| 1346 | EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU), | ||
| 1347 | // .. .. reg_phy_wr_data_slave_ratio = 0xb5 | ||
| 1348 | // .. .. ==> 0XF8006188[9:0] = 0x000000B5U | ||
| 1349 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U | ||
| 1350 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
| 1351 | // .. .. ==> 0XF8006188[10:10] = 0x00000000U | ||
| 1352 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 1353 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
| 1354 | // .. .. ==> 0XF8006188[19:11] = 0x00000000U | ||
| 1355 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 1356 | // .. .. | ||
| 1357 | EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U), | ||
| 1358 | // .. .. reg_phy_bl2 = 0x0 | ||
| 1359 | // .. .. ==> 0XF8006190[1:1] = 0x00000000U | ||
| 1360 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 1361 | // .. .. reg_phy_at_spd_atpg = 0x0 | ||
| 1362 | // .. .. ==> 0XF8006190[2:2] = 0x00000000U | ||
| 1363 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 1364 | // .. .. reg_phy_bist_enable = 0x0 | ||
| 1365 | // .. .. ==> 0XF8006190[3:3] = 0x00000000U | ||
| 1366 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 1367 | // .. .. reg_phy_bist_force_err = 0x0 | ||
| 1368 | // .. .. ==> 0XF8006190[4:4] = 0x00000000U | ||
| 1369 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 1370 | // .. .. reg_phy_bist_mode = 0x0 | ||
| 1371 | // .. .. ==> 0XF8006190[6:5] = 0x00000000U | ||
| 1372 | // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
| 1373 | // .. .. reg_phy_invert_clkout = 0x1 | ||
| 1374 | // .. .. ==> 0XF8006190[7:7] = 0x00000001U | ||
| 1375 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
| 1376 | // .. .. reg_phy_sel_logic = 0x0 | ||
| 1377 | // .. .. ==> 0XF8006190[9:9] = 0x00000000U | ||
| 1378 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
| 1379 | // .. .. reg_phy_ctrl_slave_ratio = 0x100 | ||
| 1380 | // .. .. ==> 0XF8006190[19:10] = 0x00000100U | ||
| 1381 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U | ||
| 1382 | // .. .. reg_phy_ctrl_slave_force = 0x0 | ||
| 1383 | // .. .. ==> 0XF8006190[20:20] = 0x00000000U | ||
| 1384 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
| 1385 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | ||
| 1386 | // .. .. ==> 0XF8006190[27:21] = 0x00000000U | ||
| 1387 | // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U | ||
| 1388 | // .. .. reg_phy_lpddr = 0x0 | ||
| 1389 | // .. .. ==> 0XF8006190[29:29] = 0x00000000U | ||
| 1390 | // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U | ||
| 1391 | // .. .. reg_phy_cmd_latency = 0x0 | ||
| 1392 | // .. .. ==> 0XF8006190[30:30] = 0x00000000U | ||
| 1393 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | ||
| 1394 | // .. .. | ||
| 1395 | EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), | ||
| 1396 | // .. .. reg_phy_wr_rl_delay = 0x2 | ||
| 1397 | // .. .. ==> 0XF8006194[4:0] = 0x00000002U | ||
| 1398 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U | ||
| 1399 | // .. .. reg_phy_rd_rl_delay = 0x4 | ||
| 1400 | // .. .. ==> 0XF8006194[9:5] = 0x00000004U | ||
| 1401 | // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U | ||
| 1402 | // .. .. reg_phy_dll_lock_diff = 0xf | ||
| 1403 | // .. .. ==> 0XF8006194[13:10] = 0x0000000FU | ||
| 1404 | // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U | ||
| 1405 | // .. .. reg_phy_use_wr_level = 0x1 | ||
| 1406 | // .. .. ==> 0XF8006194[14:14] = 0x00000001U | ||
| 1407 | // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U | ||
| 1408 | // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 | ||
| 1409 | // .. .. ==> 0XF8006194[15:15] = 0x00000001U | ||
| 1410 | // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U | ||
| 1411 | // .. .. reg_phy_use_rd_data_eye_level = 0x1 | ||
| 1412 | // .. .. ==> 0XF8006194[16:16] = 0x00000001U | ||
| 1413 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | ||
| 1414 | // .. .. reg_phy_dis_calib_rst = 0x0 | ||
| 1415 | // .. .. ==> 0XF8006194[17:17] = 0x00000000U | ||
| 1416 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 1417 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | ||
| 1418 | // .. .. ==> 0XF8006194[19:18] = 0x00000000U | ||
| 1419 | // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U | ||
| 1420 | // .. .. | ||
| 1421 | EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), | ||
| 1422 | // .. .. reg_arb_page_addr_mask = 0x0 | ||
| 1423 | // .. .. ==> 0XF8006204[31:0] = 0x00000000U | ||
| 1424 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
| 1425 | // .. .. | ||
| 1426 | EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), | ||
| 1427 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
| 1428 | // .. .. ==> 0XF8006208[9:0] = 0x000003FFU | ||
| 1429 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 1430 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
| 1431 | // .. .. ==> 0XF8006208[16:16] = 0x00000000U | ||
| 1432 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 1433 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
| 1434 | // .. .. ==> 0XF8006208[17:17] = 0x00000000U | ||
| 1435 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 1436 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
| 1437 | // .. .. ==> 0XF8006208[18:18] = 0x00000000U | ||
| 1438 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 1439 | // .. .. | ||
| 1440 | EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), | ||
| 1441 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
| 1442 | // .. .. ==> 0XF800620C[9:0] = 0x000003FFU | ||
| 1443 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 1444 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
| 1445 | // .. .. ==> 0XF800620C[16:16] = 0x00000000U | ||
| 1446 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 1447 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
| 1448 | // .. .. ==> 0XF800620C[17:17] = 0x00000000U | ||
| 1449 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 1450 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
| 1451 | // .. .. ==> 0XF800620C[18:18] = 0x00000000U | ||
| 1452 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 1453 | // .. .. | ||
| 1454 | EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), | ||
| 1455 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
| 1456 | // .. .. ==> 0XF8006210[9:0] = 0x000003FFU | ||
| 1457 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 1458 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
| 1459 | // .. .. ==> 0XF8006210[16:16] = 0x00000000U | ||
| 1460 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 1461 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
| 1462 | // .. .. ==> 0XF8006210[17:17] = 0x00000000U | ||
| 1463 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 1464 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
| 1465 | // .. .. ==> 0XF8006210[18:18] = 0x00000000U | ||
| 1466 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 1467 | // .. .. | ||
| 1468 | EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), | ||
| 1469 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
| 1470 | // .. .. ==> 0XF8006214[9:0] = 0x000003FFU | ||
| 1471 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 1472 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
| 1473 | // .. .. ==> 0XF8006214[16:16] = 0x00000000U | ||
| 1474 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 1475 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
| 1476 | // .. .. ==> 0XF8006214[17:17] = 0x00000000U | ||
| 1477 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 1478 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
| 1479 | // .. .. ==> 0XF8006214[18:18] = 0x00000000U | ||
| 1480 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 1481 | // .. .. | ||
| 1482 | EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), | ||
| 1483 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
| 1484 | // .. .. ==> 0XF8006218[9:0] = 0x000003FFU | ||
| 1485 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 1486 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
| 1487 | // .. .. ==> 0XF8006218[16:16] = 0x00000000U | ||
| 1488 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 1489 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
| 1490 | // .. .. ==> 0XF8006218[17:17] = 0x00000000U | ||
| 1491 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 1492 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
| 1493 | // .. .. ==> 0XF8006218[18:18] = 0x00000000U | ||
| 1494 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 1495 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
| 1496 | // .. .. ==> 0XF8006218[19:19] = 0x00000000U | ||
| 1497 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
| 1498 | // .. .. | ||
| 1499 | EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), | ||
| 1500 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
| 1501 | // .. .. ==> 0XF800621C[9:0] = 0x000003FFU | ||
| 1502 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 1503 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
| 1504 | // .. .. ==> 0XF800621C[16:16] = 0x00000000U | ||
| 1505 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 1506 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
| 1507 | // .. .. ==> 0XF800621C[17:17] = 0x00000000U | ||
| 1508 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 1509 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
| 1510 | // .. .. ==> 0XF800621C[18:18] = 0x00000000U | ||
| 1511 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 1512 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
| 1513 | // .. .. ==> 0XF800621C[19:19] = 0x00000000U | ||
| 1514 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
| 1515 | // .. .. | ||
| 1516 | EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), | ||
| 1517 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
| 1518 | // .. .. ==> 0XF8006220[9:0] = 0x000003FFU | ||
| 1519 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 1520 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
| 1521 | // .. .. ==> 0XF8006220[16:16] = 0x00000000U | ||
| 1522 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 1523 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
| 1524 | // .. .. ==> 0XF8006220[17:17] = 0x00000000U | ||
| 1525 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 1526 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
| 1527 | // .. .. ==> 0XF8006220[18:18] = 0x00000000U | ||
| 1528 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 1529 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
| 1530 | // .. .. ==> 0XF8006220[19:19] = 0x00000000U | ||
| 1531 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
| 1532 | // .. .. | ||
| 1533 | EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), | ||
| 1534 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
| 1535 | // .. .. ==> 0XF8006224[9:0] = 0x000003FFU | ||
| 1536 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 1537 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
| 1538 | // .. .. ==> 0XF8006224[16:16] = 0x00000000U | ||
| 1539 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 1540 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
| 1541 | // .. .. ==> 0XF8006224[17:17] = 0x00000000U | ||
| 1542 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 1543 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
| 1544 | // .. .. ==> 0XF8006224[18:18] = 0x00000000U | ||
| 1545 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 1546 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
| 1547 | // .. .. ==> 0XF8006224[19:19] = 0x00000000U | ||
| 1548 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
| 1549 | // .. .. | ||
| 1550 | EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), | ||
| 1551 | // .. .. reg_ddrc_lpddr2 = 0x0 | ||
| 1552 | // .. .. ==> 0XF80062A8[0:0] = 0x00000000U | ||
| 1553 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 1554 | // .. .. reg_ddrc_derate_enable = 0x0 | ||
| 1555 | // .. .. ==> 0XF80062A8[2:2] = 0x00000000U | ||
| 1556 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 1557 | // .. .. reg_ddrc_mr4_margin = 0x0 | ||
| 1558 | // .. .. ==> 0XF80062A8[11:4] = 0x00000000U | ||
| 1559 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U | ||
| 1560 | // .. .. | ||
| 1561 | EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), | ||
| 1562 | // .. .. reg_ddrc_mr4_read_interval = 0x0 | ||
| 1563 | // .. .. ==> 0XF80062AC[31:0] = 0x00000000U | ||
| 1564 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
| 1565 | // .. .. | ||
| 1566 | EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), | ||
| 1567 | // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 | ||
| 1568 | // .. .. ==> 0XF80062B0[3:0] = 0x00000005U | ||
| 1569 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U | ||
| 1570 | // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 | ||
| 1571 | // .. .. ==> 0XF80062B0[11:4] = 0x00000012U | ||
| 1572 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U | ||
| 1573 | // .. .. reg_ddrc_t_mrw = 0x5 | ||
| 1574 | // .. .. ==> 0XF80062B0[21:12] = 0x00000005U | ||
| 1575 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U | ||
| 1576 | // .. .. | ||
| 1577 | EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), | ||
| 1578 | // .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 | ||
| 1579 | // .. .. ==> 0XF80062B4[7:0] = 0x000000A6U | ||
| 1580 | // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U | ||
| 1581 | // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 | ||
| 1582 | // .. .. ==> 0XF80062B4[17:8] = 0x00000012U | ||
| 1583 | // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U | ||
| 1584 | // .. .. | ||
| 1585 | EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U), | ||
| 1586 | // .. .. START: POLL ON DCI STATUS | ||
| 1587 | // .. .. DONE = 1 | ||
| 1588 | // .. .. ==> 0XF8000B74[13:13] = 0x00000001U | ||
| 1589 | // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 1590 | // .. .. | ||
| 1591 | EMIT_MASKPOLL(0XF8000B74, 0x00002000U), | ||
| 1592 | // .. .. FINISH: POLL ON DCI STATUS | ||
| 1593 | // .. .. START: UNLOCK DDR | ||
| 1594 | // .. .. reg_ddrc_soft_rstb = 0x1 | ||
| 1595 | // .. .. ==> 0XF8006000[0:0] = 0x00000001U | ||
| 1596 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 1597 | // .. .. reg_ddrc_powerdown_en = 0x0 | ||
| 1598 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | ||
| 1599 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 1600 | // .. .. reg_ddrc_data_bus_width = 0x0 | ||
| 1601 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | ||
| 1602 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | ||
| 1603 | // .. .. reg_ddrc_burst8_refresh = 0x0 | ||
| 1604 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | ||
| 1605 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
| 1606 | // .. .. reg_ddrc_rdwr_idle_gap = 1 | ||
| 1607 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | ||
| 1608 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | ||
| 1609 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | ||
| 1610 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | ||
| 1611 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
| 1612 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | ||
| 1613 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | ||
| 1614 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
| 1615 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | ||
| 1616 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | ||
| 1617 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 1618 | // .. .. | ||
| 1619 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), | ||
| 1620 | // .. .. FINISH: UNLOCK DDR | ||
| 1621 | // .. .. START: CHECK DDR STATUS | ||
| 1622 | // .. .. ddrc_reg_operating_mode = 1 | ||
| 1623 | // .. .. ==> 0XF8006054[2:0] = 0x00000001U | ||
| 1624 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U | ||
| 1625 | // .. .. | ||
| 1626 | EMIT_MASKPOLL(0XF8006054, 0x00000007U), | ||
| 1627 | // .. .. FINISH: CHECK DDR STATUS | ||
| 1628 | // .. FINISH: DDR INITIALIZATION | ||
| 1629 | // FINISH: top | ||
| 1630 | // | ||
| 1631 | EMIT_EXIT(), | ||
| 1632 | |||
| 1633 | // | ||
| 1634 | }; | ||
| 1635 | |||
| 1636 | unsigned long ps7_mio_init_data_3_0[] = { | ||
| 1637 | // START: top | ||
| 1638 | // .. START: SLCR SETTINGS | ||
| 1639 | // .. UNLOCK_KEY = 0XDF0D | ||
| 1640 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
| 1641 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
| 1642 | // .. | ||
| 1643 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
| 1644 | // .. FINISH: SLCR SETTINGS | ||
| 1645 | // .. START: OCM REMAPPING | ||
| 1646 | // .. VREF_EN = 0x1 | ||
| 1647 | // .. ==> 0XF8000B00[0:0] = 0x00000001U | ||
| 1648 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 1649 | // .. VREF_SEL = 0x0 | ||
| 1650 | // .. ==> 0XF8000B00[6:4] = 0x00000000U | ||
| 1651 | // .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
| 1652 | // .. | ||
| 1653 | EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U), | ||
| 1654 | // .. FINISH: OCM REMAPPING | ||
| 1655 | // .. START: DDRIOB SETTINGS | ||
| 1656 | // .. reserved_INP_POWER = 0x0 | ||
| 1657 | // .. ==> 0XF8000B40[0:0] = 0x00000000U | ||
| 1658 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 1659 | // .. INP_TYPE = 0x0 | ||
| 1660 | // .. ==> 0XF8000B40[2:1] = 0x00000000U | ||
| 1661 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
| 1662 | // .. DCI_UPDATE_B = 0x0 | ||
| 1663 | // .. ==> 0XF8000B40[3:3] = 0x00000000U | ||
| 1664 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 1665 | // .. TERM_EN = 0x0 | ||
| 1666 | // .. ==> 0XF8000B40[4:4] = 0x00000000U | ||
| 1667 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 1668 | // .. DCI_TYPE = 0x0 | ||
| 1669 | // .. ==> 0XF8000B40[6:5] = 0x00000000U | ||
| 1670 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
| 1671 | // .. IBUF_DISABLE_MODE = 0x0 | ||
| 1672 | // .. ==> 0XF8000B40[7:7] = 0x00000000U | ||
| 1673 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 1674 | // .. TERM_DISABLE_MODE = 0x0 | ||
| 1675 | // .. ==> 0XF8000B40[8:8] = 0x00000000U | ||
| 1676 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 1677 | // .. OUTPUT_EN = 0x3 | ||
| 1678 | // .. ==> 0XF8000B40[10:9] = 0x00000003U | ||
| 1679 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 1680 | // .. PULLUP_EN = 0x0 | ||
| 1681 | // .. ==> 0XF8000B40[11:11] = 0x00000000U | ||
| 1682 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 1683 | // .. | ||
| 1684 | EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), | ||
| 1685 | // .. reserved_INP_POWER = 0x0 | ||
| 1686 | // .. ==> 0XF8000B44[0:0] = 0x00000000U | ||
| 1687 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 1688 | // .. INP_TYPE = 0x0 | ||
| 1689 | // .. ==> 0XF8000B44[2:1] = 0x00000000U | ||
| 1690 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
| 1691 | // .. DCI_UPDATE_B = 0x0 | ||
| 1692 | // .. ==> 0XF8000B44[3:3] = 0x00000000U | ||
| 1693 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 1694 | // .. TERM_EN = 0x0 | ||
| 1695 | // .. ==> 0XF8000B44[4:4] = 0x00000000U | ||
| 1696 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 1697 | // .. DCI_TYPE = 0x0 | ||
| 1698 | // .. ==> 0XF8000B44[6:5] = 0x00000000U | ||
| 1699 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
| 1700 | // .. IBUF_DISABLE_MODE = 0x0 | ||
| 1701 | // .. ==> 0XF8000B44[7:7] = 0x00000000U | ||
| 1702 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 1703 | // .. TERM_DISABLE_MODE = 0x0 | ||
| 1704 | // .. ==> 0XF8000B44[8:8] = 0x00000000U | ||
| 1705 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 1706 | // .. OUTPUT_EN = 0x3 | ||
| 1707 | // .. ==> 0XF8000B44[10:9] = 0x00000003U | ||
| 1708 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 1709 | // .. PULLUP_EN = 0x0 | ||
| 1710 | // .. ==> 0XF8000B44[11:11] = 0x00000000U | ||
| 1711 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 1712 | // .. | ||
| 1713 | EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), | ||
| 1714 | // .. reserved_INP_POWER = 0x0 | ||
| 1715 | // .. ==> 0XF8000B48[0:0] = 0x00000000U | ||
| 1716 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 1717 | // .. INP_TYPE = 0x1 | ||
| 1718 | // .. ==> 0XF8000B48[2:1] = 0x00000001U | ||
| 1719 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | ||
| 1720 | // .. DCI_UPDATE_B = 0x0 | ||
| 1721 | // .. ==> 0XF8000B48[3:3] = 0x00000000U | ||
| 1722 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 1723 | // .. TERM_EN = 0x1 | ||
| 1724 | // .. ==> 0XF8000B48[4:4] = 0x00000001U | ||
| 1725 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 1726 | // .. DCI_TYPE = 0x3 | ||
| 1727 | // .. ==> 0XF8000B48[6:5] = 0x00000003U | ||
| 1728 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
| 1729 | // .. IBUF_DISABLE_MODE = 0 | ||
| 1730 | // .. ==> 0XF8000B48[7:7] = 0x00000000U | ||
| 1731 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 1732 | // .. TERM_DISABLE_MODE = 0 | ||
| 1733 | // .. ==> 0XF8000B48[8:8] = 0x00000000U | ||
| 1734 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 1735 | // .. OUTPUT_EN = 0x3 | ||
| 1736 | // .. ==> 0XF8000B48[10:9] = 0x00000003U | ||
| 1737 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 1738 | // .. PULLUP_EN = 0x0 | ||
| 1739 | // .. ==> 0XF8000B48[11:11] = 0x00000000U | ||
| 1740 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 1741 | // .. | ||
| 1742 | EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), | ||
| 1743 | // .. reserved_INP_POWER = 0x0 | ||
| 1744 | // .. ==> 0XF8000B4C[0:0] = 0x00000000U | ||
| 1745 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 1746 | // .. INP_TYPE = 0x1 | ||
| 1747 | // .. ==> 0XF8000B4C[2:1] = 0x00000001U | ||
| 1748 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | ||
| 1749 | // .. DCI_UPDATE_B = 0x0 | ||
| 1750 | // .. ==> 0XF8000B4C[3:3] = 0x00000000U | ||
| 1751 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 1752 | // .. TERM_EN = 0x1 | ||
| 1753 | // .. ==> 0XF8000B4C[4:4] = 0x00000001U | ||
| 1754 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 1755 | // .. DCI_TYPE = 0x3 | ||
| 1756 | // .. ==> 0XF8000B4C[6:5] = 0x00000003U | ||
| 1757 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
| 1758 | // .. IBUF_DISABLE_MODE = 0 | ||
| 1759 | // .. ==> 0XF8000B4C[7:7] = 0x00000000U | ||
| 1760 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 1761 | // .. TERM_DISABLE_MODE = 0 | ||
| 1762 | // .. ==> 0XF8000B4C[8:8] = 0x00000000U | ||
| 1763 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 1764 | // .. OUTPUT_EN = 0x3 | ||
| 1765 | // .. ==> 0XF8000B4C[10:9] = 0x00000003U | ||
| 1766 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 1767 | // .. PULLUP_EN = 0x0 | ||
| 1768 | // .. ==> 0XF8000B4C[11:11] = 0x00000000U | ||
| 1769 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 1770 | // .. | ||
| 1771 | EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), | ||
| 1772 | // .. reserved_INP_POWER = 0x0 | ||
| 1773 | // .. ==> 0XF8000B50[0:0] = 0x00000000U | ||
| 1774 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 1775 | // .. INP_TYPE = 0x2 | ||
| 1776 | // .. ==> 0XF8000B50[2:1] = 0x00000002U | ||
| 1777 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | ||
| 1778 | // .. DCI_UPDATE_B = 0x0 | ||
| 1779 | // .. ==> 0XF8000B50[3:3] = 0x00000000U | ||
| 1780 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 1781 | // .. TERM_EN = 0x1 | ||
| 1782 | // .. ==> 0XF8000B50[4:4] = 0x00000001U | ||
| 1783 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 1784 | // .. DCI_TYPE = 0x3 | ||
| 1785 | // .. ==> 0XF8000B50[6:5] = 0x00000003U | ||
| 1786 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
| 1787 | // .. IBUF_DISABLE_MODE = 0 | ||
| 1788 | // .. ==> 0XF8000B50[7:7] = 0x00000000U | ||
| 1789 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 1790 | // .. TERM_DISABLE_MODE = 0 | ||
| 1791 | // .. ==> 0XF8000B50[8:8] = 0x00000000U | ||
| 1792 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 1793 | // .. OUTPUT_EN = 0x3 | ||
| 1794 | // .. ==> 0XF8000B50[10:9] = 0x00000003U | ||
| 1795 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 1796 | // .. PULLUP_EN = 0x0 | ||
| 1797 | // .. ==> 0XF8000B50[11:11] = 0x00000000U | ||
| 1798 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 1799 | // .. | ||
| 1800 | EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), | ||
| 1801 | // .. reserved_INP_POWER = 0x0 | ||
| 1802 | // .. ==> 0XF8000B54[0:0] = 0x00000000U | ||
| 1803 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 1804 | // .. INP_TYPE = 0x2 | ||
| 1805 | // .. ==> 0XF8000B54[2:1] = 0x00000002U | ||
| 1806 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | ||
| 1807 | // .. DCI_UPDATE_B = 0x0 | ||
| 1808 | // .. ==> 0XF8000B54[3:3] = 0x00000000U | ||
| 1809 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 1810 | // .. TERM_EN = 0x1 | ||
| 1811 | // .. ==> 0XF8000B54[4:4] = 0x00000001U | ||
| 1812 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 1813 | // .. DCI_TYPE = 0x3 | ||
| 1814 | // .. ==> 0XF8000B54[6:5] = 0x00000003U | ||
| 1815 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
| 1816 | // .. IBUF_DISABLE_MODE = 0 | ||
| 1817 | // .. ==> 0XF8000B54[7:7] = 0x00000000U | ||
| 1818 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 1819 | // .. TERM_DISABLE_MODE = 0 | ||
| 1820 | // .. ==> 0XF8000B54[8:8] = 0x00000000U | ||
| 1821 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 1822 | // .. OUTPUT_EN = 0x3 | ||
| 1823 | // .. ==> 0XF8000B54[10:9] = 0x00000003U | ||
| 1824 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 1825 | // .. PULLUP_EN = 0x0 | ||
| 1826 | // .. ==> 0XF8000B54[11:11] = 0x00000000U | ||
| 1827 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 1828 | // .. | ||
| 1829 | EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), | ||
| 1830 | // .. reserved_INP_POWER = 0x0 | ||
| 1831 | // .. ==> 0XF8000B58[0:0] = 0x00000000U | ||
| 1832 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 1833 | // .. INP_TYPE = 0x0 | ||
| 1834 | // .. ==> 0XF8000B58[2:1] = 0x00000000U | ||
| 1835 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
| 1836 | // .. DCI_UPDATE_B = 0x0 | ||
| 1837 | // .. ==> 0XF8000B58[3:3] = 0x00000000U | ||
| 1838 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 1839 | // .. TERM_EN = 0x0 | ||
| 1840 | // .. ==> 0XF8000B58[4:4] = 0x00000000U | ||
| 1841 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 1842 | // .. DCI_TYPE = 0x0 | ||
| 1843 | // .. ==> 0XF8000B58[6:5] = 0x00000000U | ||
| 1844 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
| 1845 | // .. IBUF_DISABLE_MODE = 0x0 | ||
| 1846 | // .. ==> 0XF8000B58[7:7] = 0x00000000U | ||
| 1847 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 1848 | // .. TERM_DISABLE_MODE = 0x0 | ||
| 1849 | // .. ==> 0XF8000B58[8:8] = 0x00000000U | ||
| 1850 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 1851 | // .. OUTPUT_EN = 0x3 | ||
| 1852 | // .. ==> 0XF8000B58[10:9] = 0x00000003U | ||
| 1853 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 1854 | // .. PULLUP_EN = 0x0 | ||
| 1855 | // .. ==> 0XF8000B58[11:11] = 0x00000000U | ||
| 1856 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 1857 | // .. | ||
| 1858 | EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), | ||
| 1859 | // .. reserved_DRIVE_P = 0x1c | ||
| 1860 | // .. ==> 0XF8000B5C[6:0] = 0x0000001CU | ||
| 1861 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
| 1862 | // .. reserved_DRIVE_N = 0xc | ||
| 1863 | // .. ==> 0XF8000B5C[13:7] = 0x0000000CU | ||
| 1864 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
| 1865 | // .. reserved_SLEW_P = 0x3 | ||
| 1866 | // .. ==> 0XF8000B5C[18:14] = 0x00000003U | ||
| 1867 | // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U | ||
| 1868 | // .. reserved_SLEW_N = 0x3 | ||
| 1869 | // .. ==> 0XF8000B5C[23:19] = 0x00000003U | ||
| 1870 | // .. ==> MASK : 0x00F80000U VAL : 0x00180000U | ||
| 1871 | // .. reserved_GTL = 0x0 | ||
| 1872 | // .. ==> 0XF8000B5C[26:24] = 0x00000000U | ||
| 1873 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
| 1874 | // .. reserved_RTERM = 0x0 | ||
| 1875 | // .. ==> 0XF8000B5C[31:27] = 0x00000000U | ||
| 1876 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
| 1877 | // .. | ||
| 1878 | EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), | ||
| 1879 | // .. reserved_DRIVE_P = 0x1c | ||
| 1880 | // .. ==> 0XF8000B60[6:0] = 0x0000001CU | ||
| 1881 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
| 1882 | // .. reserved_DRIVE_N = 0xc | ||
| 1883 | // .. ==> 0XF8000B60[13:7] = 0x0000000CU | ||
| 1884 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
| 1885 | // .. reserved_SLEW_P = 0x6 | ||
| 1886 | // .. ==> 0XF8000B60[18:14] = 0x00000006U | ||
| 1887 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
| 1888 | // .. reserved_SLEW_N = 0x1f | ||
| 1889 | // .. ==> 0XF8000B60[23:19] = 0x0000001FU | ||
| 1890 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
| 1891 | // .. reserved_GTL = 0x0 | ||
| 1892 | // .. ==> 0XF8000B60[26:24] = 0x00000000U | ||
| 1893 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
| 1894 | // .. reserved_RTERM = 0x0 | ||
| 1895 | // .. ==> 0XF8000B60[31:27] = 0x00000000U | ||
| 1896 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
| 1897 | // .. | ||
| 1898 | EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), | ||
| 1899 | // .. reserved_DRIVE_P = 0x1c | ||
| 1900 | // .. ==> 0XF8000B64[6:0] = 0x0000001CU | ||
| 1901 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
| 1902 | // .. reserved_DRIVE_N = 0xc | ||
| 1903 | // .. ==> 0XF8000B64[13:7] = 0x0000000CU | ||
| 1904 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
| 1905 | // .. reserved_SLEW_P = 0x6 | ||
| 1906 | // .. ==> 0XF8000B64[18:14] = 0x00000006U | ||
| 1907 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
| 1908 | // .. reserved_SLEW_N = 0x1f | ||
| 1909 | // .. ==> 0XF8000B64[23:19] = 0x0000001FU | ||
| 1910 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
| 1911 | // .. reserved_GTL = 0x0 | ||
| 1912 | // .. ==> 0XF8000B64[26:24] = 0x00000000U | ||
| 1913 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
| 1914 | // .. reserved_RTERM = 0x0 | ||
| 1915 | // .. ==> 0XF8000B64[31:27] = 0x00000000U | ||
| 1916 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
| 1917 | // .. | ||
| 1918 | EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), | ||
| 1919 | // .. reserved_DRIVE_P = 0x1c | ||
| 1920 | // .. ==> 0XF8000B68[6:0] = 0x0000001CU | ||
| 1921 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
| 1922 | // .. reserved_DRIVE_N = 0xc | ||
| 1923 | // .. ==> 0XF8000B68[13:7] = 0x0000000CU | ||
| 1924 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
| 1925 | // .. reserved_SLEW_P = 0x6 | ||
| 1926 | // .. ==> 0XF8000B68[18:14] = 0x00000006U | ||
| 1927 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
| 1928 | // .. reserved_SLEW_N = 0x1f | ||
| 1929 | // .. ==> 0XF8000B68[23:19] = 0x0000001FU | ||
| 1930 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
| 1931 | // .. reserved_GTL = 0x0 | ||
| 1932 | // .. ==> 0XF8000B68[26:24] = 0x00000000U | ||
| 1933 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
| 1934 | // .. reserved_RTERM = 0x0 | ||
| 1935 | // .. ==> 0XF8000B68[31:27] = 0x00000000U | ||
| 1936 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
| 1937 | // .. | ||
| 1938 | EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), | ||
| 1939 | // .. VREF_INT_EN = 0x0 | ||
| 1940 | // .. ==> 0XF8000B6C[0:0] = 0x00000000U | ||
| 1941 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 1942 | // .. VREF_SEL = 0x0 | ||
| 1943 | // .. ==> 0XF8000B6C[4:1] = 0x00000000U | ||
| 1944 | // .. ==> MASK : 0x0000001EU VAL : 0x00000000U | ||
| 1945 | // .. VREF_EXT_EN = 0x3 | ||
| 1946 | // .. ==> 0XF8000B6C[6:5] = 0x00000003U | ||
| 1947 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
| 1948 | // .. reserved_VREF_PULLUP_EN = 0x0 | ||
| 1949 | // .. ==> 0XF8000B6C[8:7] = 0x00000000U | ||
| 1950 | // .. ==> MASK : 0x00000180U VAL : 0x00000000U | ||
| 1951 | // .. REFIO_EN = 0x1 | ||
| 1952 | // .. ==> 0XF8000B6C[9:9] = 0x00000001U | ||
| 1953 | // .. ==> MASK : 0x00000200U VAL : 0x00000200U | ||
| 1954 | // .. reserved_REFIO_TEST = 0x0 | ||
| 1955 | // .. ==> 0XF8000B6C[11:10] = 0x00000000U | ||
| 1956 | // .. ==> MASK : 0x00000C00U VAL : 0x00000000U | ||
| 1957 | // .. reserved_REFIO_PULLUP_EN = 0x0 | ||
| 1958 | // .. ==> 0XF8000B6C[12:12] = 0x00000000U | ||
| 1959 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 1960 | // .. reserved_DRST_B_PULLUP_EN = 0x0 | ||
| 1961 | // .. ==> 0XF8000B6C[13:13] = 0x00000000U | ||
| 1962 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 1963 | // .. reserved_CKE_PULLUP_EN = 0x0 | ||
| 1964 | // .. ==> 0XF8000B6C[14:14] = 0x00000000U | ||
| 1965 | // .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
| 1966 | // .. | ||
| 1967 | EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), | ||
| 1968 | // .. .. START: ASSERT RESET | ||
| 1969 | // .. .. RESET = 1 | ||
| 1970 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | ||
| 1971 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 1972 | // .. .. | ||
| 1973 | EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), | ||
| 1974 | // .. .. FINISH: ASSERT RESET | ||
| 1975 | // .. .. START: DEASSERT RESET | ||
| 1976 | // .. .. RESET = 0 | ||
| 1977 | // .. .. ==> 0XF8000B70[0:0] = 0x00000000U | ||
| 1978 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 1979 | // .. .. reserved_VRN_OUT = 0x1 | ||
| 1980 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | ||
| 1981 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | ||
| 1982 | // .. .. | ||
| 1983 | EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), | ||
| 1984 | // .. .. FINISH: DEASSERT RESET | ||
| 1985 | // .. .. RESET = 0x1 | ||
| 1986 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | ||
| 1987 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 1988 | // .. .. ENABLE = 0x1 | ||
| 1989 | // .. .. ==> 0XF8000B70[1:1] = 0x00000001U | ||
| 1990 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 1991 | // .. .. reserved_VRP_TRI = 0x0 | ||
| 1992 | // .. .. ==> 0XF8000B70[2:2] = 0x00000000U | ||
| 1993 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 1994 | // .. .. reserved_VRN_TRI = 0x0 | ||
| 1995 | // .. .. ==> 0XF8000B70[3:3] = 0x00000000U | ||
| 1996 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 1997 | // .. .. reserved_VRP_OUT = 0x0 | ||
| 1998 | // .. .. ==> 0XF8000B70[4:4] = 0x00000000U | ||
| 1999 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 2000 | // .. .. reserved_VRN_OUT = 0x1 | ||
| 2001 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | ||
| 2002 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | ||
| 2003 | // .. .. NREF_OPT1 = 0x0 | ||
| 2004 | // .. .. ==> 0XF8000B70[7:6] = 0x00000000U | ||
| 2005 | // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U | ||
| 2006 | // .. .. NREF_OPT2 = 0x0 | ||
| 2007 | // .. .. ==> 0XF8000B70[10:8] = 0x00000000U | ||
| 2008 | // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U | ||
| 2009 | // .. .. NREF_OPT4 = 0x1 | ||
| 2010 | // .. .. ==> 0XF8000B70[13:11] = 0x00000001U | ||
| 2011 | // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U | ||
| 2012 | // .. .. PREF_OPT1 = 0x0 | ||
| 2013 | // .. .. ==> 0XF8000B70[15:14] = 0x00000000U | ||
| 2014 | // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U | ||
| 2015 | // .. .. PREF_OPT2 = 0x0 | ||
| 2016 | // .. .. ==> 0XF8000B70[19:17] = 0x00000000U | ||
| 2017 | // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U | ||
| 2018 | // .. .. UPDATE_CONTROL = 0x0 | ||
| 2019 | // .. .. ==> 0XF8000B70[20:20] = 0x00000000U | ||
| 2020 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
| 2021 | // .. .. reserved_INIT_COMPLETE = 0x0 | ||
| 2022 | // .. .. ==> 0XF8000B70[21:21] = 0x00000000U | ||
| 2023 | // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U | ||
| 2024 | // .. .. reserved_TST_CLK = 0x0 | ||
| 2025 | // .. .. ==> 0XF8000B70[22:22] = 0x00000000U | ||
| 2026 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
| 2027 | // .. .. reserved_TST_HLN = 0x0 | ||
| 2028 | // .. .. ==> 0XF8000B70[23:23] = 0x00000000U | ||
| 2029 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
| 2030 | // .. .. reserved_TST_HLP = 0x0 | ||
| 2031 | // .. .. ==> 0XF8000B70[24:24] = 0x00000000U | ||
| 2032 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
| 2033 | // .. .. reserved_TST_RST = 0x0 | ||
| 2034 | // .. .. ==> 0XF8000B70[25:25] = 0x00000000U | ||
| 2035 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
| 2036 | // .. .. reserved_INT_DCI_EN = 0x0 | ||
| 2037 | // .. .. ==> 0XF8000B70[26:26] = 0x00000000U | ||
| 2038 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | ||
| 2039 | // .. .. | ||
| 2040 | EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), | ||
| 2041 | // .. FINISH: DDRIOB SETTINGS | ||
| 2042 | // .. START: MIO PROGRAMMING | ||
| 2043 | // .. TRI_ENABLE = 0 | ||
| 2044 | // .. ==> 0XF8000704[0:0] = 0x00000000U | ||
| 2045 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2046 | // .. L0_SEL = 1 | ||
| 2047 | // .. ==> 0XF8000704[1:1] = 0x00000001U | ||
| 2048 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2049 | // .. L1_SEL = 0 | ||
| 2050 | // .. ==> 0XF8000704[2:2] = 0x00000000U | ||
| 2051 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2052 | // .. L2_SEL = 0 | ||
| 2053 | // .. ==> 0XF8000704[4:3] = 0x00000000U | ||
| 2054 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2055 | // .. L3_SEL = 0 | ||
| 2056 | // .. ==> 0XF8000704[7:5] = 0x00000000U | ||
| 2057 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2058 | // .. Speed = 1 | ||
| 2059 | // .. ==> 0XF8000704[8:8] = 0x00000001U | ||
| 2060 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2061 | // .. IO_Type = 3 | ||
| 2062 | // .. ==> 0XF8000704[11:9] = 0x00000003U | ||
| 2063 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 2064 | // .. PULLUP = 0 | ||
| 2065 | // .. ==> 0XF8000704[12:12] = 0x00000000U | ||
| 2066 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2067 | // .. DisableRcvr = 0 | ||
| 2068 | // .. ==> 0XF8000704[13:13] = 0x00000000U | ||
| 2069 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2070 | // .. | ||
| 2071 | EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U), | ||
| 2072 | // .. TRI_ENABLE = 0 | ||
| 2073 | // .. ==> 0XF8000708[0:0] = 0x00000000U | ||
| 2074 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2075 | // .. L0_SEL = 1 | ||
| 2076 | // .. ==> 0XF8000708[1:1] = 0x00000001U | ||
| 2077 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2078 | // .. L1_SEL = 0 | ||
| 2079 | // .. ==> 0XF8000708[2:2] = 0x00000000U | ||
| 2080 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2081 | // .. L2_SEL = 0 | ||
| 2082 | // .. ==> 0XF8000708[4:3] = 0x00000000U | ||
| 2083 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2084 | // .. L3_SEL = 0 | ||
| 2085 | // .. ==> 0XF8000708[7:5] = 0x00000000U | ||
| 2086 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2087 | // .. Speed = 1 | ||
| 2088 | // .. ==> 0XF8000708[8:8] = 0x00000001U | ||
| 2089 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2090 | // .. IO_Type = 3 | ||
| 2091 | // .. ==> 0XF8000708[11:9] = 0x00000003U | ||
| 2092 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 2093 | // .. PULLUP = 0 | ||
| 2094 | // .. ==> 0XF8000708[12:12] = 0x00000000U | ||
| 2095 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2096 | // .. DisableRcvr = 0 | ||
| 2097 | // .. ==> 0XF8000708[13:13] = 0x00000000U | ||
| 2098 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2099 | // .. | ||
| 2100 | EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U), | ||
| 2101 | // .. TRI_ENABLE = 0 | ||
| 2102 | // .. ==> 0XF800070C[0:0] = 0x00000000U | ||
| 2103 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2104 | // .. L0_SEL = 1 | ||
| 2105 | // .. ==> 0XF800070C[1:1] = 0x00000001U | ||
| 2106 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2107 | // .. L1_SEL = 0 | ||
| 2108 | // .. ==> 0XF800070C[2:2] = 0x00000000U | ||
| 2109 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2110 | // .. L2_SEL = 0 | ||
| 2111 | // .. ==> 0XF800070C[4:3] = 0x00000000U | ||
| 2112 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2113 | // .. L3_SEL = 0 | ||
| 2114 | // .. ==> 0XF800070C[7:5] = 0x00000000U | ||
| 2115 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2116 | // .. Speed = 1 | ||
| 2117 | // .. ==> 0XF800070C[8:8] = 0x00000001U | ||
| 2118 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2119 | // .. IO_Type = 3 | ||
| 2120 | // .. ==> 0XF800070C[11:9] = 0x00000003U | ||
| 2121 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 2122 | // .. PULLUP = 0 | ||
| 2123 | // .. ==> 0XF800070C[12:12] = 0x00000000U | ||
| 2124 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2125 | // .. DisableRcvr = 0 | ||
| 2126 | // .. ==> 0XF800070C[13:13] = 0x00000000U | ||
| 2127 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2128 | // .. | ||
| 2129 | EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U), | ||
| 2130 | // .. TRI_ENABLE = 0 | ||
| 2131 | // .. ==> 0XF8000710[0:0] = 0x00000000U | ||
| 2132 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2133 | // .. L0_SEL = 1 | ||
| 2134 | // .. ==> 0XF8000710[1:1] = 0x00000001U | ||
| 2135 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2136 | // .. L1_SEL = 0 | ||
| 2137 | // .. ==> 0XF8000710[2:2] = 0x00000000U | ||
| 2138 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2139 | // .. L2_SEL = 0 | ||
| 2140 | // .. ==> 0XF8000710[4:3] = 0x00000000U | ||
| 2141 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2142 | // .. L3_SEL = 0 | ||
| 2143 | // .. ==> 0XF8000710[7:5] = 0x00000000U | ||
| 2144 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2145 | // .. Speed = 1 | ||
| 2146 | // .. ==> 0XF8000710[8:8] = 0x00000001U | ||
| 2147 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2148 | // .. IO_Type = 3 | ||
| 2149 | // .. ==> 0XF8000710[11:9] = 0x00000003U | ||
| 2150 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 2151 | // .. PULLUP = 0 | ||
| 2152 | // .. ==> 0XF8000710[12:12] = 0x00000000U | ||
| 2153 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2154 | // .. DisableRcvr = 0 | ||
| 2155 | // .. ==> 0XF8000710[13:13] = 0x00000000U | ||
| 2156 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2157 | // .. | ||
| 2158 | EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U), | ||
| 2159 | // .. TRI_ENABLE = 0 | ||
| 2160 | // .. ==> 0XF8000714[0:0] = 0x00000000U | ||
| 2161 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2162 | // .. L0_SEL = 1 | ||
| 2163 | // .. ==> 0XF8000714[1:1] = 0x00000001U | ||
| 2164 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2165 | // .. L1_SEL = 0 | ||
| 2166 | // .. ==> 0XF8000714[2:2] = 0x00000000U | ||
| 2167 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2168 | // .. L2_SEL = 0 | ||
| 2169 | // .. ==> 0XF8000714[4:3] = 0x00000000U | ||
| 2170 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2171 | // .. L3_SEL = 0 | ||
| 2172 | // .. ==> 0XF8000714[7:5] = 0x00000000U | ||
| 2173 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2174 | // .. Speed = 1 | ||
| 2175 | // .. ==> 0XF8000714[8:8] = 0x00000001U | ||
| 2176 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2177 | // .. IO_Type = 3 | ||
| 2178 | // .. ==> 0XF8000714[11:9] = 0x00000003U | ||
| 2179 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 2180 | // .. PULLUP = 0 | ||
| 2181 | // .. ==> 0XF8000714[12:12] = 0x00000000U | ||
| 2182 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2183 | // .. DisableRcvr = 0 | ||
| 2184 | // .. ==> 0XF8000714[13:13] = 0x00000000U | ||
| 2185 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2186 | // .. | ||
| 2187 | EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U), | ||
| 2188 | // .. TRI_ENABLE = 0 | ||
| 2189 | // .. ==> 0XF8000718[0:0] = 0x00000000U | ||
| 2190 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2191 | // .. L0_SEL = 1 | ||
| 2192 | // .. ==> 0XF8000718[1:1] = 0x00000001U | ||
| 2193 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2194 | // .. L1_SEL = 0 | ||
| 2195 | // .. ==> 0XF8000718[2:2] = 0x00000000U | ||
| 2196 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2197 | // .. L2_SEL = 0 | ||
| 2198 | // .. ==> 0XF8000718[4:3] = 0x00000000U | ||
| 2199 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2200 | // .. L3_SEL = 0 | ||
| 2201 | // .. ==> 0XF8000718[7:5] = 0x00000000U | ||
| 2202 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2203 | // .. Speed = 1 | ||
| 2204 | // .. ==> 0XF8000718[8:8] = 0x00000001U | ||
| 2205 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2206 | // .. IO_Type = 3 | ||
| 2207 | // .. ==> 0XF8000718[11:9] = 0x00000003U | ||
| 2208 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 2209 | // .. PULLUP = 0 | ||
| 2210 | // .. ==> 0XF8000718[12:12] = 0x00000000U | ||
| 2211 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2212 | // .. DisableRcvr = 0 | ||
| 2213 | // .. ==> 0XF8000718[13:13] = 0x00000000U | ||
| 2214 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2215 | // .. | ||
| 2216 | EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U), | ||
| 2217 | // .. TRI_ENABLE = 0 | ||
| 2218 | // .. ==> 0XF8000740[0:0] = 0x00000000U | ||
| 2219 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2220 | // .. L0_SEL = 1 | ||
| 2221 | // .. ==> 0XF8000740[1:1] = 0x00000001U | ||
| 2222 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2223 | // .. L1_SEL = 0 | ||
| 2224 | // .. ==> 0XF8000740[2:2] = 0x00000000U | ||
| 2225 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2226 | // .. L2_SEL = 0 | ||
| 2227 | // .. ==> 0XF8000740[4:3] = 0x00000000U | ||
| 2228 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2229 | // .. L3_SEL = 0 | ||
| 2230 | // .. ==> 0XF8000740[7:5] = 0x00000000U | ||
| 2231 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2232 | // .. Speed = 1 | ||
| 2233 | // .. ==> 0XF8000740[8:8] = 0x00000001U | ||
| 2234 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2235 | // .. IO_Type = 4 | ||
| 2236 | // .. ==> 0XF8000740[11:9] = 0x00000004U | ||
| 2237 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 2238 | // .. PULLUP = 0 | ||
| 2239 | // .. ==> 0XF8000740[12:12] = 0x00000000U | ||
| 2240 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2241 | // .. DisableRcvr = 1 | ||
| 2242 | // .. ==> 0XF8000740[13:13] = 0x00000001U | ||
| 2243 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 2244 | // .. | ||
| 2245 | EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U), | ||
| 2246 | // .. TRI_ENABLE = 0 | ||
| 2247 | // .. ==> 0XF8000744[0:0] = 0x00000000U | ||
| 2248 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2249 | // .. L0_SEL = 1 | ||
| 2250 | // .. ==> 0XF8000744[1:1] = 0x00000001U | ||
| 2251 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2252 | // .. L1_SEL = 0 | ||
| 2253 | // .. ==> 0XF8000744[2:2] = 0x00000000U | ||
| 2254 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2255 | // .. L2_SEL = 0 | ||
| 2256 | // .. ==> 0XF8000744[4:3] = 0x00000000U | ||
| 2257 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2258 | // .. L3_SEL = 0 | ||
| 2259 | // .. ==> 0XF8000744[7:5] = 0x00000000U | ||
| 2260 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2261 | // .. Speed = 1 | ||
| 2262 | // .. ==> 0XF8000744[8:8] = 0x00000001U | ||
| 2263 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2264 | // .. IO_Type = 4 | ||
| 2265 | // .. ==> 0XF8000744[11:9] = 0x00000004U | ||
| 2266 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 2267 | // .. PULLUP = 0 | ||
| 2268 | // .. ==> 0XF8000744[12:12] = 0x00000000U | ||
| 2269 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2270 | // .. DisableRcvr = 1 | ||
| 2271 | // .. ==> 0XF8000744[13:13] = 0x00000001U | ||
| 2272 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 2273 | // .. | ||
| 2274 | EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U), | ||
| 2275 | // .. TRI_ENABLE = 0 | ||
| 2276 | // .. ==> 0XF8000748[0:0] = 0x00000000U | ||
| 2277 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2278 | // .. L0_SEL = 1 | ||
| 2279 | // .. ==> 0XF8000748[1:1] = 0x00000001U | ||
| 2280 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2281 | // .. L1_SEL = 0 | ||
| 2282 | // .. ==> 0XF8000748[2:2] = 0x00000000U | ||
| 2283 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2284 | // .. L2_SEL = 0 | ||
| 2285 | // .. ==> 0XF8000748[4:3] = 0x00000000U | ||
| 2286 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2287 | // .. L3_SEL = 0 | ||
| 2288 | // .. ==> 0XF8000748[7:5] = 0x00000000U | ||
| 2289 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2290 | // .. Speed = 1 | ||
| 2291 | // .. ==> 0XF8000748[8:8] = 0x00000001U | ||
| 2292 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2293 | // .. IO_Type = 4 | ||
| 2294 | // .. ==> 0XF8000748[11:9] = 0x00000004U | ||
| 2295 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 2296 | // .. PULLUP = 0 | ||
| 2297 | // .. ==> 0XF8000748[12:12] = 0x00000000U | ||
| 2298 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2299 | // .. DisableRcvr = 1 | ||
| 2300 | // .. ==> 0XF8000748[13:13] = 0x00000001U | ||
| 2301 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 2302 | // .. | ||
| 2303 | EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U), | ||
| 2304 | // .. TRI_ENABLE = 0 | ||
| 2305 | // .. ==> 0XF800074C[0:0] = 0x00000000U | ||
| 2306 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2307 | // .. L0_SEL = 1 | ||
| 2308 | // .. ==> 0XF800074C[1:1] = 0x00000001U | ||
| 2309 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2310 | // .. L1_SEL = 0 | ||
| 2311 | // .. ==> 0XF800074C[2:2] = 0x00000000U | ||
| 2312 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2313 | // .. L2_SEL = 0 | ||
| 2314 | // .. ==> 0XF800074C[4:3] = 0x00000000U | ||
| 2315 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2316 | // .. L3_SEL = 0 | ||
| 2317 | // .. ==> 0XF800074C[7:5] = 0x00000000U | ||
| 2318 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2319 | // .. Speed = 1 | ||
| 2320 | // .. ==> 0XF800074C[8:8] = 0x00000001U | ||
| 2321 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2322 | // .. IO_Type = 4 | ||
| 2323 | // .. ==> 0XF800074C[11:9] = 0x00000004U | ||
| 2324 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 2325 | // .. PULLUP = 0 | ||
| 2326 | // .. ==> 0XF800074C[12:12] = 0x00000000U | ||
| 2327 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2328 | // .. DisableRcvr = 1 | ||
| 2329 | // .. ==> 0XF800074C[13:13] = 0x00000001U | ||
| 2330 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 2331 | // .. | ||
| 2332 | EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U), | ||
| 2333 | // .. TRI_ENABLE = 0 | ||
| 2334 | // .. ==> 0XF8000750[0:0] = 0x00000000U | ||
| 2335 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2336 | // .. L0_SEL = 1 | ||
| 2337 | // .. ==> 0XF8000750[1:1] = 0x00000001U | ||
| 2338 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2339 | // .. L1_SEL = 0 | ||
| 2340 | // .. ==> 0XF8000750[2:2] = 0x00000000U | ||
| 2341 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2342 | // .. L2_SEL = 0 | ||
| 2343 | // .. ==> 0XF8000750[4:3] = 0x00000000U | ||
| 2344 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2345 | // .. L3_SEL = 0 | ||
| 2346 | // .. ==> 0XF8000750[7:5] = 0x00000000U | ||
| 2347 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2348 | // .. Speed = 1 | ||
| 2349 | // .. ==> 0XF8000750[8:8] = 0x00000001U | ||
| 2350 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2351 | // .. IO_Type = 4 | ||
| 2352 | // .. ==> 0XF8000750[11:9] = 0x00000004U | ||
| 2353 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 2354 | // .. PULLUP = 0 | ||
| 2355 | // .. ==> 0XF8000750[12:12] = 0x00000000U | ||
| 2356 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2357 | // .. DisableRcvr = 1 | ||
| 2358 | // .. ==> 0XF8000750[13:13] = 0x00000001U | ||
| 2359 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 2360 | // .. | ||
| 2361 | EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U), | ||
| 2362 | // .. TRI_ENABLE = 0 | ||
| 2363 | // .. ==> 0XF8000754[0:0] = 0x00000000U | ||
| 2364 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2365 | // .. L0_SEL = 1 | ||
| 2366 | // .. ==> 0XF8000754[1:1] = 0x00000001U | ||
| 2367 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2368 | // .. L1_SEL = 0 | ||
| 2369 | // .. ==> 0XF8000754[2:2] = 0x00000000U | ||
| 2370 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2371 | // .. L2_SEL = 0 | ||
| 2372 | // .. ==> 0XF8000754[4:3] = 0x00000000U | ||
| 2373 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2374 | // .. L3_SEL = 0 | ||
| 2375 | // .. ==> 0XF8000754[7:5] = 0x00000000U | ||
| 2376 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2377 | // .. Speed = 1 | ||
| 2378 | // .. ==> 0XF8000754[8:8] = 0x00000001U | ||
| 2379 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2380 | // .. IO_Type = 4 | ||
| 2381 | // .. ==> 0XF8000754[11:9] = 0x00000004U | ||
| 2382 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 2383 | // .. PULLUP = 0 | ||
| 2384 | // .. ==> 0XF8000754[12:12] = 0x00000000U | ||
| 2385 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2386 | // .. DisableRcvr = 1 | ||
| 2387 | // .. ==> 0XF8000754[13:13] = 0x00000001U | ||
| 2388 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 2389 | // .. | ||
| 2390 | EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U), | ||
| 2391 | // .. TRI_ENABLE = 1 | ||
| 2392 | // .. ==> 0XF8000758[0:0] = 0x00000001U | ||
| 2393 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 2394 | // .. L0_SEL = 1 | ||
| 2395 | // .. ==> 0XF8000758[1:1] = 0x00000001U | ||
| 2396 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2397 | // .. L1_SEL = 0 | ||
| 2398 | // .. ==> 0XF8000758[2:2] = 0x00000000U | ||
| 2399 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2400 | // .. L2_SEL = 0 | ||
| 2401 | // .. ==> 0XF8000758[4:3] = 0x00000000U | ||
| 2402 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2403 | // .. L3_SEL = 0 | ||
| 2404 | // .. ==> 0XF8000758[7:5] = 0x00000000U | ||
| 2405 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2406 | // .. Speed = 1 | ||
| 2407 | // .. ==> 0XF8000758[8:8] = 0x00000001U | ||
| 2408 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2409 | // .. IO_Type = 4 | ||
| 2410 | // .. ==> 0XF8000758[11:9] = 0x00000004U | ||
| 2411 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 2412 | // .. PULLUP = 0 | ||
| 2413 | // .. ==> 0XF8000758[12:12] = 0x00000000U | ||
| 2414 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2415 | // .. DisableRcvr = 0 | ||
| 2416 | // .. ==> 0XF8000758[13:13] = 0x00000000U | ||
| 2417 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2418 | // .. | ||
| 2419 | EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U), | ||
| 2420 | // .. TRI_ENABLE = 1 | ||
| 2421 | // .. ==> 0XF800075C[0:0] = 0x00000001U | ||
| 2422 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 2423 | // .. L0_SEL = 1 | ||
| 2424 | // .. ==> 0XF800075C[1:1] = 0x00000001U | ||
| 2425 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2426 | // .. L1_SEL = 0 | ||
| 2427 | // .. ==> 0XF800075C[2:2] = 0x00000000U | ||
| 2428 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2429 | // .. L2_SEL = 0 | ||
| 2430 | // .. ==> 0XF800075C[4:3] = 0x00000000U | ||
| 2431 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2432 | // .. L3_SEL = 0 | ||
| 2433 | // .. ==> 0XF800075C[7:5] = 0x00000000U | ||
| 2434 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2435 | // .. Speed = 1 | ||
| 2436 | // .. ==> 0XF800075C[8:8] = 0x00000001U | ||
| 2437 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2438 | // .. IO_Type = 4 | ||
| 2439 | // .. ==> 0XF800075C[11:9] = 0x00000004U | ||
| 2440 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 2441 | // .. PULLUP = 0 | ||
| 2442 | // .. ==> 0XF800075C[12:12] = 0x00000000U | ||
| 2443 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2444 | // .. DisableRcvr = 0 | ||
| 2445 | // .. ==> 0XF800075C[13:13] = 0x00000000U | ||
| 2446 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2447 | // .. | ||
| 2448 | EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U), | ||
| 2449 | // .. TRI_ENABLE = 1 | ||
| 2450 | // .. ==> 0XF8000760[0:0] = 0x00000001U | ||
| 2451 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 2452 | // .. L0_SEL = 1 | ||
| 2453 | // .. ==> 0XF8000760[1:1] = 0x00000001U | ||
| 2454 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2455 | // .. L1_SEL = 0 | ||
| 2456 | // .. ==> 0XF8000760[2:2] = 0x00000000U | ||
| 2457 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2458 | // .. L2_SEL = 0 | ||
| 2459 | // .. ==> 0XF8000760[4:3] = 0x00000000U | ||
| 2460 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2461 | // .. L3_SEL = 0 | ||
| 2462 | // .. ==> 0XF8000760[7:5] = 0x00000000U | ||
| 2463 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2464 | // .. Speed = 1 | ||
| 2465 | // .. ==> 0XF8000760[8:8] = 0x00000001U | ||
| 2466 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2467 | // .. IO_Type = 4 | ||
| 2468 | // .. ==> 0XF8000760[11:9] = 0x00000004U | ||
| 2469 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 2470 | // .. PULLUP = 0 | ||
| 2471 | // .. ==> 0XF8000760[12:12] = 0x00000000U | ||
| 2472 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2473 | // .. DisableRcvr = 0 | ||
| 2474 | // .. ==> 0XF8000760[13:13] = 0x00000000U | ||
| 2475 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2476 | // .. | ||
| 2477 | EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U), | ||
| 2478 | // .. TRI_ENABLE = 1 | ||
| 2479 | // .. ==> 0XF8000764[0:0] = 0x00000001U | ||
| 2480 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 2481 | // .. L0_SEL = 1 | ||
| 2482 | // .. ==> 0XF8000764[1:1] = 0x00000001U | ||
| 2483 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2484 | // .. L1_SEL = 0 | ||
| 2485 | // .. ==> 0XF8000764[2:2] = 0x00000000U | ||
| 2486 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2487 | // .. L2_SEL = 0 | ||
| 2488 | // .. ==> 0XF8000764[4:3] = 0x00000000U | ||
| 2489 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2490 | // .. L3_SEL = 0 | ||
| 2491 | // .. ==> 0XF8000764[7:5] = 0x00000000U | ||
| 2492 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2493 | // .. Speed = 1 | ||
| 2494 | // .. ==> 0XF8000764[8:8] = 0x00000001U | ||
| 2495 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2496 | // .. IO_Type = 4 | ||
| 2497 | // .. ==> 0XF8000764[11:9] = 0x00000004U | ||
| 2498 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 2499 | // .. PULLUP = 0 | ||
| 2500 | // .. ==> 0XF8000764[12:12] = 0x00000000U | ||
| 2501 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2502 | // .. DisableRcvr = 0 | ||
| 2503 | // .. ==> 0XF8000764[13:13] = 0x00000000U | ||
| 2504 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2505 | // .. | ||
| 2506 | EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U), | ||
| 2507 | // .. TRI_ENABLE = 1 | ||
| 2508 | // .. ==> 0XF8000768[0:0] = 0x00000001U | ||
| 2509 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 2510 | // .. L0_SEL = 1 | ||
| 2511 | // .. ==> 0XF8000768[1:1] = 0x00000001U | ||
| 2512 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2513 | // .. L1_SEL = 0 | ||
| 2514 | // .. ==> 0XF8000768[2:2] = 0x00000000U | ||
| 2515 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2516 | // .. L2_SEL = 0 | ||
| 2517 | // .. ==> 0XF8000768[4:3] = 0x00000000U | ||
| 2518 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2519 | // .. L3_SEL = 0 | ||
| 2520 | // .. ==> 0XF8000768[7:5] = 0x00000000U | ||
| 2521 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2522 | // .. Speed = 1 | ||
| 2523 | // .. ==> 0XF8000768[8:8] = 0x00000001U | ||
| 2524 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2525 | // .. IO_Type = 4 | ||
| 2526 | // .. ==> 0XF8000768[11:9] = 0x00000004U | ||
| 2527 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 2528 | // .. PULLUP = 0 | ||
| 2529 | // .. ==> 0XF8000768[12:12] = 0x00000000U | ||
| 2530 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2531 | // .. DisableRcvr = 0 | ||
| 2532 | // .. ==> 0XF8000768[13:13] = 0x00000000U | ||
| 2533 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2534 | // .. | ||
| 2535 | EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U), | ||
| 2536 | // .. TRI_ENABLE = 1 | ||
| 2537 | // .. ==> 0XF800076C[0:0] = 0x00000001U | ||
| 2538 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 2539 | // .. L0_SEL = 1 | ||
| 2540 | // .. ==> 0XF800076C[1:1] = 0x00000001U | ||
| 2541 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 2542 | // .. L1_SEL = 0 | ||
| 2543 | // .. ==> 0XF800076C[2:2] = 0x00000000U | ||
| 2544 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2545 | // .. L2_SEL = 0 | ||
| 2546 | // .. ==> 0XF800076C[4:3] = 0x00000000U | ||
| 2547 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2548 | // .. L3_SEL = 0 | ||
| 2549 | // .. ==> 0XF800076C[7:5] = 0x00000000U | ||
| 2550 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2551 | // .. Speed = 1 | ||
| 2552 | // .. ==> 0XF800076C[8:8] = 0x00000001U | ||
| 2553 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2554 | // .. IO_Type = 4 | ||
| 2555 | // .. ==> 0XF800076C[11:9] = 0x00000004U | ||
| 2556 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 2557 | // .. PULLUP = 0 | ||
| 2558 | // .. ==> 0XF800076C[12:12] = 0x00000000U | ||
| 2559 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2560 | // .. DisableRcvr = 0 | ||
| 2561 | // .. ==> 0XF800076C[13:13] = 0x00000000U | ||
| 2562 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2563 | // .. | ||
| 2564 | EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U), | ||
| 2565 | // .. TRI_ENABLE = 0 | ||
| 2566 | // .. ==> 0XF8000770[0:0] = 0x00000000U | ||
| 2567 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2568 | // .. L0_SEL = 0 | ||
| 2569 | // .. ==> 0XF8000770[1:1] = 0x00000000U | ||
| 2570 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 2571 | // .. L1_SEL = 1 | ||
| 2572 | // .. ==> 0XF8000770[2:2] = 0x00000001U | ||
| 2573 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 2574 | // .. L2_SEL = 0 | ||
| 2575 | // .. ==> 0XF8000770[4:3] = 0x00000000U | ||
| 2576 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2577 | // .. L3_SEL = 0 | ||
| 2578 | // .. ==> 0XF8000770[7:5] = 0x00000000U | ||
| 2579 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2580 | // .. Speed = 1 | ||
| 2581 | // .. ==> 0XF8000770[8:8] = 0x00000001U | ||
| 2582 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2583 | // .. IO_Type = 1 | ||
| 2584 | // .. ==> 0XF8000770[11:9] = 0x00000001U | ||
| 2585 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 2586 | // .. PULLUP = 0 | ||
| 2587 | // .. ==> 0XF8000770[12:12] = 0x00000000U | ||
| 2588 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2589 | // .. DisableRcvr = 0 | ||
| 2590 | // .. ==> 0XF8000770[13:13] = 0x00000000U | ||
| 2591 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2592 | // .. | ||
| 2593 | EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U), | ||
| 2594 | // .. TRI_ENABLE = 1 | ||
| 2595 | // .. ==> 0XF8000774[0:0] = 0x00000001U | ||
| 2596 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 2597 | // .. L0_SEL = 0 | ||
| 2598 | // .. ==> 0XF8000774[1:1] = 0x00000000U | ||
| 2599 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 2600 | // .. L1_SEL = 1 | ||
| 2601 | // .. ==> 0XF8000774[2:2] = 0x00000001U | ||
| 2602 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 2603 | // .. L2_SEL = 0 | ||
| 2604 | // .. ==> 0XF8000774[4:3] = 0x00000000U | ||
| 2605 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2606 | // .. L3_SEL = 0 | ||
| 2607 | // .. ==> 0XF8000774[7:5] = 0x00000000U | ||
| 2608 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2609 | // .. Speed = 1 | ||
| 2610 | // .. ==> 0XF8000774[8:8] = 0x00000001U | ||
| 2611 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2612 | // .. IO_Type = 1 | ||
| 2613 | // .. ==> 0XF8000774[11:9] = 0x00000001U | ||
| 2614 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 2615 | // .. PULLUP = 0 | ||
| 2616 | // .. ==> 0XF8000774[12:12] = 0x00000000U | ||
| 2617 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2618 | // .. DisableRcvr = 0 | ||
| 2619 | // .. ==> 0XF8000774[13:13] = 0x00000000U | ||
| 2620 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2621 | // .. | ||
| 2622 | EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U), | ||
| 2623 | // .. TRI_ENABLE = 0 | ||
| 2624 | // .. ==> 0XF8000778[0:0] = 0x00000000U | ||
| 2625 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2626 | // .. L0_SEL = 0 | ||
| 2627 | // .. ==> 0XF8000778[1:1] = 0x00000000U | ||
| 2628 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 2629 | // .. L1_SEL = 1 | ||
| 2630 | // .. ==> 0XF8000778[2:2] = 0x00000001U | ||
| 2631 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 2632 | // .. L2_SEL = 0 | ||
| 2633 | // .. ==> 0XF8000778[4:3] = 0x00000000U | ||
| 2634 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2635 | // .. L3_SEL = 0 | ||
| 2636 | // .. ==> 0XF8000778[7:5] = 0x00000000U | ||
| 2637 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2638 | // .. Speed = 1 | ||
| 2639 | // .. ==> 0XF8000778[8:8] = 0x00000001U | ||
| 2640 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2641 | // .. IO_Type = 1 | ||
| 2642 | // .. ==> 0XF8000778[11:9] = 0x00000001U | ||
| 2643 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 2644 | // .. PULLUP = 0 | ||
| 2645 | // .. ==> 0XF8000778[12:12] = 0x00000000U | ||
| 2646 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2647 | // .. DisableRcvr = 0 | ||
| 2648 | // .. ==> 0XF8000778[13:13] = 0x00000000U | ||
| 2649 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2650 | // .. | ||
| 2651 | EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U), | ||
| 2652 | // .. TRI_ENABLE = 1 | ||
| 2653 | // .. ==> 0XF800077C[0:0] = 0x00000001U | ||
| 2654 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 2655 | // .. L0_SEL = 0 | ||
| 2656 | // .. ==> 0XF800077C[1:1] = 0x00000000U | ||
| 2657 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 2658 | // .. L1_SEL = 1 | ||
| 2659 | // .. ==> 0XF800077C[2:2] = 0x00000001U | ||
| 2660 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 2661 | // .. L2_SEL = 0 | ||
| 2662 | // .. ==> 0XF800077C[4:3] = 0x00000000U | ||
| 2663 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2664 | // .. L3_SEL = 0 | ||
| 2665 | // .. ==> 0XF800077C[7:5] = 0x00000000U | ||
| 2666 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2667 | // .. Speed = 1 | ||
| 2668 | // .. ==> 0XF800077C[8:8] = 0x00000001U | ||
| 2669 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2670 | // .. IO_Type = 1 | ||
| 2671 | // .. ==> 0XF800077C[11:9] = 0x00000001U | ||
| 2672 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 2673 | // .. PULLUP = 0 | ||
| 2674 | // .. ==> 0XF800077C[12:12] = 0x00000000U | ||
| 2675 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2676 | // .. DisableRcvr = 0 | ||
| 2677 | // .. ==> 0XF800077C[13:13] = 0x00000000U | ||
| 2678 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2679 | // .. | ||
| 2680 | EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U), | ||
| 2681 | // .. TRI_ENABLE = 0 | ||
| 2682 | // .. ==> 0XF8000780[0:0] = 0x00000000U | ||
| 2683 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2684 | // .. L0_SEL = 0 | ||
| 2685 | // .. ==> 0XF8000780[1:1] = 0x00000000U | ||
| 2686 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 2687 | // .. L1_SEL = 1 | ||
| 2688 | // .. ==> 0XF8000780[2:2] = 0x00000001U | ||
| 2689 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 2690 | // .. L2_SEL = 0 | ||
| 2691 | // .. ==> 0XF8000780[4:3] = 0x00000000U | ||
| 2692 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2693 | // .. L3_SEL = 0 | ||
| 2694 | // .. ==> 0XF8000780[7:5] = 0x00000000U | ||
| 2695 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2696 | // .. Speed = 1 | ||
| 2697 | // .. ==> 0XF8000780[8:8] = 0x00000001U | ||
| 2698 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2699 | // .. IO_Type = 1 | ||
| 2700 | // .. ==> 0XF8000780[11:9] = 0x00000001U | ||
| 2701 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 2702 | // .. PULLUP = 0 | ||
| 2703 | // .. ==> 0XF8000780[12:12] = 0x00000000U | ||
| 2704 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2705 | // .. DisableRcvr = 0 | ||
| 2706 | // .. ==> 0XF8000780[13:13] = 0x00000000U | ||
| 2707 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2708 | // .. | ||
| 2709 | EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U), | ||
| 2710 | // .. TRI_ENABLE = 0 | ||
| 2711 | // .. ==> 0XF8000784[0:0] = 0x00000000U | ||
| 2712 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2713 | // .. L0_SEL = 0 | ||
| 2714 | // .. ==> 0XF8000784[1:1] = 0x00000000U | ||
| 2715 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 2716 | // .. L1_SEL = 1 | ||
| 2717 | // .. ==> 0XF8000784[2:2] = 0x00000001U | ||
| 2718 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 2719 | // .. L2_SEL = 0 | ||
| 2720 | // .. ==> 0XF8000784[4:3] = 0x00000000U | ||
| 2721 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2722 | // .. L3_SEL = 0 | ||
| 2723 | // .. ==> 0XF8000784[7:5] = 0x00000000U | ||
| 2724 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2725 | // .. Speed = 1 | ||
| 2726 | // .. ==> 0XF8000784[8:8] = 0x00000001U | ||
| 2727 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2728 | // .. IO_Type = 1 | ||
| 2729 | // .. ==> 0XF8000784[11:9] = 0x00000001U | ||
| 2730 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 2731 | // .. PULLUP = 0 | ||
| 2732 | // .. ==> 0XF8000784[12:12] = 0x00000000U | ||
| 2733 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2734 | // .. DisableRcvr = 0 | ||
| 2735 | // .. ==> 0XF8000784[13:13] = 0x00000000U | ||
| 2736 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2737 | // .. | ||
| 2738 | EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U), | ||
| 2739 | // .. TRI_ENABLE = 0 | ||
| 2740 | // .. ==> 0XF8000788[0:0] = 0x00000000U | ||
| 2741 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2742 | // .. L0_SEL = 0 | ||
| 2743 | // .. ==> 0XF8000788[1:1] = 0x00000000U | ||
| 2744 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 2745 | // .. L1_SEL = 1 | ||
| 2746 | // .. ==> 0XF8000788[2:2] = 0x00000001U | ||
| 2747 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 2748 | // .. L2_SEL = 0 | ||
| 2749 | // .. ==> 0XF8000788[4:3] = 0x00000000U | ||
| 2750 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2751 | // .. L3_SEL = 0 | ||
| 2752 | // .. ==> 0XF8000788[7:5] = 0x00000000U | ||
| 2753 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2754 | // .. Speed = 1 | ||
| 2755 | // .. ==> 0XF8000788[8:8] = 0x00000001U | ||
| 2756 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2757 | // .. IO_Type = 1 | ||
| 2758 | // .. ==> 0XF8000788[11:9] = 0x00000001U | ||
| 2759 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 2760 | // .. PULLUP = 0 | ||
| 2761 | // .. ==> 0XF8000788[12:12] = 0x00000000U | ||
| 2762 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2763 | // .. DisableRcvr = 0 | ||
| 2764 | // .. ==> 0XF8000788[13:13] = 0x00000000U | ||
| 2765 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2766 | // .. | ||
| 2767 | EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U), | ||
| 2768 | // .. TRI_ENABLE = 0 | ||
| 2769 | // .. ==> 0XF800078C[0:0] = 0x00000000U | ||
| 2770 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2771 | // .. L0_SEL = 0 | ||
| 2772 | // .. ==> 0XF800078C[1:1] = 0x00000000U | ||
| 2773 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 2774 | // .. L1_SEL = 1 | ||
| 2775 | // .. ==> 0XF800078C[2:2] = 0x00000001U | ||
| 2776 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 2777 | // .. L2_SEL = 0 | ||
| 2778 | // .. ==> 0XF800078C[4:3] = 0x00000000U | ||
| 2779 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2780 | // .. L3_SEL = 0 | ||
| 2781 | // .. ==> 0XF800078C[7:5] = 0x00000000U | ||
| 2782 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2783 | // .. Speed = 1 | ||
| 2784 | // .. ==> 0XF800078C[8:8] = 0x00000001U | ||
| 2785 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2786 | // .. IO_Type = 1 | ||
| 2787 | // .. ==> 0XF800078C[11:9] = 0x00000001U | ||
| 2788 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 2789 | // .. PULLUP = 0 | ||
| 2790 | // .. ==> 0XF800078C[12:12] = 0x00000000U | ||
| 2791 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2792 | // .. DisableRcvr = 0 | ||
| 2793 | // .. ==> 0XF800078C[13:13] = 0x00000000U | ||
| 2794 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2795 | // .. | ||
| 2796 | EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U), | ||
| 2797 | // .. TRI_ENABLE = 1 | ||
| 2798 | // .. ==> 0XF8000790[0:0] = 0x00000001U | ||
| 2799 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 2800 | // .. L0_SEL = 0 | ||
| 2801 | // .. ==> 0XF8000790[1:1] = 0x00000000U | ||
| 2802 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 2803 | // .. L1_SEL = 1 | ||
| 2804 | // .. ==> 0XF8000790[2:2] = 0x00000001U | ||
| 2805 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 2806 | // .. L2_SEL = 0 | ||
| 2807 | // .. ==> 0XF8000790[4:3] = 0x00000000U | ||
| 2808 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2809 | // .. L3_SEL = 0 | ||
| 2810 | // .. ==> 0XF8000790[7:5] = 0x00000000U | ||
| 2811 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2812 | // .. Speed = 1 | ||
| 2813 | // .. ==> 0XF8000790[8:8] = 0x00000001U | ||
| 2814 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2815 | // .. IO_Type = 1 | ||
| 2816 | // .. ==> 0XF8000790[11:9] = 0x00000001U | ||
| 2817 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 2818 | // .. PULLUP = 0 | ||
| 2819 | // .. ==> 0XF8000790[12:12] = 0x00000000U | ||
| 2820 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2821 | // .. DisableRcvr = 0 | ||
| 2822 | // .. ==> 0XF8000790[13:13] = 0x00000000U | ||
| 2823 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2824 | // .. | ||
| 2825 | EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U), | ||
| 2826 | // .. TRI_ENABLE = 0 | ||
| 2827 | // .. ==> 0XF8000794[0:0] = 0x00000000U | ||
| 2828 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2829 | // .. L0_SEL = 0 | ||
| 2830 | // .. ==> 0XF8000794[1:1] = 0x00000000U | ||
| 2831 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 2832 | // .. L1_SEL = 1 | ||
| 2833 | // .. ==> 0XF8000794[2:2] = 0x00000001U | ||
| 2834 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 2835 | // .. L2_SEL = 0 | ||
| 2836 | // .. ==> 0XF8000794[4:3] = 0x00000000U | ||
| 2837 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2838 | // .. L3_SEL = 0 | ||
| 2839 | // .. ==> 0XF8000794[7:5] = 0x00000000U | ||
| 2840 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2841 | // .. Speed = 1 | ||
| 2842 | // .. ==> 0XF8000794[8:8] = 0x00000001U | ||
| 2843 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2844 | // .. IO_Type = 1 | ||
| 2845 | // .. ==> 0XF8000794[11:9] = 0x00000001U | ||
| 2846 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 2847 | // .. PULLUP = 0 | ||
| 2848 | // .. ==> 0XF8000794[12:12] = 0x00000000U | ||
| 2849 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2850 | // .. DisableRcvr = 0 | ||
| 2851 | // .. ==> 0XF8000794[13:13] = 0x00000000U | ||
| 2852 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2853 | // .. | ||
| 2854 | EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U), | ||
| 2855 | // .. TRI_ENABLE = 0 | ||
| 2856 | // .. ==> 0XF8000798[0:0] = 0x00000000U | ||
| 2857 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2858 | // .. L0_SEL = 0 | ||
| 2859 | // .. ==> 0XF8000798[1:1] = 0x00000000U | ||
| 2860 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 2861 | // .. L1_SEL = 1 | ||
| 2862 | // .. ==> 0XF8000798[2:2] = 0x00000001U | ||
| 2863 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 2864 | // .. L2_SEL = 0 | ||
| 2865 | // .. ==> 0XF8000798[4:3] = 0x00000000U | ||
| 2866 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2867 | // .. L3_SEL = 0 | ||
| 2868 | // .. ==> 0XF8000798[7:5] = 0x00000000U | ||
| 2869 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2870 | // .. Speed = 1 | ||
| 2871 | // .. ==> 0XF8000798[8:8] = 0x00000001U | ||
| 2872 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2873 | // .. IO_Type = 1 | ||
| 2874 | // .. ==> 0XF8000798[11:9] = 0x00000001U | ||
| 2875 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 2876 | // .. PULLUP = 0 | ||
| 2877 | // .. ==> 0XF8000798[12:12] = 0x00000000U | ||
| 2878 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2879 | // .. DisableRcvr = 0 | ||
| 2880 | // .. ==> 0XF8000798[13:13] = 0x00000000U | ||
| 2881 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2882 | // .. | ||
| 2883 | EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U), | ||
| 2884 | // .. TRI_ENABLE = 0 | ||
| 2885 | // .. ==> 0XF800079C[0:0] = 0x00000000U | ||
| 2886 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2887 | // .. L0_SEL = 0 | ||
| 2888 | // .. ==> 0XF800079C[1:1] = 0x00000000U | ||
| 2889 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 2890 | // .. L1_SEL = 1 | ||
| 2891 | // .. ==> 0XF800079C[2:2] = 0x00000001U | ||
| 2892 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 2893 | // .. L2_SEL = 0 | ||
| 2894 | // .. ==> 0XF800079C[4:3] = 0x00000000U | ||
| 2895 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2896 | // .. L3_SEL = 0 | ||
| 2897 | // .. ==> 0XF800079C[7:5] = 0x00000000U | ||
| 2898 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 2899 | // .. Speed = 1 | ||
| 2900 | // .. ==> 0XF800079C[8:8] = 0x00000001U | ||
| 2901 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2902 | // .. IO_Type = 1 | ||
| 2903 | // .. ==> 0XF800079C[11:9] = 0x00000001U | ||
| 2904 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 2905 | // .. PULLUP = 0 | ||
| 2906 | // .. ==> 0XF800079C[12:12] = 0x00000000U | ||
| 2907 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2908 | // .. DisableRcvr = 0 | ||
| 2909 | // .. ==> 0XF800079C[13:13] = 0x00000000U | ||
| 2910 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2911 | // .. | ||
| 2912 | EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U), | ||
| 2913 | // .. TRI_ENABLE = 0 | ||
| 2914 | // .. ==> 0XF80007A0[0:0] = 0x00000000U | ||
| 2915 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2916 | // .. L0_SEL = 0 | ||
| 2917 | // .. ==> 0XF80007A0[1:1] = 0x00000000U | ||
| 2918 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 2919 | // .. L1_SEL = 0 | ||
| 2920 | // .. ==> 0XF80007A0[2:2] = 0x00000000U | ||
| 2921 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2922 | // .. L2_SEL = 0 | ||
| 2923 | // .. ==> 0XF80007A0[4:3] = 0x00000000U | ||
| 2924 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2925 | // .. L3_SEL = 4 | ||
| 2926 | // .. ==> 0XF80007A0[7:5] = 0x00000004U | ||
| 2927 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 2928 | // .. Speed = 1 | ||
| 2929 | // .. ==> 0XF80007A0[8:8] = 0x00000001U | ||
| 2930 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2931 | // .. IO_Type = 1 | ||
| 2932 | // .. ==> 0XF80007A0[11:9] = 0x00000001U | ||
| 2933 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 2934 | // .. PULLUP = 0 | ||
| 2935 | // .. ==> 0XF80007A0[12:12] = 0x00000000U | ||
| 2936 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2937 | // .. DisableRcvr = 0 | ||
| 2938 | // .. ==> 0XF80007A0[13:13] = 0x00000000U | ||
| 2939 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2940 | // .. | ||
| 2941 | EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U), | ||
| 2942 | // .. TRI_ENABLE = 0 | ||
| 2943 | // .. ==> 0XF80007A4[0:0] = 0x00000000U | ||
| 2944 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2945 | // .. L0_SEL = 0 | ||
| 2946 | // .. ==> 0XF80007A4[1:1] = 0x00000000U | ||
| 2947 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 2948 | // .. L1_SEL = 0 | ||
| 2949 | // .. ==> 0XF80007A4[2:2] = 0x00000000U | ||
| 2950 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2951 | // .. L2_SEL = 0 | ||
| 2952 | // .. ==> 0XF80007A4[4:3] = 0x00000000U | ||
| 2953 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2954 | // .. L3_SEL = 4 | ||
| 2955 | // .. ==> 0XF80007A4[7:5] = 0x00000004U | ||
| 2956 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 2957 | // .. Speed = 1 | ||
| 2958 | // .. ==> 0XF80007A4[8:8] = 0x00000001U | ||
| 2959 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2960 | // .. IO_Type = 1 | ||
| 2961 | // .. ==> 0XF80007A4[11:9] = 0x00000001U | ||
| 2962 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 2963 | // .. PULLUP = 0 | ||
| 2964 | // .. ==> 0XF80007A4[12:12] = 0x00000000U | ||
| 2965 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2966 | // .. DisableRcvr = 0 | ||
| 2967 | // .. ==> 0XF80007A4[13:13] = 0x00000000U | ||
| 2968 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2969 | // .. | ||
| 2970 | EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U), | ||
| 2971 | // .. TRI_ENABLE = 0 | ||
| 2972 | // .. ==> 0XF80007A8[0:0] = 0x00000000U | ||
| 2973 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 2974 | // .. L0_SEL = 0 | ||
| 2975 | // .. ==> 0XF80007A8[1:1] = 0x00000000U | ||
| 2976 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 2977 | // .. L1_SEL = 0 | ||
| 2978 | // .. ==> 0XF80007A8[2:2] = 0x00000000U | ||
| 2979 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 2980 | // .. L2_SEL = 0 | ||
| 2981 | // .. ==> 0XF80007A8[4:3] = 0x00000000U | ||
| 2982 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 2983 | // .. L3_SEL = 4 | ||
| 2984 | // .. ==> 0XF80007A8[7:5] = 0x00000004U | ||
| 2985 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 2986 | // .. Speed = 1 | ||
| 2987 | // .. ==> 0XF80007A8[8:8] = 0x00000001U | ||
| 2988 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 2989 | // .. IO_Type = 1 | ||
| 2990 | // .. ==> 0XF80007A8[11:9] = 0x00000001U | ||
| 2991 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 2992 | // .. PULLUP = 0 | ||
| 2993 | // .. ==> 0XF80007A8[12:12] = 0x00000000U | ||
| 2994 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 2995 | // .. DisableRcvr = 0 | ||
| 2996 | // .. ==> 0XF80007A8[13:13] = 0x00000000U | ||
| 2997 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 2998 | // .. | ||
| 2999 | EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U), | ||
| 3000 | // .. TRI_ENABLE = 0 | ||
| 3001 | // .. ==> 0XF80007AC[0:0] = 0x00000000U | ||
| 3002 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 3003 | // .. L0_SEL = 0 | ||
| 3004 | // .. ==> 0XF80007AC[1:1] = 0x00000000U | ||
| 3005 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 3006 | // .. L1_SEL = 0 | ||
| 3007 | // .. ==> 0XF80007AC[2:2] = 0x00000000U | ||
| 3008 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 3009 | // .. L2_SEL = 0 | ||
| 3010 | // .. ==> 0XF80007AC[4:3] = 0x00000000U | ||
| 3011 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 3012 | // .. L3_SEL = 4 | ||
| 3013 | // .. ==> 0XF80007AC[7:5] = 0x00000004U | ||
| 3014 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 3015 | // .. Speed = 1 | ||
| 3016 | // .. ==> 0XF80007AC[8:8] = 0x00000001U | ||
| 3017 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 3018 | // .. IO_Type = 1 | ||
| 3019 | // .. ==> 0XF80007AC[11:9] = 0x00000001U | ||
| 3020 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 3021 | // .. PULLUP = 0 | ||
| 3022 | // .. ==> 0XF80007AC[12:12] = 0x00000000U | ||
| 3023 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 3024 | // .. DisableRcvr = 0 | ||
| 3025 | // .. ==> 0XF80007AC[13:13] = 0x00000000U | ||
| 3026 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 3027 | // .. | ||
| 3028 | EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U), | ||
| 3029 | // .. TRI_ENABLE = 0 | ||
| 3030 | // .. ==> 0XF80007B0[0:0] = 0x00000000U | ||
| 3031 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 3032 | // .. L0_SEL = 0 | ||
| 3033 | // .. ==> 0XF80007B0[1:1] = 0x00000000U | ||
| 3034 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 3035 | // .. L1_SEL = 0 | ||
| 3036 | // .. ==> 0XF80007B0[2:2] = 0x00000000U | ||
| 3037 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 3038 | // .. L2_SEL = 0 | ||
| 3039 | // .. ==> 0XF80007B0[4:3] = 0x00000000U | ||
| 3040 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 3041 | // .. L3_SEL = 4 | ||
| 3042 | // .. ==> 0XF80007B0[7:5] = 0x00000004U | ||
| 3043 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 3044 | // .. Speed = 1 | ||
| 3045 | // .. ==> 0XF80007B0[8:8] = 0x00000001U | ||
| 3046 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 3047 | // .. IO_Type = 1 | ||
| 3048 | // .. ==> 0XF80007B0[11:9] = 0x00000001U | ||
| 3049 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 3050 | // .. PULLUP = 0 | ||
| 3051 | // .. ==> 0XF80007B0[12:12] = 0x00000000U | ||
| 3052 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 3053 | // .. DisableRcvr = 0 | ||
| 3054 | // .. ==> 0XF80007B0[13:13] = 0x00000000U | ||
| 3055 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 3056 | // .. | ||
| 3057 | EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U), | ||
| 3058 | // .. TRI_ENABLE = 0 | ||
| 3059 | // .. ==> 0XF80007B4[0:0] = 0x00000000U | ||
| 3060 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 3061 | // .. L0_SEL = 0 | ||
| 3062 | // .. ==> 0XF80007B4[1:1] = 0x00000000U | ||
| 3063 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 3064 | // .. L1_SEL = 0 | ||
| 3065 | // .. ==> 0XF80007B4[2:2] = 0x00000000U | ||
| 3066 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 3067 | // .. L2_SEL = 0 | ||
| 3068 | // .. ==> 0XF80007B4[4:3] = 0x00000000U | ||
| 3069 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 3070 | // .. L3_SEL = 4 | ||
| 3071 | // .. ==> 0XF80007B4[7:5] = 0x00000004U | ||
| 3072 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 3073 | // .. Speed = 1 | ||
| 3074 | // .. ==> 0XF80007B4[8:8] = 0x00000001U | ||
| 3075 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 3076 | // .. IO_Type = 1 | ||
| 3077 | // .. ==> 0XF80007B4[11:9] = 0x00000001U | ||
| 3078 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 3079 | // .. PULLUP = 0 | ||
| 3080 | // .. ==> 0XF80007B4[12:12] = 0x00000000U | ||
| 3081 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 3082 | // .. DisableRcvr = 0 | ||
| 3083 | // .. ==> 0XF80007B4[13:13] = 0x00000000U | ||
| 3084 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 3085 | // .. | ||
| 3086 | EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U), | ||
| 3087 | // .. TRI_ENABLE = 1 | ||
| 3088 | // .. ==> 0XF80007BC[0:0] = 0x00000001U | ||
| 3089 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 3090 | // .. Speed = 0 | ||
| 3091 | // .. ==> 0XF80007BC[8:8] = 0x00000000U | ||
| 3092 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 3093 | // .. IO_Type = 1 | ||
| 3094 | // .. ==> 0XF80007BC[11:9] = 0x00000001U | ||
| 3095 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 3096 | // .. PULLUP = 0 | ||
| 3097 | // .. ==> 0XF80007BC[12:12] = 0x00000000U | ||
| 3098 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 3099 | // .. DisableRcvr = 0 | ||
| 3100 | // .. ==> 0XF80007BC[13:13] = 0x00000000U | ||
| 3101 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 3102 | // .. | ||
| 3103 | EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U), | ||
| 3104 | // .. TRI_ENABLE = 0 | ||
| 3105 | // .. ==> 0XF80007C0[0:0] = 0x00000000U | ||
| 3106 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 3107 | // .. L0_SEL = 0 | ||
| 3108 | // .. ==> 0XF80007C0[1:1] = 0x00000000U | ||
| 3109 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 3110 | // .. L1_SEL = 0 | ||
| 3111 | // .. ==> 0XF80007C0[2:2] = 0x00000000U | ||
| 3112 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 3113 | // .. L2_SEL = 0 | ||
| 3114 | // .. ==> 0XF80007C0[4:3] = 0x00000000U | ||
| 3115 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 3116 | // .. L3_SEL = 7 | ||
| 3117 | // .. ==> 0XF80007C0[7:5] = 0x00000007U | ||
| 3118 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | ||
| 3119 | // .. Speed = 0 | ||
| 3120 | // .. ==> 0XF80007C0[8:8] = 0x00000000U | ||
| 3121 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 3122 | // .. IO_Type = 1 | ||
| 3123 | // .. ==> 0XF80007C0[11:9] = 0x00000001U | ||
| 3124 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 3125 | // .. PULLUP = 0 | ||
| 3126 | // .. ==> 0XF80007C0[12:12] = 0x00000000U | ||
| 3127 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 3128 | // .. DisableRcvr = 0 | ||
| 3129 | // .. ==> 0XF80007C0[13:13] = 0x00000000U | ||
| 3130 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 3131 | // .. | ||
| 3132 | EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), | ||
| 3133 | // .. TRI_ENABLE = 1 | ||
| 3134 | // .. ==> 0XF80007C4[0:0] = 0x00000001U | ||
| 3135 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 3136 | // .. L0_SEL = 0 | ||
| 3137 | // .. ==> 0XF80007C4[1:1] = 0x00000000U | ||
| 3138 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 3139 | // .. L1_SEL = 0 | ||
| 3140 | // .. ==> 0XF80007C4[2:2] = 0x00000000U | ||
| 3141 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 3142 | // .. L2_SEL = 0 | ||
| 3143 | // .. ==> 0XF80007C4[4:3] = 0x00000000U | ||
| 3144 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 3145 | // .. L3_SEL = 7 | ||
| 3146 | // .. ==> 0XF80007C4[7:5] = 0x00000007U | ||
| 3147 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | ||
| 3148 | // .. Speed = 0 | ||
| 3149 | // .. ==> 0XF80007C4[8:8] = 0x00000000U | ||
| 3150 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 3151 | // .. IO_Type = 1 | ||
| 3152 | // .. ==> 0XF80007C4[11:9] = 0x00000001U | ||
| 3153 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 3154 | // .. PULLUP = 0 | ||
| 3155 | // .. ==> 0XF80007C4[12:12] = 0x00000000U | ||
| 3156 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 3157 | // .. DisableRcvr = 0 | ||
| 3158 | // .. ==> 0XF80007C4[13:13] = 0x00000000U | ||
| 3159 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 3160 | // .. | ||
| 3161 | EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), | ||
| 3162 | // .. TRI_ENABLE = 0 | ||
| 3163 | // .. ==> 0XF80007D0[0:0] = 0x00000000U | ||
| 3164 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 3165 | // .. L0_SEL = 0 | ||
| 3166 | // .. ==> 0XF80007D0[1:1] = 0x00000000U | ||
| 3167 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 3168 | // .. L1_SEL = 0 | ||
| 3169 | // .. ==> 0XF80007D0[2:2] = 0x00000000U | ||
| 3170 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 3171 | // .. L2_SEL = 0 | ||
| 3172 | // .. ==> 0XF80007D0[4:3] = 0x00000000U | ||
| 3173 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 3174 | // .. L3_SEL = 4 | ||
| 3175 | // .. ==> 0XF80007D0[7:5] = 0x00000004U | ||
| 3176 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 3177 | // .. Speed = 0 | ||
| 3178 | // .. ==> 0XF80007D0[8:8] = 0x00000000U | ||
| 3179 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 3180 | // .. IO_Type = 1 | ||
| 3181 | // .. ==> 0XF80007D0[11:9] = 0x00000001U | ||
| 3182 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 3183 | // .. PULLUP = 0 | ||
| 3184 | // .. ==> 0XF80007D0[12:12] = 0x00000000U | ||
| 3185 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 3186 | // .. DisableRcvr = 0 | ||
| 3187 | // .. ==> 0XF80007D0[13:13] = 0x00000000U | ||
| 3188 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 3189 | // .. | ||
| 3190 | EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), | ||
| 3191 | // .. TRI_ENABLE = 0 | ||
| 3192 | // .. ==> 0XF80007D4[0:0] = 0x00000000U | ||
| 3193 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 3194 | // .. L0_SEL = 0 | ||
| 3195 | // .. ==> 0XF80007D4[1:1] = 0x00000000U | ||
| 3196 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 3197 | // .. L1_SEL = 0 | ||
| 3198 | // .. ==> 0XF80007D4[2:2] = 0x00000000U | ||
| 3199 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 3200 | // .. L2_SEL = 0 | ||
| 3201 | // .. ==> 0XF80007D4[4:3] = 0x00000000U | ||
| 3202 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 3203 | // .. L3_SEL = 4 | ||
| 3204 | // .. ==> 0XF80007D4[7:5] = 0x00000004U | ||
| 3205 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 3206 | // .. Speed = 0 | ||
| 3207 | // .. ==> 0XF80007D4[8:8] = 0x00000000U | ||
| 3208 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 3209 | // .. IO_Type = 1 | ||
| 3210 | // .. ==> 0XF80007D4[11:9] = 0x00000001U | ||
| 3211 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 3212 | // .. PULLUP = 0 | ||
| 3213 | // .. ==> 0XF80007D4[12:12] = 0x00000000U | ||
| 3214 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 3215 | // .. DisableRcvr = 0 | ||
| 3216 | // .. ==> 0XF80007D4[13:13] = 0x00000000U | ||
| 3217 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 3218 | // .. | ||
| 3219 | EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), | ||
| 3220 | // .. SDIO0_WP_SEL = 55 | ||
| 3221 | // .. ==> 0XF8000830[5:0] = 0x00000037U | ||
| 3222 | // .. ==> MASK : 0x0000003FU VAL : 0x00000037U | ||
| 3223 | // .. SDIO0_CD_SEL = 47 | ||
| 3224 | // .. ==> 0XF8000830[21:16] = 0x0000002FU | ||
| 3225 | // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U | ||
| 3226 | // .. | ||
| 3227 | EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U), | ||
| 3228 | // .. FINISH: MIO PROGRAMMING | ||
| 3229 | // .. START: LOCK IT BACK | ||
| 3230 | // .. LOCK_KEY = 0X767B | ||
| 3231 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
| 3232 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
| 3233 | // .. | ||
| 3234 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
| 3235 | // .. FINISH: LOCK IT BACK | ||
| 3236 | // FINISH: top | ||
| 3237 | // | ||
| 3238 | EMIT_EXIT(), | ||
| 3239 | |||
| 3240 | // | ||
| 3241 | }; | ||
| 3242 | |||
| 3243 | unsigned long ps7_peripherals_init_data_3_0[] = { | ||
| 3244 | // START: top | ||
| 3245 | // .. START: SLCR SETTINGS | ||
| 3246 | // .. UNLOCK_KEY = 0XDF0D | ||
| 3247 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
| 3248 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
| 3249 | // .. | ||
| 3250 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
| 3251 | // .. FINISH: SLCR SETTINGS | ||
| 3252 | // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS | ||
| 3253 | // .. IBUF_DISABLE_MODE = 0x1 | ||
| 3254 | // .. ==> 0XF8000B48[7:7] = 0x00000001U | ||
| 3255 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
| 3256 | // .. TERM_DISABLE_MODE = 0x1 | ||
| 3257 | // .. ==> 0XF8000B48[8:8] = 0x00000001U | ||
| 3258 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 3259 | // .. | ||
| 3260 | EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), | ||
| 3261 | // .. IBUF_DISABLE_MODE = 0x1 | ||
| 3262 | // .. ==> 0XF8000B4C[7:7] = 0x00000001U | ||
| 3263 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
| 3264 | // .. TERM_DISABLE_MODE = 0x1 | ||
| 3265 | // .. ==> 0XF8000B4C[8:8] = 0x00000001U | ||
| 3266 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 3267 | // .. | ||
| 3268 | EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), | ||
| 3269 | // .. IBUF_DISABLE_MODE = 0x1 | ||
| 3270 | // .. ==> 0XF8000B50[7:7] = 0x00000001U | ||
| 3271 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
| 3272 | // .. TERM_DISABLE_MODE = 0x1 | ||
| 3273 | // .. ==> 0XF8000B50[8:8] = 0x00000001U | ||
| 3274 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 3275 | // .. | ||
| 3276 | EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), | ||
| 3277 | // .. IBUF_DISABLE_MODE = 0x1 | ||
| 3278 | // .. ==> 0XF8000B54[7:7] = 0x00000001U | ||
| 3279 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
| 3280 | // .. TERM_DISABLE_MODE = 0x1 | ||
| 3281 | // .. ==> 0XF8000B54[8:8] = 0x00000001U | ||
| 3282 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 3283 | // .. | ||
| 3284 | EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), | ||
| 3285 | // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS | ||
| 3286 | // .. START: LOCK IT BACK | ||
| 3287 | // .. LOCK_KEY = 0X767B | ||
| 3288 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
| 3289 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
| 3290 | // .. | ||
| 3291 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
| 3292 | // .. FINISH: LOCK IT BACK | ||
| 3293 | // .. START: SRAM/NOR SET OPMODE | ||
| 3294 | // .. FINISH: SRAM/NOR SET OPMODE | ||
| 3295 | // .. START: UART REGISTERS | ||
| 3296 | // .. BDIV = 0x6 | ||
| 3297 | // .. ==> 0XE0001034[7:0] = 0x00000006U | ||
| 3298 | // .. ==> MASK : 0x000000FFU VAL : 0x00000006U | ||
| 3299 | // .. | ||
| 3300 | EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), | ||
| 3301 | // .. CD = 0x3e | ||
| 3302 | // .. ==> 0XE0001018[15:0] = 0x0000003EU | ||
| 3303 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU | ||
| 3304 | // .. | ||
| 3305 | EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), | ||
| 3306 | // .. STPBRK = 0x0 | ||
| 3307 | // .. ==> 0XE0001000[8:8] = 0x00000000U | ||
| 3308 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 3309 | // .. STTBRK = 0x0 | ||
| 3310 | // .. ==> 0XE0001000[7:7] = 0x00000000U | ||
| 3311 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 3312 | // .. RSTTO = 0x0 | ||
| 3313 | // .. ==> 0XE0001000[6:6] = 0x00000000U | ||
| 3314 | // .. ==> MASK : 0x00000040U VAL : 0x00000000U | ||
| 3315 | // .. TXDIS = 0x0 | ||
| 3316 | // .. ==> 0XE0001000[5:5] = 0x00000000U | ||
| 3317 | // .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
| 3318 | // .. TXEN = 0x1 | ||
| 3319 | // .. ==> 0XE0001000[4:4] = 0x00000001U | ||
| 3320 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 3321 | // .. RXDIS = 0x0 | ||
| 3322 | // .. ==> 0XE0001000[3:3] = 0x00000000U | ||
| 3323 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 3324 | // .. RXEN = 0x1 | ||
| 3325 | // .. ==> 0XE0001000[2:2] = 0x00000001U | ||
| 3326 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 3327 | // .. TXRES = 0x1 | ||
| 3328 | // .. ==> 0XE0001000[1:1] = 0x00000001U | ||
| 3329 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 3330 | // .. RXRES = 0x1 | ||
| 3331 | // .. ==> 0XE0001000[0:0] = 0x00000001U | ||
| 3332 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 3333 | // .. | ||
| 3334 | EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), | ||
| 3335 | // .. CHMODE = 0x0 | ||
| 3336 | // .. ==> 0XE0001004[9:8] = 0x00000000U | ||
| 3337 | // .. ==> MASK : 0x00000300U VAL : 0x00000000U | ||
| 3338 | // .. NBSTOP = 0x0 | ||
| 3339 | // .. ==> 0XE0001004[7:6] = 0x00000000U | ||
| 3340 | // .. ==> MASK : 0x000000C0U VAL : 0x00000000U | ||
| 3341 | // .. PAR = 0x4 | ||
| 3342 | // .. ==> 0XE0001004[5:3] = 0x00000004U | ||
| 3343 | // .. ==> MASK : 0x00000038U VAL : 0x00000020U | ||
| 3344 | // .. CHRL = 0x0 | ||
| 3345 | // .. ==> 0XE0001004[2:1] = 0x00000000U | ||
| 3346 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
| 3347 | // .. CLKS = 0x0 | ||
| 3348 | // .. ==> 0XE0001004[0:0] = 0x00000000U | ||
| 3349 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 3350 | // .. | ||
| 3351 | EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), | ||
| 3352 | // .. FINISH: UART REGISTERS | ||
| 3353 | // .. START: TPIU WIDTH IN CASE OF EMIO | ||
| 3354 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
| 3355 | // .. .. a = 0XC5ACCE55 | ||
| 3356 | // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U | ||
| 3357 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
| 3358 | // .. .. | ||
| 3359 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
| 3360 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
| 3361 | // .. .. START: TRACE CURRENT PORT SIZE | ||
| 3362 | // .. .. a = 2 | ||
| 3363 | // .. .. ==> 0XF8803004[31:0] = 0x00000002U | ||
| 3364 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U | ||
| 3365 | // .. .. | ||
| 3366 | EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), | ||
| 3367 | // .. .. FINISH: TRACE CURRENT PORT SIZE | ||
| 3368 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
| 3369 | // .. .. a = 0X0 | ||
| 3370 | // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U | ||
| 3371 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
| 3372 | // .. .. | ||
| 3373 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), | ||
| 3374 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
| 3375 | // .. FINISH: TPIU WIDTH IN CASE OF EMIO | ||
| 3376 | // .. START: QSPI REGISTERS | ||
| 3377 | // .. Holdb_dr = 1 | ||
| 3378 | // .. ==> 0XE000D000[19:19] = 0x00000001U | ||
| 3379 | // .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
| 3380 | // .. | ||
| 3381 | EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), | ||
| 3382 | // .. FINISH: QSPI REGISTERS | ||
| 3383 | // .. START: PL POWER ON RESET REGISTERS | ||
| 3384 | // .. PCFG_POR_CNT_4K = 0 | ||
| 3385 | // .. ==> 0XF8007000[29:29] = 0x00000000U | ||
| 3386 | // .. ==> MASK : 0x20000000U VAL : 0x00000000U | ||
| 3387 | // .. | ||
| 3388 | EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), | ||
| 3389 | // .. FINISH: PL POWER ON RESET REGISTERS | ||
| 3390 | // .. START: SMC TIMING CALCULATION REGISTER UPDATE | ||
| 3391 | // .. .. START: NAND SET CYCLE | ||
| 3392 | // .. .. FINISH: NAND SET CYCLE | ||
| 3393 | // .. .. START: OPMODE | ||
| 3394 | // .. .. FINISH: OPMODE | ||
| 3395 | // .. .. START: DIRECT COMMAND | ||
| 3396 | // .. .. FINISH: DIRECT COMMAND | ||
| 3397 | // .. .. START: SRAM/NOR CS0 SET CYCLE | ||
| 3398 | // .. .. FINISH: SRAM/NOR CS0 SET CYCLE | ||
| 3399 | // .. .. START: DIRECT COMMAND | ||
| 3400 | // .. .. FINISH: DIRECT COMMAND | ||
| 3401 | // .. .. START: NOR CS0 BASE ADDRESS | ||
| 3402 | // .. .. FINISH: NOR CS0 BASE ADDRESS | ||
| 3403 | // .. .. START: SRAM/NOR CS1 SET CYCLE | ||
| 3404 | // .. .. FINISH: SRAM/NOR CS1 SET CYCLE | ||
| 3405 | // .. .. START: DIRECT COMMAND | ||
| 3406 | // .. .. FINISH: DIRECT COMMAND | ||
| 3407 | // .. .. START: NOR CS1 BASE ADDRESS | ||
| 3408 | // .. .. FINISH: NOR CS1 BASE ADDRESS | ||
| 3409 | // .. .. START: USB RESET | ||
| 3410 | // .. .. .. START: USB0 RESET | ||
| 3411 | // .. .. .. .. START: DIR MODE BANK 0 | ||
| 3412 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
| 3413 | // .. .. .. .. START: DIR MODE BANK 1 | ||
| 3414 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
| 3415 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3416 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3417 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3418 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3419 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3420 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3421 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3422 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3423 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
| 3424 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
| 3425 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
| 3426 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
| 3427 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 3428 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 3429 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 3430 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 3431 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 3432 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 3433 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 3434 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 3435 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 3436 | // .. .. .. .. | ||
| 3437 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 3438 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 3439 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3440 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3441 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3442 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3443 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3444 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3445 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3446 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3447 | // .. .. .. FINISH: USB0 RESET | ||
| 3448 | // .. .. .. START: USB1 RESET | ||
| 3449 | // .. .. .. .. START: DIR MODE BANK 0 | ||
| 3450 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
| 3451 | // .. .. .. .. START: DIR MODE BANK 1 | ||
| 3452 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
| 3453 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3454 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3455 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3456 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3457 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3458 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3459 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3460 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3461 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
| 3462 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
| 3463 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
| 3464 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
| 3465 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 3466 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 3467 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 3468 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 3469 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 3470 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 3471 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 3472 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 3473 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 3474 | // .. .. .. .. | ||
| 3475 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 3476 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 3477 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3478 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3479 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3480 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3481 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3482 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3483 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3484 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3485 | // .. .. .. FINISH: USB1 RESET | ||
| 3486 | // .. .. FINISH: USB RESET | ||
| 3487 | // .. .. START: ENET RESET | ||
| 3488 | // .. .. .. START: ENET0 RESET | ||
| 3489 | // .. .. .. .. START: DIR MODE BANK 0 | ||
| 3490 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
| 3491 | // .. .. .. .. START: DIR MODE BANK 1 | ||
| 3492 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
| 3493 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3494 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3495 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3496 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3497 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3498 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3499 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3500 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3501 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
| 3502 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
| 3503 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
| 3504 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
| 3505 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 3506 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 3507 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 3508 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 3509 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 3510 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 3511 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 3512 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 3513 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 3514 | // .. .. .. .. | ||
| 3515 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 3516 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 3517 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3518 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3519 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3520 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3521 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3522 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3523 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3524 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3525 | // .. .. .. FINISH: ENET0 RESET | ||
| 3526 | // .. .. .. START: ENET1 RESET | ||
| 3527 | // .. .. .. .. START: DIR MODE BANK 0 | ||
| 3528 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
| 3529 | // .. .. .. .. START: DIR MODE BANK 1 | ||
| 3530 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
| 3531 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3532 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3533 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3534 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3535 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3536 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3537 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3538 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3539 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
| 3540 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
| 3541 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
| 3542 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
| 3543 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 3544 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 3545 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 3546 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 3547 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 3548 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 3549 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 3550 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 3551 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 3552 | // .. .. .. .. | ||
| 3553 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 3554 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 3555 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3556 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3557 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3558 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3559 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3560 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3561 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3562 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3563 | // .. .. .. FINISH: ENET1 RESET | ||
| 3564 | // .. .. FINISH: ENET RESET | ||
| 3565 | // .. .. START: I2C RESET | ||
| 3566 | // .. .. .. START: I2C0 RESET | ||
| 3567 | // .. .. .. .. START: DIR MODE GPIO BANK0 | ||
| 3568 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | ||
| 3569 | // .. .. .. .. START: DIR MODE GPIO BANK1 | ||
| 3570 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | ||
| 3571 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3572 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3573 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3574 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3575 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3576 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3577 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3578 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3579 | // .. .. .. .. START: OUTPUT ENABLE | ||
| 3580 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
| 3581 | // .. .. .. .. START: OUTPUT ENABLE | ||
| 3582 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
| 3583 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 3584 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 3585 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 3586 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 3587 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 3588 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 3589 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 3590 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 3591 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 3592 | // .. .. .. .. | ||
| 3593 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 3594 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 3595 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3596 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3597 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3598 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3599 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3600 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3601 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3602 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3603 | // .. .. .. FINISH: I2C0 RESET | ||
| 3604 | // .. .. .. START: I2C1 RESET | ||
| 3605 | // .. .. .. .. START: DIR MODE GPIO BANK0 | ||
| 3606 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | ||
| 3607 | // .. .. .. .. START: DIR MODE GPIO BANK1 | ||
| 3608 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | ||
| 3609 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3610 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3611 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3612 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3613 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3614 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3615 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3616 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3617 | // .. .. .. .. START: OUTPUT ENABLE | ||
| 3618 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
| 3619 | // .. .. .. .. START: OUTPUT ENABLE | ||
| 3620 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
| 3621 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 3622 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 3623 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 3624 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 3625 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 3626 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 3627 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 3628 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 3629 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 3630 | // .. .. .. .. | ||
| 3631 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 3632 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 3633 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3634 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3635 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3636 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 3637 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3638 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 3639 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3640 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 3641 | // .. .. .. FINISH: I2C1 RESET | ||
| 3642 | // .. .. FINISH: I2C RESET | ||
| 3643 | // .. .. START: NOR CHIP SELECT | ||
| 3644 | // .. .. .. START: DIR MODE BANK 0 | ||
| 3645 | // .. .. .. FINISH: DIR MODE BANK 0 | ||
| 3646 | // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3647 | // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 3648 | // .. .. .. START: OUTPUT ENABLE BANK 0 | ||
| 3649 | // .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
| 3650 | // .. .. FINISH: NOR CHIP SELECT | ||
| 3651 | // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE | ||
| 3652 | // FINISH: top | ||
| 3653 | // | ||
| 3654 | EMIT_EXIT(), | ||
| 3655 | |||
| 3656 | // | ||
| 3657 | }; | ||
| 3658 | |||
| 3659 | unsigned long ps7_post_config_3_0[] = { | ||
| 3660 | // START: top | ||
| 3661 | // .. START: SLCR SETTINGS | ||
| 3662 | // .. UNLOCK_KEY = 0XDF0D | ||
| 3663 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
| 3664 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
| 3665 | // .. | ||
| 3666 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
| 3667 | // .. FINISH: SLCR SETTINGS | ||
| 3668 | // .. START: ENABLING LEVEL SHIFTER | ||
| 3669 | // .. USER_LVL_INP_EN_0 = 1 | ||
| 3670 | // .. ==> 0XF8000900[3:3] = 0x00000001U | ||
| 3671 | // .. ==> MASK : 0x00000008U VAL : 0x00000008U | ||
| 3672 | // .. USER_LVL_OUT_EN_0 = 1 | ||
| 3673 | // .. ==> 0XF8000900[2:2] = 0x00000001U | ||
| 3674 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 3675 | // .. USER_LVL_INP_EN_1 = 1 | ||
| 3676 | // .. ==> 0XF8000900[1:1] = 0x00000001U | ||
| 3677 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 3678 | // .. USER_LVL_OUT_EN_1 = 1 | ||
| 3679 | // .. ==> 0XF8000900[0:0] = 0x00000001U | ||
| 3680 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 3681 | // .. | ||
| 3682 | EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), | ||
| 3683 | // .. FINISH: ENABLING LEVEL SHIFTER | ||
| 3684 | // .. START: TPIU WIDTH IN CASE OF EMIO | ||
| 3685 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
| 3686 | // .. .. a = 0XC5ACCE55 | ||
| 3687 | // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U | ||
| 3688 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
| 3689 | // .. .. | ||
| 3690 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
| 3691 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
| 3692 | // .. .. START: TRACE CURRENT PORT SIZE | ||
| 3693 | // .. .. a = 2 | ||
| 3694 | // .. .. ==> 0XF8803004[31:0] = 0x00000002U | ||
| 3695 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U | ||
| 3696 | // .. .. | ||
| 3697 | EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), | ||
| 3698 | // .. .. FINISH: TRACE CURRENT PORT SIZE | ||
| 3699 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
| 3700 | // .. .. a = 0X0 | ||
| 3701 | // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U | ||
| 3702 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
| 3703 | // .. .. | ||
| 3704 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), | ||
| 3705 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
| 3706 | // .. FINISH: TPIU WIDTH IN CASE OF EMIO | ||
| 3707 | // .. START: FPGA RESETS TO 0 | ||
| 3708 | // .. reserved_3 = 0 | ||
| 3709 | // .. ==> 0XF8000240[31:25] = 0x00000000U | ||
| 3710 | // .. ==> MASK : 0xFE000000U VAL : 0x00000000U | ||
| 3711 | // .. reserved_FPGA_ACP_RST = 0 | ||
| 3712 | // .. ==> 0XF8000240[24:24] = 0x00000000U | ||
| 3713 | // .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
| 3714 | // .. reserved_FPGA_AXDS3_RST = 0 | ||
| 3715 | // .. ==> 0XF8000240[23:23] = 0x00000000U | ||
| 3716 | // .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
| 3717 | // .. reserved_FPGA_AXDS2_RST = 0 | ||
| 3718 | // .. ==> 0XF8000240[22:22] = 0x00000000U | ||
| 3719 | // .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
| 3720 | // .. reserved_FPGA_AXDS1_RST = 0 | ||
| 3721 | // .. ==> 0XF8000240[21:21] = 0x00000000U | ||
| 3722 | // .. ==> MASK : 0x00200000U VAL : 0x00000000U | ||
| 3723 | // .. reserved_FPGA_AXDS0_RST = 0 | ||
| 3724 | // .. ==> 0XF8000240[20:20] = 0x00000000U | ||
| 3725 | // .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
| 3726 | // .. reserved_2 = 0 | ||
| 3727 | // .. ==> 0XF8000240[19:18] = 0x00000000U | ||
| 3728 | // .. ==> MASK : 0x000C0000U VAL : 0x00000000U | ||
| 3729 | // .. reserved_FSSW1_FPGA_RST = 0 | ||
| 3730 | // .. ==> 0XF8000240[17:17] = 0x00000000U | ||
| 3731 | // .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 3732 | // .. reserved_FSSW0_FPGA_RST = 0 | ||
| 3733 | // .. ==> 0XF8000240[16:16] = 0x00000000U | ||
| 3734 | // .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 3735 | // .. reserved_1 = 0 | ||
| 3736 | // .. ==> 0XF8000240[15:14] = 0x00000000U | ||
| 3737 | // .. ==> MASK : 0x0000C000U VAL : 0x00000000U | ||
| 3738 | // .. reserved_FPGA_FMSW1_RST = 0 | ||
| 3739 | // .. ==> 0XF8000240[13:13] = 0x00000000U | ||
| 3740 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 3741 | // .. reserved_FPGA_FMSW0_RST = 0 | ||
| 3742 | // .. ==> 0XF8000240[12:12] = 0x00000000U | ||
| 3743 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 3744 | // .. reserved_FPGA_DMA3_RST = 0 | ||
| 3745 | // .. ==> 0XF8000240[11:11] = 0x00000000U | ||
| 3746 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 3747 | // .. reserved_FPGA_DMA2_RST = 0 | ||
| 3748 | // .. ==> 0XF8000240[10:10] = 0x00000000U | ||
| 3749 | // .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 3750 | // .. reserved_FPGA_DMA1_RST = 0 | ||
| 3751 | // .. ==> 0XF8000240[9:9] = 0x00000000U | ||
| 3752 | // .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
| 3753 | // .. reserved_FPGA_DMA0_RST = 0 | ||
| 3754 | // .. ==> 0XF8000240[8:8] = 0x00000000U | ||
| 3755 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 3756 | // .. reserved = 0 | ||
| 3757 | // .. ==> 0XF8000240[7:4] = 0x00000000U | ||
| 3758 | // .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
| 3759 | // .. FPGA3_OUT_RST = 0 | ||
| 3760 | // .. ==> 0XF8000240[3:3] = 0x00000000U | ||
| 3761 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 3762 | // .. FPGA2_OUT_RST = 0 | ||
| 3763 | // .. ==> 0XF8000240[2:2] = 0x00000000U | ||
| 3764 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 3765 | // .. FPGA1_OUT_RST = 0 | ||
| 3766 | // .. ==> 0XF8000240[1:1] = 0x00000000U | ||
| 3767 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 3768 | // .. FPGA0_OUT_RST = 0 | ||
| 3769 | // .. ==> 0XF8000240[0:0] = 0x00000000U | ||
| 3770 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 3771 | // .. | ||
| 3772 | EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), | ||
| 3773 | // .. FINISH: FPGA RESETS TO 0 | ||
| 3774 | // .. START: AFI REGISTERS | ||
| 3775 | // .. .. START: AFI0 REGISTERS | ||
| 3776 | // .. .. FINISH: AFI0 REGISTERS | ||
| 3777 | // .. .. START: AFI1 REGISTERS | ||
| 3778 | // .. .. FINISH: AFI1 REGISTERS | ||
| 3779 | // .. .. START: AFI2 REGISTERS | ||
| 3780 | // .. .. FINISH: AFI2 REGISTERS | ||
| 3781 | // .. .. START: AFI3 REGISTERS | ||
| 3782 | // .. .. FINISH: AFI3 REGISTERS | ||
| 3783 | // .. FINISH: AFI REGISTERS | ||
| 3784 | // .. START: LOCK IT BACK | ||
| 3785 | // .. LOCK_KEY = 0X767B | ||
| 3786 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
| 3787 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
| 3788 | // .. | ||
| 3789 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
| 3790 | // .. FINISH: LOCK IT BACK | ||
| 3791 | // FINISH: top | ||
| 3792 | // | ||
| 3793 | EMIT_EXIT(), | ||
| 3794 | |||
| 3795 | // | ||
| 3796 | }; | ||
| 3797 | |||
| 3798 | unsigned long ps7_debug_3_0[] = { | ||
| 3799 | // START: top | ||
| 3800 | // .. START: CROSS TRIGGER CONFIGURATIONS | ||
| 3801 | // .. .. START: UNLOCKING CTI REGISTERS | ||
| 3802 | // .. .. KEY = 0XC5ACCE55 | ||
| 3803 | // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U | ||
| 3804 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
| 3805 | // .. .. | ||
| 3806 | EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
| 3807 | // .. .. KEY = 0XC5ACCE55 | ||
| 3808 | // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U | ||
| 3809 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
| 3810 | // .. .. | ||
| 3811 | EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
| 3812 | // .. .. KEY = 0XC5ACCE55 | ||
| 3813 | // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U | ||
| 3814 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
| 3815 | // .. .. | ||
| 3816 | EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
| 3817 | // .. .. FINISH: UNLOCKING CTI REGISTERS | ||
| 3818 | // .. .. START: ENABLING CTI MODULES AND CHANNELS | ||
| 3819 | // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS | ||
| 3820 | // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS | ||
| 3821 | // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS | ||
| 3822 | // .. FINISH: CROSS TRIGGER CONFIGURATIONS | ||
| 3823 | // FINISH: top | ||
| 3824 | // | ||
| 3825 | EMIT_EXIT(), | ||
| 3826 | |||
| 3827 | // | ||
| 3828 | }; | ||
| 3829 | |||
| 3830 | unsigned long ps7_pll_init_data_2_0[] = { | ||
| 3831 | // START: top | ||
| 3832 | // .. START: SLCR SETTINGS | ||
| 3833 | // .. UNLOCK_KEY = 0XDF0D | ||
| 3834 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
| 3835 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
| 3836 | // .. | ||
| 3837 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
| 3838 | // .. FINISH: SLCR SETTINGS | ||
| 3839 | // .. START: PLL SLCR REGISTERS | ||
| 3840 | // .. .. START: ARM PLL INIT | ||
| 3841 | // .. .. PLL_RES = 0xc | ||
| 3842 | // .. .. ==> 0XF8000110[7:4] = 0x0000000CU | ||
| 3843 | // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U | ||
| 3844 | // .. .. PLL_CP = 0x2 | ||
| 3845 | // .. .. ==> 0XF8000110[11:8] = 0x00000002U | ||
| 3846 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
| 3847 | // .. .. LOCK_CNT = 0x177 | ||
| 3848 | // .. .. ==> 0XF8000110[21:12] = 0x00000177U | ||
| 3849 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U | ||
| 3850 | // .. .. | ||
| 3851 | EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U), | ||
| 3852 | // .. .. .. START: UPDATE FB_DIV | ||
| 3853 | // .. .. .. PLL_FDIV = 0x1a | ||
| 3854 | // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU | ||
| 3855 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U | ||
| 3856 | // .. .. .. | ||
| 3857 | EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U), | ||
| 3858 | // .. .. .. FINISH: UPDATE FB_DIV | ||
| 3859 | // .. .. .. START: BY PASS PLL | ||
| 3860 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
| 3861 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U | ||
| 3862 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 3863 | // .. .. .. | ||
| 3864 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), | ||
| 3865 | // .. .. .. FINISH: BY PASS PLL | ||
| 3866 | // .. .. .. START: ASSERT RESET | ||
| 3867 | // .. .. .. PLL_RESET = 1 | ||
| 3868 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U | ||
| 3869 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 3870 | // .. .. .. | ||
| 3871 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), | ||
| 3872 | // .. .. .. FINISH: ASSERT RESET | ||
| 3873 | // .. .. .. START: DEASSERT RESET | ||
| 3874 | // .. .. .. PLL_RESET = 0 | ||
| 3875 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U | ||
| 3876 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 3877 | // .. .. .. | ||
| 3878 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), | ||
| 3879 | // .. .. .. FINISH: DEASSERT RESET | ||
| 3880 | // .. .. .. START: CHECK PLL STATUS | ||
| 3881 | // .. .. .. ARM_PLL_LOCK = 1 | ||
| 3882 | // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U | ||
| 3883 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 3884 | // .. .. .. | ||
| 3885 | EMIT_MASKPOLL(0XF800010C, 0x00000001U), | ||
| 3886 | // .. .. .. FINISH: CHECK PLL STATUS | ||
| 3887 | // .. .. .. START: REMOVE PLL BY PASS | ||
| 3888 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
| 3889 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U | ||
| 3890 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 3891 | // .. .. .. | ||
| 3892 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), | ||
| 3893 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
| 3894 | // .. .. .. SRCSEL = 0x0 | ||
| 3895 | // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U | ||
| 3896 | // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 3897 | // .. .. .. DIVISOR = 0x2 | ||
| 3898 | // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U | ||
| 3899 | // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U | ||
| 3900 | // .. .. .. CPU_6OR4XCLKACT = 0x1 | ||
| 3901 | // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U | ||
| 3902 | // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U | ||
| 3903 | // .. .. .. CPU_3OR2XCLKACT = 0x1 | ||
| 3904 | // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U | ||
| 3905 | // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U | ||
| 3906 | // .. .. .. CPU_2XCLKACT = 0x1 | ||
| 3907 | // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U | ||
| 3908 | // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | ||
| 3909 | // .. .. .. CPU_1XCLKACT = 0x1 | ||
| 3910 | // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U | ||
| 3911 | // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | ||
| 3912 | // .. .. .. CPU_PERI_CLKACT = 0x1 | ||
| 3913 | // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U | ||
| 3914 | // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | ||
| 3915 | // .. .. .. | ||
| 3916 | EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), | ||
| 3917 | // .. .. FINISH: ARM PLL INIT | ||
| 3918 | // .. .. START: DDR PLL INIT | ||
| 3919 | // .. .. PLL_RES = 0xc | ||
| 3920 | // .. .. ==> 0XF8000114[7:4] = 0x0000000CU | ||
| 3921 | // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U | ||
| 3922 | // .. .. PLL_CP = 0x2 | ||
| 3923 | // .. .. ==> 0XF8000114[11:8] = 0x00000002U | ||
| 3924 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
| 3925 | // .. .. LOCK_CNT = 0x1db | ||
| 3926 | // .. .. ==> 0XF8000114[21:12] = 0x000001DBU | ||
| 3927 | // .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U | ||
| 3928 | // .. .. | ||
| 3929 | EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U), | ||
| 3930 | // .. .. .. START: UPDATE FB_DIV | ||
| 3931 | // .. .. .. PLL_FDIV = 0x15 | ||
| 3932 | // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U | ||
| 3933 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U | ||
| 3934 | // .. .. .. | ||
| 3935 | EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U), | ||
| 3936 | // .. .. .. FINISH: UPDATE FB_DIV | ||
| 3937 | // .. .. .. START: BY PASS PLL | ||
| 3938 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
| 3939 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U | ||
| 3940 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 3941 | // .. .. .. | ||
| 3942 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), | ||
| 3943 | // .. .. .. FINISH: BY PASS PLL | ||
| 3944 | // .. .. .. START: ASSERT RESET | ||
| 3945 | // .. .. .. PLL_RESET = 1 | ||
| 3946 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U | ||
| 3947 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 3948 | // .. .. .. | ||
| 3949 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), | ||
| 3950 | // .. .. .. FINISH: ASSERT RESET | ||
| 3951 | // .. .. .. START: DEASSERT RESET | ||
| 3952 | // .. .. .. PLL_RESET = 0 | ||
| 3953 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U | ||
| 3954 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 3955 | // .. .. .. | ||
| 3956 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), | ||
| 3957 | // .. .. .. FINISH: DEASSERT RESET | ||
| 3958 | // .. .. .. START: CHECK PLL STATUS | ||
| 3959 | // .. .. .. DDR_PLL_LOCK = 1 | ||
| 3960 | // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U | ||
| 3961 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 3962 | // .. .. .. | ||
| 3963 | EMIT_MASKPOLL(0XF800010C, 0x00000002U), | ||
| 3964 | // .. .. .. FINISH: CHECK PLL STATUS | ||
| 3965 | // .. .. .. START: REMOVE PLL BY PASS | ||
| 3966 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
| 3967 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U | ||
| 3968 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 3969 | // .. .. .. | ||
| 3970 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), | ||
| 3971 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
| 3972 | // .. .. .. DDR_3XCLKACT = 0x1 | ||
| 3973 | // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U | ||
| 3974 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 3975 | // .. .. .. DDR_2XCLKACT = 0x1 | ||
| 3976 | // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U | ||
| 3977 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 3978 | // .. .. .. DDR_3XCLK_DIVISOR = 0x2 | ||
| 3979 | // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U | ||
| 3980 | // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U | ||
| 3981 | // .. .. .. DDR_2XCLK_DIVISOR = 0x3 | ||
| 3982 | // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U | ||
| 3983 | // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U | ||
| 3984 | // .. .. .. | ||
| 3985 | EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), | ||
| 3986 | // .. .. FINISH: DDR PLL INIT | ||
| 3987 | // .. .. START: IO PLL INIT | ||
| 3988 | // .. .. PLL_RES = 0xc | ||
| 3989 | // .. .. ==> 0XF8000118[7:4] = 0x0000000CU | ||
| 3990 | // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U | ||
| 3991 | // .. .. PLL_CP = 0x2 | ||
| 3992 | // .. .. ==> 0XF8000118[11:8] = 0x00000002U | ||
| 3993 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
| 3994 | // .. .. LOCK_CNT = 0x1f4 | ||
| 3995 | // .. .. ==> 0XF8000118[21:12] = 0x000001F4U | ||
| 3996 | // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U | ||
| 3997 | // .. .. | ||
| 3998 | EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U), | ||
| 3999 | // .. .. .. START: UPDATE FB_DIV | ||
| 4000 | // .. .. .. PLL_FDIV = 0x14 | ||
| 4001 | // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U | ||
| 4002 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U | ||
| 4003 | // .. .. .. | ||
| 4004 | EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U), | ||
| 4005 | // .. .. .. FINISH: UPDATE FB_DIV | ||
| 4006 | // .. .. .. START: BY PASS PLL | ||
| 4007 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
| 4008 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U | ||
| 4009 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 4010 | // .. .. .. | ||
| 4011 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), | ||
| 4012 | // .. .. .. FINISH: BY PASS PLL | ||
| 4013 | // .. .. .. START: ASSERT RESET | ||
| 4014 | // .. .. .. PLL_RESET = 1 | ||
| 4015 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U | ||
| 4016 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 4017 | // .. .. .. | ||
| 4018 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), | ||
| 4019 | // .. .. .. FINISH: ASSERT RESET | ||
| 4020 | // .. .. .. START: DEASSERT RESET | ||
| 4021 | // .. .. .. PLL_RESET = 0 | ||
| 4022 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U | ||
| 4023 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 4024 | // .. .. .. | ||
| 4025 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), | ||
| 4026 | // .. .. .. FINISH: DEASSERT RESET | ||
| 4027 | // .. .. .. START: CHECK PLL STATUS | ||
| 4028 | // .. .. .. IO_PLL_LOCK = 1 | ||
| 4029 | // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U | ||
| 4030 | // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 4031 | // .. .. .. | ||
| 4032 | EMIT_MASKPOLL(0XF800010C, 0x00000004U), | ||
| 4033 | // .. .. .. FINISH: CHECK PLL STATUS | ||
| 4034 | // .. .. .. START: REMOVE PLL BY PASS | ||
| 4035 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
| 4036 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U | ||
| 4037 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 4038 | // .. .. .. | ||
| 4039 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), | ||
| 4040 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
| 4041 | // .. .. FINISH: IO PLL INIT | ||
| 4042 | // .. FINISH: PLL SLCR REGISTERS | ||
| 4043 | // .. START: LOCK IT BACK | ||
| 4044 | // .. LOCK_KEY = 0X767B | ||
| 4045 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
| 4046 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
| 4047 | // .. | ||
| 4048 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
| 4049 | // .. FINISH: LOCK IT BACK | ||
| 4050 | // FINISH: top | ||
| 4051 | // | ||
| 4052 | EMIT_EXIT(), | ||
| 4053 | |||
| 4054 | // | ||
| 4055 | }; | ||
| 4056 | |||
| 4057 | unsigned long ps7_clock_init_data_2_0[] = { | ||
| 4058 | // START: top | ||
| 4059 | // .. START: SLCR SETTINGS | ||
| 4060 | // .. UNLOCK_KEY = 0XDF0D | ||
| 4061 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
| 4062 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
| 4063 | // .. | ||
| 4064 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
| 4065 | // .. FINISH: SLCR SETTINGS | ||
| 4066 | // .. START: CLOCK CONTROL SLCR REGISTERS | ||
| 4067 | // .. CLKACT = 0x1 | ||
| 4068 | // .. ==> 0XF8000128[0:0] = 0x00000001U | ||
| 4069 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 4070 | // .. DIVISOR0 = 0x34 | ||
| 4071 | // .. ==> 0XF8000128[13:8] = 0x00000034U | ||
| 4072 | // .. ==> MASK : 0x00003F00U VAL : 0x00003400U | ||
| 4073 | // .. DIVISOR1 = 0x2 | ||
| 4074 | // .. ==> 0XF8000128[25:20] = 0x00000002U | ||
| 4075 | // .. ==> MASK : 0x03F00000U VAL : 0x00200000U | ||
| 4076 | // .. | ||
| 4077 | EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U), | ||
| 4078 | // .. CLKACT = 0x1 | ||
| 4079 | // .. ==> 0XF8000138[0:0] = 0x00000001U | ||
| 4080 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 4081 | // .. SRCSEL = 0x0 | ||
| 4082 | // .. ==> 0XF8000138[4:4] = 0x00000000U | ||
| 4083 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 4084 | // .. | ||
| 4085 | EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), | ||
| 4086 | // .. CLKACT = 0x1 | ||
| 4087 | // .. ==> 0XF8000140[0:0] = 0x00000001U | ||
| 4088 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 4089 | // .. SRCSEL = 0x0 | ||
| 4090 | // .. ==> 0XF8000140[6:4] = 0x00000000U | ||
| 4091 | // .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
| 4092 | // .. DIVISOR = 0x8 | ||
| 4093 | // .. ==> 0XF8000140[13:8] = 0x00000008U | ||
| 4094 | // .. ==> MASK : 0x00003F00U VAL : 0x00000800U | ||
| 4095 | // .. DIVISOR1 = 0x1 | ||
| 4096 | // .. ==> 0XF8000140[25:20] = 0x00000001U | ||
| 4097 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
| 4098 | // .. | ||
| 4099 | EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), | ||
| 4100 | // .. CLKACT = 0x1 | ||
| 4101 | // .. ==> 0XF800014C[0:0] = 0x00000001U | ||
| 4102 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 4103 | // .. SRCSEL = 0x0 | ||
| 4104 | // .. ==> 0XF800014C[5:4] = 0x00000000U | ||
| 4105 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 4106 | // .. DIVISOR = 0x5 | ||
| 4107 | // .. ==> 0XF800014C[13:8] = 0x00000005U | ||
| 4108 | // .. ==> MASK : 0x00003F00U VAL : 0x00000500U | ||
| 4109 | // .. | ||
| 4110 | EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), | ||
| 4111 | // .. CLKACT0 = 0x1 | ||
| 4112 | // .. ==> 0XF8000150[0:0] = 0x00000001U | ||
| 4113 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 4114 | // .. CLKACT1 = 0x0 | ||
| 4115 | // .. ==> 0XF8000150[1:1] = 0x00000000U | ||
| 4116 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 4117 | // .. SRCSEL = 0x0 | ||
| 4118 | // .. ==> 0XF8000150[5:4] = 0x00000000U | ||
| 4119 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 4120 | // .. DIVISOR = 0x14 | ||
| 4121 | // .. ==> 0XF8000150[13:8] = 0x00000014U | ||
| 4122 | // .. ==> MASK : 0x00003F00U VAL : 0x00001400U | ||
| 4123 | // .. | ||
| 4124 | EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), | ||
| 4125 | // .. CLKACT0 = 0x0 | ||
| 4126 | // .. ==> 0XF8000154[0:0] = 0x00000000U | ||
| 4127 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 4128 | // .. CLKACT1 = 0x1 | ||
| 4129 | // .. ==> 0XF8000154[1:1] = 0x00000001U | ||
| 4130 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 4131 | // .. SRCSEL = 0x0 | ||
| 4132 | // .. ==> 0XF8000154[5:4] = 0x00000000U | ||
| 4133 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 4134 | // .. DIVISOR = 0x14 | ||
| 4135 | // .. ==> 0XF8000154[13:8] = 0x00000014U | ||
| 4136 | // .. ==> MASK : 0x00003F00U VAL : 0x00001400U | ||
| 4137 | // .. | ||
| 4138 | EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), | ||
| 4139 | // .. .. START: TRACE CLOCK | ||
| 4140 | // .. .. FINISH: TRACE CLOCK | ||
| 4141 | // .. .. CLKACT = 0x1 | ||
| 4142 | // .. .. ==> 0XF8000168[0:0] = 0x00000001U | ||
| 4143 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 4144 | // .. .. SRCSEL = 0x0 | ||
| 4145 | // .. .. ==> 0XF8000168[5:4] = 0x00000000U | ||
| 4146 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 4147 | // .. .. DIVISOR = 0x5 | ||
| 4148 | // .. .. ==> 0XF8000168[13:8] = 0x00000005U | ||
| 4149 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U | ||
| 4150 | // .. .. | ||
| 4151 | EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), | ||
| 4152 | // .. .. SRCSEL = 0x0 | ||
| 4153 | // .. .. ==> 0XF8000170[5:4] = 0x00000000U | ||
| 4154 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 4155 | // .. .. DIVISOR0 = 0xa | ||
| 4156 | // .. .. ==> 0XF8000170[13:8] = 0x0000000AU | ||
| 4157 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | ||
| 4158 | // .. .. DIVISOR1 = 0x1 | ||
| 4159 | // .. .. ==> 0XF8000170[25:20] = 0x00000001U | ||
| 4160 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
| 4161 | // .. .. | ||
| 4162 | EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), | ||
| 4163 | // .. .. SRCSEL = 0x3 | ||
| 4164 | // .. .. ==> 0XF8000180[5:4] = 0x00000003U | ||
| 4165 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000030U | ||
| 4166 | // .. .. DIVISOR0 = 0x6 | ||
| 4167 | // .. .. ==> 0XF8000180[13:8] = 0x00000006U | ||
| 4168 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U | ||
| 4169 | // .. .. DIVISOR1 = 0x1 | ||
| 4170 | // .. .. ==> 0XF8000180[25:20] = 0x00000001U | ||
| 4171 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
| 4172 | // .. .. | ||
| 4173 | EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100630U), | ||
| 4174 | // .. .. SRCSEL = 0x2 | ||
| 4175 | // .. .. ==> 0XF8000190[5:4] = 0x00000002U | ||
| 4176 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000020U | ||
| 4177 | // .. .. DIVISOR0 = 0x35 | ||
| 4178 | // .. .. ==> 0XF8000190[13:8] = 0x00000035U | ||
| 4179 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U | ||
| 4180 | // .. .. DIVISOR1 = 0x2 | ||
| 4181 | // .. .. ==> 0XF8000190[25:20] = 0x00000002U | ||
| 4182 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U | ||
| 4183 | // .. .. | ||
| 4184 | EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00203520U), | ||
| 4185 | // .. .. SRCSEL = 0x0 | ||
| 4186 | // .. .. ==> 0XF80001A0[5:4] = 0x00000000U | ||
| 4187 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 4188 | // .. .. DIVISOR0 = 0xa | ||
| 4189 | // .. .. ==> 0XF80001A0[13:8] = 0x0000000AU | ||
| 4190 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | ||
| 4191 | // .. .. DIVISOR1 = 0x1 | ||
| 4192 | // .. .. ==> 0XF80001A0[25:20] = 0x00000001U | ||
| 4193 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
| 4194 | // .. .. | ||
| 4195 | EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100A00U), | ||
| 4196 | // .. .. CLK_621_TRUE = 0x1 | ||
| 4197 | // .. .. ==> 0XF80001C4[0:0] = 0x00000001U | ||
| 4198 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 4199 | // .. .. | ||
| 4200 | EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), | ||
| 4201 | // .. .. DMA_CPU_2XCLKACT = 0x1 | ||
| 4202 | // .. .. ==> 0XF800012C[0:0] = 0x00000001U | ||
| 4203 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 4204 | // .. .. USB0_CPU_1XCLKACT = 0x1 | ||
| 4205 | // .. .. ==> 0XF800012C[2:2] = 0x00000001U | ||
| 4206 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 4207 | // .. .. USB1_CPU_1XCLKACT = 0x1 | ||
| 4208 | // .. .. ==> 0XF800012C[3:3] = 0x00000001U | ||
| 4209 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U | ||
| 4210 | // .. .. GEM0_CPU_1XCLKACT = 0x1 | ||
| 4211 | // .. .. ==> 0XF800012C[6:6] = 0x00000001U | ||
| 4212 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U | ||
| 4213 | // .. .. GEM1_CPU_1XCLKACT = 0x0 | ||
| 4214 | // .. .. ==> 0XF800012C[7:7] = 0x00000000U | ||
| 4215 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 4216 | // .. .. SDI0_CPU_1XCLKACT = 0x1 | ||
| 4217 | // .. .. ==> 0XF800012C[10:10] = 0x00000001U | ||
| 4218 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U | ||
| 4219 | // .. .. SDI1_CPU_1XCLKACT = 0x0 | ||
| 4220 | // .. .. ==> 0XF800012C[11:11] = 0x00000000U | ||
| 4221 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 4222 | // .. .. SPI0_CPU_1XCLKACT = 0x0 | ||
| 4223 | // .. .. ==> 0XF800012C[14:14] = 0x00000000U | ||
| 4224 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
| 4225 | // .. .. SPI1_CPU_1XCLKACT = 0x0 | ||
| 4226 | // .. .. ==> 0XF800012C[15:15] = 0x00000000U | ||
| 4227 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
| 4228 | // .. .. CAN0_CPU_1XCLKACT = 0x0 | ||
| 4229 | // .. .. ==> 0XF800012C[16:16] = 0x00000000U | ||
| 4230 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 4231 | // .. .. CAN1_CPU_1XCLKACT = 0x0 | ||
| 4232 | // .. .. ==> 0XF800012C[17:17] = 0x00000000U | ||
| 4233 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 4234 | // .. .. I2C0_CPU_1XCLKACT = 0x1 | ||
| 4235 | // .. .. ==> 0XF800012C[18:18] = 0x00000001U | ||
| 4236 | // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U | ||
| 4237 | // .. .. I2C1_CPU_1XCLKACT = 0x1 | ||
| 4238 | // .. .. ==> 0XF800012C[19:19] = 0x00000001U | ||
| 4239 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
| 4240 | // .. .. UART0_CPU_1XCLKACT = 0x0 | ||
| 4241 | // .. .. ==> 0XF800012C[20:20] = 0x00000000U | ||
| 4242 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
| 4243 | // .. .. UART1_CPU_1XCLKACT = 0x1 | ||
| 4244 | // .. .. ==> 0XF800012C[21:21] = 0x00000001U | ||
| 4245 | // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U | ||
| 4246 | // .. .. GPIO_CPU_1XCLKACT = 0x1 | ||
| 4247 | // .. .. ==> 0XF800012C[22:22] = 0x00000001U | ||
| 4248 | // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U | ||
| 4249 | // .. .. LQSPI_CPU_1XCLKACT = 0x1 | ||
| 4250 | // .. .. ==> 0XF800012C[23:23] = 0x00000001U | ||
| 4251 | // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U | ||
| 4252 | // .. .. SMC_CPU_1XCLKACT = 0x1 | ||
| 4253 | // .. .. ==> 0XF800012C[24:24] = 0x00000001U | ||
| 4254 | // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U | ||
| 4255 | // .. .. | ||
| 4256 | EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), | ||
| 4257 | // .. FINISH: CLOCK CONTROL SLCR REGISTERS | ||
| 4258 | // .. START: THIS SHOULD BE BLANK | ||
| 4259 | // .. FINISH: THIS SHOULD BE BLANK | ||
| 4260 | // .. START: LOCK IT BACK | ||
| 4261 | // .. LOCK_KEY = 0X767B | ||
| 4262 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
| 4263 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
| 4264 | // .. | ||
| 4265 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
| 4266 | // .. FINISH: LOCK IT BACK | ||
| 4267 | // FINISH: top | ||
| 4268 | // | ||
| 4269 | EMIT_EXIT(), | ||
| 4270 | |||
| 4271 | // | ||
| 4272 | }; | ||
| 4273 | |||
| 4274 | unsigned long ps7_ddr_init_data_2_0[] = { | ||
| 4275 | // START: top | ||
| 4276 | // .. START: DDR INITIALIZATION | ||
| 4277 | // .. .. START: LOCK DDR | ||
| 4278 | // .. .. reg_ddrc_soft_rstb = 0 | ||
| 4279 | // .. .. ==> 0XF8006000[0:0] = 0x00000000U | ||
| 4280 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 4281 | // .. .. reg_ddrc_powerdown_en = 0x0 | ||
| 4282 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | ||
| 4283 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 4284 | // .. .. reg_ddrc_data_bus_width = 0x0 | ||
| 4285 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | ||
| 4286 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | ||
| 4287 | // .. .. reg_ddrc_burst8_refresh = 0x0 | ||
| 4288 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | ||
| 4289 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
| 4290 | // .. .. reg_ddrc_rdwr_idle_gap = 0x1 | ||
| 4291 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | ||
| 4292 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | ||
| 4293 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | ||
| 4294 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | ||
| 4295 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
| 4296 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | ||
| 4297 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | ||
| 4298 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
| 4299 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | ||
| 4300 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | ||
| 4301 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 4302 | // .. .. | ||
| 4303 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), | ||
| 4304 | // .. .. FINISH: LOCK DDR | ||
| 4305 | // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f | ||
| 4306 | // .. .. ==> 0XF8006004[11:0] = 0x0000007FU | ||
| 4307 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU | ||
| 4308 | // .. .. reg_ddrc_active_ranks = 0x1 | ||
| 4309 | // .. .. ==> 0XF8006004[13:12] = 0x00000001U | ||
| 4310 | // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U | ||
| 4311 | // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 | ||
| 4312 | // .. .. ==> 0XF8006004[18:14] = 0x00000000U | ||
| 4313 | // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U | ||
| 4314 | // .. .. reg_ddrc_wr_odt_block = 0x1 | ||
| 4315 | // .. .. ==> 0XF8006004[20:19] = 0x00000001U | ||
| 4316 | // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U | ||
| 4317 | // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 | ||
| 4318 | // .. .. ==> 0XF8006004[21:21] = 0x00000000U | ||
| 4319 | // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U | ||
| 4320 | // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 | ||
| 4321 | // .. .. ==> 0XF8006004[26:22] = 0x00000000U | ||
| 4322 | // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U | ||
| 4323 | // .. .. reg_ddrc_addrmap_open_bank = 0x0 | ||
| 4324 | // .. .. ==> 0XF8006004[27:27] = 0x00000000U | ||
| 4325 | // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U | ||
| 4326 | // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 | ||
| 4327 | // .. .. ==> 0XF8006004[28:28] = 0x00000000U | ||
| 4328 | // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U | ||
| 4329 | // .. .. | ||
| 4330 | EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x0008107FU), | ||
| 4331 | // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf | ||
| 4332 | // .. .. ==> 0XF8006008[10:0] = 0x0000000FU | ||
| 4333 | // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU | ||
| 4334 | // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf | ||
| 4335 | // .. .. ==> 0XF8006008[21:11] = 0x0000000FU | ||
| 4336 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U | ||
| 4337 | // .. .. reg_ddrc_hpr_xact_run_length = 0xf | ||
| 4338 | // .. .. ==> 0XF8006008[25:22] = 0x0000000FU | ||
| 4339 | // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U | ||
| 4340 | // .. .. | ||
| 4341 | EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), | ||
| 4342 | // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 | ||
| 4343 | // .. .. ==> 0XF800600C[10:0] = 0x00000001U | ||
| 4344 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | ||
| 4345 | // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 | ||
| 4346 | // .. .. ==> 0XF800600C[21:11] = 0x00000002U | ||
| 4347 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U | ||
| 4348 | // .. .. reg_ddrc_lpr_xact_run_length = 0x8 | ||
| 4349 | // .. .. ==> 0XF800600C[25:22] = 0x00000008U | ||
| 4350 | // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U | ||
| 4351 | // .. .. | ||
| 4352 | EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), | ||
| 4353 | // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 | ||
| 4354 | // .. .. ==> 0XF8006010[10:0] = 0x00000001U | ||
| 4355 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | ||
| 4356 | // .. .. reg_ddrc_w_xact_run_length = 0x8 | ||
| 4357 | // .. .. ==> 0XF8006010[14:11] = 0x00000008U | ||
| 4358 | // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U | ||
| 4359 | // .. .. reg_ddrc_w_max_starve_x32 = 0x2 | ||
| 4360 | // .. .. ==> 0XF8006010[25:15] = 0x00000002U | ||
| 4361 | // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U | ||
| 4362 | // .. .. | ||
| 4363 | EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), | ||
| 4364 | // .. .. reg_ddrc_t_rc = 0x1a | ||
| 4365 | // .. .. ==> 0XF8006014[5:0] = 0x0000001AU | ||
| 4366 | // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU | ||
| 4367 | // .. .. reg_ddrc_t_rfc_min = 0x54 | ||
| 4368 | // .. .. ==> 0XF8006014[13:6] = 0x00000054U | ||
| 4369 | // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U | ||
| 4370 | // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 | ||
| 4371 | // .. .. ==> 0XF8006014[20:14] = 0x00000010U | ||
| 4372 | // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U | ||
| 4373 | // .. .. | ||
| 4374 | EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU), | ||
| 4375 | // .. .. reg_ddrc_wr2pre = 0x12 | ||
| 4376 | // .. .. ==> 0XF8006018[4:0] = 0x00000012U | ||
| 4377 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U | ||
| 4378 | // .. .. reg_ddrc_powerdown_to_x32 = 0x6 | ||
| 4379 | // .. .. ==> 0XF8006018[9:5] = 0x00000006U | ||
| 4380 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U | ||
| 4381 | // .. .. reg_ddrc_t_faw = 0x15 | ||
| 4382 | // .. .. ==> 0XF8006018[15:10] = 0x00000015U | ||
| 4383 | // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U | ||
| 4384 | // .. .. reg_ddrc_t_ras_max = 0x23 | ||
| 4385 | // .. .. ==> 0XF8006018[21:16] = 0x00000023U | ||
| 4386 | // .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U | ||
| 4387 | // .. .. reg_ddrc_t_ras_min = 0x13 | ||
| 4388 | // .. .. ==> 0XF8006018[26:22] = 0x00000013U | ||
| 4389 | // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U | ||
| 4390 | // .. .. reg_ddrc_t_cke = 0x4 | ||
| 4391 | // .. .. ==> 0XF8006018[31:28] = 0x00000004U | ||
| 4392 | // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U | ||
| 4393 | // .. .. | ||
| 4394 | EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U), | ||
| 4395 | // .. .. reg_ddrc_write_latency = 0x5 | ||
| 4396 | // .. .. ==> 0XF800601C[4:0] = 0x00000005U | ||
| 4397 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U | ||
| 4398 | // .. .. reg_ddrc_rd2wr = 0x7 | ||
| 4399 | // .. .. ==> 0XF800601C[9:5] = 0x00000007U | ||
| 4400 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U | ||
| 4401 | // .. .. reg_ddrc_wr2rd = 0xe | ||
| 4402 | // .. .. ==> 0XF800601C[14:10] = 0x0000000EU | ||
| 4403 | // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U | ||
| 4404 | // .. .. reg_ddrc_t_xp = 0x4 | ||
| 4405 | // .. .. ==> 0XF800601C[19:15] = 0x00000004U | ||
| 4406 | // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U | ||
| 4407 | // .. .. reg_ddrc_pad_pd = 0x0 | ||
| 4408 | // .. .. ==> 0XF800601C[22:20] = 0x00000000U | ||
| 4409 | // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U | ||
| 4410 | // .. .. reg_ddrc_rd2pre = 0x4 | ||
| 4411 | // .. .. ==> 0XF800601C[27:23] = 0x00000004U | ||
| 4412 | // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U | ||
| 4413 | // .. .. reg_ddrc_t_rcd = 0x7 | ||
| 4414 | // .. .. ==> 0XF800601C[31:28] = 0x00000007U | ||
| 4415 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | ||
| 4416 | // .. .. | ||
| 4417 | EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), | ||
| 4418 | // .. .. reg_ddrc_t_ccd = 0x4 | ||
| 4419 | // .. .. ==> 0XF8006020[4:2] = 0x00000004U | ||
| 4420 | // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U | ||
| 4421 | // .. .. reg_ddrc_t_rrd = 0x6 | ||
| 4422 | // .. .. ==> 0XF8006020[7:5] = 0x00000006U | ||
| 4423 | // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U | ||
| 4424 | // .. .. reg_ddrc_refresh_margin = 0x2 | ||
| 4425 | // .. .. ==> 0XF8006020[11:8] = 0x00000002U | ||
| 4426 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
| 4427 | // .. .. reg_ddrc_t_rp = 0x7 | ||
| 4428 | // .. .. ==> 0XF8006020[15:12] = 0x00000007U | ||
| 4429 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U | ||
| 4430 | // .. .. reg_ddrc_refresh_to_x32 = 0x8 | ||
| 4431 | // .. .. ==> 0XF8006020[20:16] = 0x00000008U | ||
| 4432 | // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U | ||
| 4433 | // .. .. reg_ddrc_sdram = 0x1 | ||
| 4434 | // .. .. ==> 0XF8006020[21:21] = 0x00000001U | ||
| 4435 | // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U | ||
| 4436 | // .. .. reg_ddrc_mobile = 0x0 | ||
| 4437 | // .. .. ==> 0XF8006020[22:22] = 0x00000000U | ||
| 4438 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
| 4439 | // .. .. reg_ddrc_clock_stop_en = 0x0 | ||
| 4440 | // .. .. ==> 0XF8006020[23:23] = 0x00000000U | ||
| 4441 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
| 4442 | // .. .. reg_ddrc_read_latency = 0x7 | ||
| 4443 | // .. .. ==> 0XF8006020[28:24] = 0x00000007U | ||
| 4444 | // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U | ||
| 4445 | // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 | ||
| 4446 | // .. .. ==> 0XF8006020[29:29] = 0x00000001U | ||
| 4447 | // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U | ||
| 4448 | // .. .. reg_ddrc_dis_pad_pd = 0x0 | ||
| 4449 | // .. .. ==> 0XF8006020[30:30] = 0x00000000U | ||
| 4450 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | ||
| 4451 | // .. .. reg_ddrc_loopback = 0x0 | ||
| 4452 | // .. .. ==> 0XF8006020[31:31] = 0x00000000U | ||
| 4453 | // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U | ||
| 4454 | // .. .. | ||
| 4455 | EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), | ||
| 4456 | // .. .. reg_ddrc_en_2t_timing_mode = 0x0 | ||
| 4457 | // .. .. ==> 0XF8006024[0:0] = 0x00000000U | ||
| 4458 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 4459 | // .. .. reg_ddrc_prefer_write = 0x0 | ||
| 4460 | // .. .. ==> 0XF8006024[1:1] = 0x00000000U | ||
| 4461 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 4462 | // .. .. reg_ddrc_max_rank_rd = 0xf | ||
| 4463 | // .. .. ==> 0XF8006024[5:2] = 0x0000000FU | ||
| 4464 | // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU | ||
| 4465 | // .. .. reg_ddrc_mr_wr = 0x0 | ||
| 4466 | // .. .. ==> 0XF8006024[6:6] = 0x00000000U | ||
| 4467 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U | ||
| 4468 | // .. .. reg_ddrc_mr_addr = 0x0 | ||
| 4469 | // .. .. ==> 0XF8006024[8:7] = 0x00000000U | ||
| 4470 | // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U | ||
| 4471 | // .. .. reg_ddrc_mr_data = 0x0 | ||
| 4472 | // .. .. ==> 0XF8006024[24:9] = 0x00000000U | ||
| 4473 | // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U | ||
| 4474 | // .. .. ddrc_reg_mr_wr_busy = 0x0 | ||
| 4475 | // .. .. ==> 0XF8006024[25:25] = 0x00000000U | ||
| 4476 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
| 4477 | // .. .. reg_ddrc_mr_type = 0x0 | ||
| 4478 | // .. .. ==> 0XF8006024[26:26] = 0x00000000U | ||
| 4479 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | ||
| 4480 | // .. .. reg_ddrc_mr_rdata_valid = 0x0 | ||
| 4481 | // .. .. ==> 0XF8006024[27:27] = 0x00000000U | ||
| 4482 | // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U | ||
| 4483 | // .. .. | ||
| 4484 | EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), | ||
| 4485 | // .. .. reg_ddrc_final_wait_x32 = 0x7 | ||
| 4486 | // .. .. ==> 0XF8006028[6:0] = 0x00000007U | ||
| 4487 | // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U | ||
| 4488 | // .. .. reg_ddrc_pre_ocd_x32 = 0x0 | ||
| 4489 | // .. .. ==> 0XF8006028[10:7] = 0x00000000U | ||
| 4490 | // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U | ||
| 4491 | // .. .. reg_ddrc_t_mrd = 0x4 | ||
| 4492 | // .. .. ==> 0XF8006028[13:11] = 0x00000004U | ||
| 4493 | // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U | ||
| 4494 | // .. .. | ||
| 4495 | EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), | ||
| 4496 | // .. .. reg_ddrc_emr2 = 0x8 | ||
| 4497 | // .. .. ==> 0XF800602C[15:0] = 0x00000008U | ||
| 4498 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U | ||
| 4499 | // .. .. reg_ddrc_emr3 = 0x0 | ||
| 4500 | // .. .. ==> 0XF800602C[31:16] = 0x00000000U | ||
| 4501 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U | ||
| 4502 | // .. .. | ||
| 4503 | EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), | ||
| 4504 | // .. .. reg_ddrc_mr = 0x930 | ||
| 4505 | // .. .. ==> 0XF8006030[15:0] = 0x00000930U | ||
| 4506 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U | ||
| 4507 | // .. .. reg_ddrc_emr = 0x4 | ||
| 4508 | // .. .. ==> 0XF8006030[31:16] = 0x00000004U | ||
| 4509 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U | ||
| 4510 | // .. .. | ||
| 4511 | EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), | ||
| 4512 | // .. .. reg_ddrc_burst_rdwr = 0x4 | ||
| 4513 | // .. .. ==> 0XF8006034[3:0] = 0x00000004U | ||
| 4514 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U | ||
| 4515 | // .. .. reg_ddrc_pre_cke_x1024 = 0x101 | ||
| 4516 | // .. .. ==> 0XF8006034[13:4] = 0x00000101U | ||
| 4517 | // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U | ||
| 4518 | // .. .. reg_ddrc_post_cke_x1024 = 0x1 | ||
| 4519 | // .. .. ==> 0XF8006034[25:16] = 0x00000001U | ||
| 4520 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U | ||
| 4521 | // .. .. reg_ddrc_burstchop = 0x0 | ||
| 4522 | // .. .. ==> 0XF8006034[28:28] = 0x00000000U | ||
| 4523 | // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U | ||
| 4524 | // .. .. | ||
| 4525 | EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011014U), | ||
| 4526 | // .. .. reg_ddrc_force_low_pri_n = 0x0 | ||
| 4527 | // .. .. ==> 0XF8006038[0:0] = 0x00000000U | ||
| 4528 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 4529 | // .. .. reg_ddrc_dis_dq = 0x0 | ||
| 4530 | // .. .. ==> 0XF8006038[1:1] = 0x00000000U | ||
| 4531 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 4532 | // .. .. reg_phy_debug_mode = 0x0 | ||
| 4533 | // .. .. ==> 0XF8006038[6:6] = 0x00000000U | ||
| 4534 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U | ||
| 4535 | // .. .. reg_phy_wr_level_start = 0x0 | ||
| 4536 | // .. .. ==> 0XF8006038[7:7] = 0x00000000U | ||
| 4537 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 4538 | // .. .. reg_phy_rd_level_start = 0x0 | ||
| 4539 | // .. .. ==> 0XF8006038[8:8] = 0x00000000U | ||
| 4540 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 4541 | // .. .. reg_phy_dq0_wait_t = 0x0 | ||
| 4542 | // .. .. ==> 0XF8006038[12:9] = 0x00000000U | ||
| 4543 | // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U | ||
| 4544 | // .. .. | ||
| 4545 | EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), | ||
| 4546 | // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 | ||
| 4547 | // .. .. ==> 0XF800603C[3:0] = 0x00000007U | ||
| 4548 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U | ||
| 4549 | // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 | ||
| 4550 | // .. .. ==> 0XF800603C[7:4] = 0x00000007U | ||
| 4551 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U | ||
| 4552 | // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 | ||
| 4553 | // .. .. ==> 0XF800603C[11:8] = 0x00000007U | ||
| 4554 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U | ||
| 4555 | // .. .. reg_ddrc_addrmap_col_b5 = 0x0 | ||
| 4556 | // .. .. ==> 0XF800603C[15:12] = 0x00000000U | ||
| 4557 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | ||
| 4558 | // .. .. reg_ddrc_addrmap_col_b6 = 0x0 | ||
| 4559 | // .. .. ==> 0XF800603C[19:16] = 0x00000000U | ||
| 4560 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | ||
| 4561 | // .. .. | ||
| 4562 | EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), | ||
| 4563 | // .. .. reg_ddrc_addrmap_col_b2 = 0x0 | ||
| 4564 | // .. .. ==> 0XF8006040[3:0] = 0x00000000U | ||
| 4565 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
| 4566 | // .. .. reg_ddrc_addrmap_col_b3 = 0x0 | ||
| 4567 | // .. .. ==> 0XF8006040[7:4] = 0x00000000U | ||
| 4568 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
| 4569 | // .. .. reg_ddrc_addrmap_col_b4 = 0x0 | ||
| 4570 | // .. .. ==> 0XF8006040[11:8] = 0x00000000U | ||
| 4571 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | ||
| 4572 | // .. .. reg_ddrc_addrmap_col_b7 = 0x0 | ||
| 4573 | // .. .. ==> 0XF8006040[15:12] = 0x00000000U | ||
| 4574 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | ||
| 4575 | // .. .. reg_ddrc_addrmap_col_b8 = 0x0 | ||
| 4576 | // .. .. ==> 0XF8006040[19:16] = 0x00000000U | ||
| 4577 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | ||
| 4578 | // .. .. reg_ddrc_addrmap_col_b9 = 0xf | ||
| 4579 | // .. .. ==> 0XF8006040[23:20] = 0x0000000FU | ||
| 4580 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U | ||
| 4581 | // .. .. reg_ddrc_addrmap_col_b10 = 0xf | ||
| 4582 | // .. .. ==> 0XF8006040[27:24] = 0x0000000FU | ||
| 4583 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | ||
| 4584 | // .. .. reg_ddrc_addrmap_col_b11 = 0xf | ||
| 4585 | // .. .. ==> 0XF8006040[31:28] = 0x0000000FU | ||
| 4586 | // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U | ||
| 4587 | // .. .. | ||
| 4588 | EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), | ||
| 4589 | // .. .. reg_ddrc_addrmap_row_b0 = 0x6 | ||
| 4590 | // .. .. ==> 0XF8006044[3:0] = 0x00000006U | ||
| 4591 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U | ||
| 4592 | // .. .. reg_ddrc_addrmap_row_b1 = 0x6 | ||
| 4593 | // .. .. ==> 0XF8006044[7:4] = 0x00000006U | ||
| 4594 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U | ||
| 4595 | // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 | ||
| 4596 | // .. .. ==> 0XF8006044[11:8] = 0x00000006U | ||
| 4597 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U | ||
| 4598 | // .. .. reg_ddrc_addrmap_row_b12 = 0x6 | ||
| 4599 | // .. .. ==> 0XF8006044[15:12] = 0x00000006U | ||
| 4600 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U | ||
| 4601 | // .. .. reg_ddrc_addrmap_row_b13 = 0x6 | ||
| 4602 | // .. .. ==> 0XF8006044[19:16] = 0x00000006U | ||
| 4603 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U | ||
| 4604 | // .. .. reg_ddrc_addrmap_row_b14 = 0xf | ||
| 4605 | // .. .. ==> 0XF8006044[23:20] = 0x0000000FU | ||
| 4606 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U | ||
| 4607 | // .. .. reg_ddrc_addrmap_row_b15 = 0xf | ||
| 4608 | // .. .. ==> 0XF8006044[27:24] = 0x0000000FU | ||
| 4609 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | ||
| 4610 | // .. .. | ||
| 4611 | EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U), | ||
| 4612 | // .. .. reg_ddrc_rank0_rd_odt = 0x0 | ||
| 4613 | // .. .. ==> 0XF8006048[2:0] = 0x00000000U | ||
| 4614 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | ||
| 4615 | // .. .. reg_ddrc_rank0_wr_odt = 0x1 | ||
| 4616 | // .. .. ==> 0XF8006048[5:3] = 0x00000001U | ||
| 4617 | // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U | ||
| 4618 | // .. .. reg_ddrc_rank1_rd_odt = 0x1 | ||
| 4619 | // .. .. ==> 0XF8006048[8:6] = 0x00000001U | ||
| 4620 | // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U | ||
| 4621 | // .. .. reg_ddrc_rank1_wr_odt = 0x1 | ||
| 4622 | // .. .. ==> 0XF8006048[11:9] = 0x00000001U | ||
| 4623 | // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 4624 | // .. .. reg_phy_rd_local_odt = 0x0 | ||
| 4625 | // .. .. ==> 0XF8006048[13:12] = 0x00000000U | ||
| 4626 | // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U | ||
| 4627 | // .. .. reg_phy_wr_local_odt = 0x3 | ||
| 4628 | // .. .. ==> 0XF8006048[15:14] = 0x00000003U | ||
| 4629 | // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U | ||
| 4630 | // .. .. reg_phy_idle_local_odt = 0x3 | ||
| 4631 | // .. .. ==> 0XF8006048[17:16] = 0x00000003U | ||
| 4632 | // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U | ||
| 4633 | // .. .. reg_ddrc_rank2_rd_odt = 0x0 | ||
| 4634 | // .. .. ==> 0XF8006048[20:18] = 0x00000000U | ||
| 4635 | // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U | ||
| 4636 | // .. .. reg_ddrc_rank2_wr_odt = 0x0 | ||
| 4637 | // .. .. ==> 0XF8006048[23:21] = 0x00000000U | ||
| 4638 | // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U | ||
| 4639 | // .. .. reg_ddrc_rank3_rd_odt = 0x0 | ||
| 4640 | // .. .. ==> 0XF8006048[26:24] = 0x00000000U | ||
| 4641 | // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
| 4642 | // .. .. reg_ddrc_rank3_wr_odt = 0x0 | ||
| 4643 | // .. .. ==> 0XF8006048[29:27] = 0x00000000U | ||
| 4644 | // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U | ||
| 4645 | // .. .. | ||
| 4646 | EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), | ||
| 4647 | // .. .. reg_phy_rd_cmd_to_data = 0x0 | ||
| 4648 | // .. .. ==> 0XF8006050[3:0] = 0x00000000U | ||
| 4649 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
| 4650 | // .. .. reg_phy_wr_cmd_to_data = 0x0 | ||
| 4651 | // .. .. ==> 0XF8006050[7:4] = 0x00000000U | ||
| 4652 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
| 4653 | // .. .. reg_phy_rdc_we_to_re_delay = 0x8 | ||
| 4654 | // .. .. ==> 0XF8006050[11:8] = 0x00000008U | ||
| 4655 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U | ||
| 4656 | // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 | ||
| 4657 | // .. .. ==> 0XF8006050[15:15] = 0x00000000U | ||
| 4658 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
| 4659 | // .. .. reg_phy_use_fixed_re = 0x1 | ||
| 4660 | // .. .. ==> 0XF8006050[16:16] = 0x00000001U | ||
| 4661 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | ||
| 4662 | // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 | ||
| 4663 | // .. .. ==> 0XF8006050[17:17] = 0x00000000U | ||
| 4664 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 4665 | // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 | ||
| 4666 | // .. .. ==> 0XF8006050[18:18] = 0x00000000U | ||
| 4667 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 4668 | // .. .. reg_phy_clk_stall_level = 0x0 | ||
| 4669 | // .. .. ==> 0XF8006050[19:19] = 0x00000000U | ||
| 4670 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
| 4671 | // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 | ||
| 4672 | // .. .. ==> 0XF8006050[27:24] = 0x00000007U | ||
| 4673 | // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U | ||
| 4674 | // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 | ||
| 4675 | // .. .. ==> 0XF8006050[31:28] = 0x00000007U | ||
| 4676 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | ||
| 4677 | // .. .. | ||
| 4678 | EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), | ||
| 4679 | // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 | ||
| 4680 | // .. .. ==> 0XF8006058[7:0] = 0x00000001U | ||
| 4681 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U | ||
| 4682 | // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 | ||
| 4683 | // .. .. ==> 0XF8006058[15:8] = 0x00000001U | ||
| 4684 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U | ||
| 4685 | // .. .. reg_ddrc_dis_dll_calib = 0x0 | ||
| 4686 | // .. .. ==> 0XF8006058[16:16] = 0x00000000U | ||
| 4687 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 4688 | // .. .. | ||
| 4689 | EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), | ||
| 4690 | // .. .. reg_ddrc_rd_odt_delay = 0x3 | ||
| 4691 | // .. .. ==> 0XF800605C[3:0] = 0x00000003U | ||
| 4692 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U | ||
| 4693 | // .. .. reg_ddrc_wr_odt_delay = 0x0 | ||
| 4694 | // .. .. ==> 0XF800605C[7:4] = 0x00000000U | ||
| 4695 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
| 4696 | // .. .. reg_ddrc_rd_odt_hold = 0x0 | ||
| 4697 | // .. .. ==> 0XF800605C[11:8] = 0x00000000U | ||
| 4698 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | ||
| 4699 | // .. .. reg_ddrc_wr_odt_hold = 0x5 | ||
| 4700 | // .. .. ==> 0XF800605C[15:12] = 0x00000005U | ||
| 4701 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U | ||
| 4702 | // .. .. | ||
| 4703 | EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), | ||
| 4704 | // .. .. reg_ddrc_pageclose = 0x0 | ||
| 4705 | // .. .. ==> 0XF8006060[0:0] = 0x00000000U | ||
| 4706 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 4707 | // .. .. reg_ddrc_lpr_num_entries = 0x1f | ||
| 4708 | // .. .. ==> 0XF8006060[6:1] = 0x0000001FU | ||
| 4709 | // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU | ||
| 4710 | // .. .. reg_ddrc_auto_pre_en = 0x0 | ||
| 4711 | // .. .. ==> 0XF8006060[7:7] = 0x00000000U | ||
| 4712 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 4713 | // .. .. reg_ddrc_refresh_update_level = 0x0 | ||
| 4714 | // .. .. ==> 0XF8006060[8:8] = 0x00000000U | ||
| 4715 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 4716 | // .. .. reg_ddrc_dis_wc = 0x0 | ||
| 4717 | // .. .. ==> 0XF8006060[9:9] = 0x00000000U | ||
| 4718 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
| 4719 | // .. .. reg_ddrc_dis_collision_page_opt = 0x0 | ||
| 4720 | // .. .. ==> 0XF8006060[10:10] = 0x00000000U | ||
| 4721 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 4722 | // .. .. reg_ddrc_selfref_en = 0x0 | ||
| 4723 | // .. .. ==> 0XF8006060[12:12] = 0x00000000U | ||
| 4724 | // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 4725 | // .. .. | ||
| 4726 | EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), | ||
| 4727 | // .. .. reg_ddrc_go2critical_hysteresis = 0x0 | ||
| 4728 | // .. .. ==> 0XF8006064[12:5] = 0x00000000U | ||
| 4729 | // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U | ||
| 4730 | // .. .. reg_arb_go2critical_en = 0x1 | ||
| 4731 | // .. .. ==> 0XF8006064[17:17] = 0x00000001U | ||
| 4732 | // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U | ||
| 4733 | // .. .. | ||
| 4734 | EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), | ||
| 4735 | // .. .. reg_ddrc_wrlvl_ww = 0x41 | ||
| 4736 | // .. .. ==> 0XF8006068[7:0] = 0x00000041U | ||
| 4737 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U | ||
| 4738 | // .. .. reg_ddrc_rdlvl_rr = 0x41 | ||
| 4739 | // .. .. ==> 0XF8006068[15:8] = 0x00000041U | ||
| 4740 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U | ||
| 4741 | // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 | ||
| 4742 | // .. .. ==> 0XF8006068[25:16] = 0x00000028U | ||
| 4743 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U | ||
| 4744 | // .. .. | ||
| 4745 | EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), | ||
| 4746 | // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 | ||
| 4747 | // .. .. ==> 0XF800606C[7:0] = 0x00000010U | ||
| 4748 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U | ||
| 4749 | // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 | ||
| 4750 | // .. .. ==> 0XF800606C[15:8] = 0x00000016U | ||
| 4751 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U | ||
| 4752 | // .. .. | ||
| 4753 | EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), | ||
| 4754 | // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 | ||
| 4755 | // .. .. ==> 0XF8006078[3:0] = 0x00000001U | ||
| 4756 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U | ||
| 4757 | // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 | ||
| 4758 | // .. .. ==> 0XF8006078[7:4] = 0x00000001U | ||
| 4759 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U | ||
| 4760 | // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 | ||
| 4761 | // .. .. ==> 0XF8006078[11:8] = 0x00000001U | ||
| 4762 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U | ||
| 4763 | // .. .. reg_ddrc_t_cksre = 0x6 | ||
| 4764 | // .. .. ==> 0XF8006078[15:12] = 0x00000006U | ||
| 4765 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U | ||
| 4766 | // .. .. reg_ddrc_t_cksrx = 0x6 | ||
| 4767 | // .. .. ==> 0XF8006078[19:16] = 0x00000006U | ||
| 4768 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U | ||
| 4769 | // .. .. reg_ddrc_t_ckesr = 0x4 | ||
| 4770 | // .. .. ==> 0XF8006078[25:20] = 0x00000004U | ||
| 4771 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U | ||
| 4772 | // .. .. | ||
| 4773 | EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), | ||
| 4774 | // .. .. reg_ddrc_t_ckpde = 0x2 | ||
| 4775 | // .. .. ==> 0XF800607C[3:0] = 0x00000002U | ||
| 4776 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U | ||
| 4777 | // .. .. reg_ddrc_t_ckpdx = 0x2 | ||
| 4778 | // .. .. ==> 0XF800607C[7:4] = 0x00000002U | ||
| 4779 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U | ||
| 4780 | // .. .. reg_ddrc_t_ckdpde = 0x2 | ||
| 4781 | // .. .. ==> 0XF800607C[11:8] = 0x00000002U | ||
| 4782 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
| 4783 | // .. .. reg_ddrc_t_ckdpdx = 0x2 | ||
| 4784 | // .. .. ==> 0XF800607C[15:12] = 0x00000002U | ||
| 4785 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U | ||
| 4786 | // .. .. reg_ddrc_t_ckcsx = 0x3 | ||
| 4787 | // .. .. ==> 0XF800607C[19:16] = 0x00000003U | ||
| 4788 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U | ||
| 4789 | // .. .. | ||
| 4790 | EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), | ||
| 4791 | // .. .. refresh_timer0_start_value_x32 = 0x0 | ||
| 4792 | // .. .. ==> 0XF80060A0[11:0] = 0x00000000U | ||
| 4793 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U | ||
| 4794 | // .. .. refresh_timer1_start_value_x32 = 0x8 | ||
| 4795 | // .. .. ==> 0XF80060A0[23:12] = 0x00000008U | ||
| 4796 | // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U | ||
| 4797 | // .. .. | ||
| 4798 | EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), | ||
| 4799 | // .. .. reg_ddrc_dis_auto_zq = 0x0 | ||
| 4800 | // .. .. ==> 0XF80060A4[0:0] = 0x00000000U | ||
| 4801 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 4802 | // .. .. reg_ddrc_ddr3 = 0x1 | ||
| 4803 | // .. .. ==> 0XF80060A4[1:1] = 0x00000001U | ||
| 4804 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 4805 | // .. .. reg_ddrc_t_mod = 0x200 | ||
| 4806 | // .. .. ==> 0XF80060A4[11:2] = 0x00000200U | ||
| 4807 | // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U | ||
| 4808 | // .. .. reg_ddrc_t_zq_long_nop = 0x200 | ||
| 4809 | // .. .. ==> 0XF80060A4[21:12] = 0x00000200U | ||
| 4810 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U | ||
| 4811 | // .. .. reg_ddrc_t_zq_short_nop = 0x40 | ||
| 4812 | // .. .. ==> 0XF80060A4[31:22] = 0x00000040U | ||
| 4813 | // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U | ||
| 4814 | // .. .. | ||
| 4815 | EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), | ||
| 4816 | // .. .. t_zq_short_interval_x1024 = 0xc845 | ||
| 4817 | // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U | ||
| 4818 | // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U | ||
| 4819 | // .. .. dram_rstn_x1024 = 0x67 | ||
| 4820 | // .. .. ==> 0XF80060A8[27:20] = 0x00000067U | ||
| 4821 | // .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U | ||
| 4822 | // .. .. | ||
| 4823 | EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U), | ||
| 4824 | // .. .. deeppowerdown_en = 0x0 | ||
| 4825 | // .. .. ==> 0XF80060AC[0:0] = 0x00000000U | ||
| 4826 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 4827 | // .. .. deeppowerdown_to_x1024 = 0xff | ||
| 4828 | // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU | ||
| 4829 | // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU | ||
| 4830 | // .. .. | ||
| 4831 | EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), | ||
| 4832 | // .. .. dfi_wrlvl_max_x1024 = 0xfff | ||
| 4833 | // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU | ||
| 4834 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU | ||
| 4835 | // .. .. dfi_rdlvl_max_x1024 = 0xfff | ||
| 4836 | // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU | ||
| 4837 | // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U | ||
| 4838 | // .. .. ddrc_reg_twrlvl_max_error = 0x0 | ||
| 4839 | // .. .. ==> 0XF80060B0[24:24] = 0x00000000U | ||
| 4840 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
| 4841 | // .. .. ddrc_reg_trdlvl_max_error = 0x0 | ||
| 4842 | // .. .. ==> 0XF80060B0[25:25] = 0x00000000U | ||
| 4843 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
| 4844 | // .. .. reg_ddrc_dfi_wr_level_en = 0x1 | ||
| 4845 | // .. .. ==> 0XF80060B0[26:26] = 0x00000001U | ||
| 4846 | // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | ||
| 4847 | // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 | ||
| 4848 | // .. .. ==> 0XF80060B0[27:27] = 0x00000001U | ||
| 4849 | // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | ||
| 4850 | // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 | ||
| 4851 | // .. .. ==> 0XF80060B0[28:28] = 0x00000001U | ||
| 4852 | // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | ||
| 4853 | // .. .. | ||
| 4854 | EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), | ||
| 4855 | // .. .. reg_ddrc_2t_delay = 0x0 | ||
| 4856 | // .. .. ==> 0XF80060B4[8:0] = 0x00000000U | ||
| 4857 | // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U | ||
| 4858 | // .. .. reg_ddrc_skip_ocd = 0x1 | ||
| 4859 | // .. .. ==> 0XF80060B4[9:9] = 0x00000001U | ||
| 4860 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U | ||
| 4861 | // .. .. reg_ddrc_dis_pre_bypass = 0x0 | ||
| 4862 | // .. .. ==> 0XF80060B4[10:10] = 0x00000000U | ||
| 4863 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 4864 | // .. .. | ||
| 4865 | EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), | ||
| 4866 | // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 | ||
| 4867 | // .. .. ==> 0XF80060B8[4:0] = 0x00000006U | ||
| 4868 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U | ||
| 4869 | // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 | ||
| 4870 | // .. .. ==> 0XF80060B8[14:5] = 0x00000003U | ||
| 4871 | // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U | ||
| 4872 | // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 | ||
| 4873 | // .. .. ==> 0XF80060B8[24:15] = 0x00000040U | ||
| 4874 | // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U | ||
| 4875 | // .. .. | ||
| 4876 | EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), | ||
| 4877 | // .. .. START: RESET ECC ERROR | ||
| 4878 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 | ||
| 4879 | // .. .. ==> 0XF80060C4[0:0] = 0x00000001U | ||
| 4880 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 4881 | // .. .. Clear_Correctable_DRAM_ECC_error = 1 | ||
| 4882 | // .. .. ==> 0XF80060C4[1:1] = 0x00000001U | ||
| 4883 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 4884 | // .. .. | ||
| 4885 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), | ||
| 4886 | // .. .. FINISH: RESET ECC ERROR | ||
| 4887 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 | ||
| 4888 | // .. .. ==> 0XF80060C4[0:0] = 0x00000000U | ||
| 4889 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 4890 | // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 | ||
| 4891 | // .. .. ==> 0XF80060C4[1:1] = 0x00000000U | ||
| 4892 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 4893 | // .. .. | ||
| 4894 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), | ||
| 4895 | // .. .. CORR_ECC_LOG_VALID = 0x0 | ||
| 4896 | // .. .. ==> 0XF80060C8[0:0] = 0x00000000U | ||
| 4897 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 4898 | // .. .. ECC_CORRECTED_BIT_NUM = 0x0 | ||
| 4899 | // .. .. ==> 0XF80060C8[7:1] = 0x00000000U | ||
| 4900 | // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U | ||
| 4901 | // .. .. | ||
| 4902 | EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), | ||
| 4903 | // .. .. UNCORR_ECC_LOG_VALID = 0x0 | ||
| 4904 | // .. .. ==> 0XF80060DC[0:0] = 0x00000000U | ||
| 4905 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 4906 | // .. .. | ||
| 4907 | EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), | ||
| 4908 | // .. .. STAT_NUM_CORR_ERR = 0x0 | ||
| 4909 | // .. .. ==> 0XF80060F0[15:8] = 0x00000000U | ||
| 4910 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U | ||
| 4911 | // .. .. STAT_NUM_UNCORR_ERR = 0x0 | ||
| 4912 | // .. .. ==> 0XF80060F0[7:0] = 0x00000000U | ||
| 4913 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U | ||
| 4914 | // .. .. | ||
| 4915 | EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), | ||
| 4916 | // .. .. reg_ddrc_ecc_mode = 0x0 | ||
| 4917 | // .. .. ==> 0XF80060F4[2:0] = 0x00000000U | ||
| 4918 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | ||
| 4919 | // .. .. reg_ddrc_dis_scrub = 0x1 | ||
| 4920 | // .. .. ==> 0XF80060F4[3:3] = 0x00000001U | ||
| 4921 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U | ||
| 4922 | // .. .. | ||
| 4923 | EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), | ||
| 4924 | // .. .. reg_phy_dif_on = 0x0 | ||
| 4925 | // .. .. ==> 0XF8006114[3:0] = 0x00000000U | ||
| 4926 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
| 4927 | // .. .. reg_phy_dif_off = 0x0 | ||
| 4928 | // .. .. ==> 0XF8006114[7:4] = 0x00000000U | ||
| 4929 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
| 4930 | // .. .. | ||
| 4931 | EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), | ||
| 4932 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
| 4933 | // .. .. ==> 0XF8006118[0:0] = 0x00000001U | ||
| 4934 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 4935 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
| 4936 | // .. .. ==> 0XF8006118[1:1] = 0x00000000U | ||
| 4937 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 4938 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
| 4939 | // .. .. ==> 0XF8006118[2:2] = 0x00000000U | ||
| 4940 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 4941 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
| 4942 | // .. .. ==> 0XF8006118[3:3] = 0x00000000U | ||
| 4943 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 4944 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
| 4945 | // .. .. ==> 0XF8006118[4:4] = 0x00000000U | ||
| 4946 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 4947 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
| 4948 | // .. .. ==> 0XF8006118[5:5] = 0x00000000U | ||
| 4949 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
| 4950 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
| 4951 | // .. .. ==> 0XF8006118[14:6] = 0x00000000U | ||
| 4952 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
| 4953 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
| 4954 | // .. .. ==> 0XF8006118[23:15] = 0x00000000U | ||
| 4955 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
| 4956 | // .. .. reg_phy_dq_offset = 0x40 | ||
| 4957 | // .. .. ==> 0XF8006118[30:24] = 0x00000040U | ||
| 4958 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
| 4959 | // .. .. | ||
| 4960 | EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), | ||
| 4961 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
| 4962 | // .. .. ==> 0XF800611C[0:0] = 0x00000001U | ||
| 4963 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 4964 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
| 4965 | // .. .. ==> 0XF800611C[1:1] = 0x00000000U | ||
| 4966 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 4967 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
| 4968 | // .. .. ==> 0XF800611C[2:2] = 0x00000000U | ||
| 4969 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 4970 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
| 4971 | // .. .. ==> 0XF800611C[3:3] = 0x00000000U | ||
| 4972 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 4973 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
| 4974 | // .. .. ==> 0XF800611C[4:4] = 0x00000000U | ||
| 4975 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 4976 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
| 4977 | // .. .. ==> 0XF800611C[5:5] = 0x00000000U | ||
| 4978 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
| 4979 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
| 4980 | // .. .. ==> 0XF800611C[14:6] = 0x00000000U | ||
| 4981 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
| 4982 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
| 4983 | // .. .. ==> 0XF800611C[23:15] = 0x00000000U | ||
| 4984 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
| 4985 | // .. .. reg_phy_dq_offset = 0x40 | ||
| 4986 | // .. .. ==> 0XF800611C[30:24] = 0x00000040U | ||
| 4987 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
| 4988 | // .. .. | ||
| 4989 | EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), | ||
| 4990 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
| 4991 | // .. .. ==> 0XF8006120[0:0] = 0x00000001U | ||
| 4992 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 4993 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
| 4994 | // .. .. ==> 0XF8006120[1:1] = 0x00000000U | ||
| 4995 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 4996 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
| 4997 | // .. .. ==> 0XF8006120[2:2] = 0x00000000U | ||
| 4998 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 4999 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
| 5000 | // .. .. ==> 0XF8006120[3:3] = 0x00000000U | ||
| 5001 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 5002 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
| 5003 | // .. .. ==> 0XF8006120[4:4] = 0x00000000U | ||
| 5004 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 5005 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
| 5006 | // .. .. ==> 0XF8006120[5:5] = 0x00000000U | ||
| 5007 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
| 5008 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
| 5009 | // .. .. ==> 0XF8006120[14:6] = 0x00000000U | ||
| 5010 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
| 5011 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
| 5012 | // .. .. ==> 0XF8006120[23:15] = 0x00000000U | ||
| 5013 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
| 5014 | // .. .. reg_phy_dq_offset = 0x40 | ||
| 5015 | // .. .. ==> 0XF8006120[30:24] = 0x00000040U | ||
| 5016 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
| 5017 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
| 5018 | // .. .. ==> 0XF8006120[0:0] = 0x00000001U | ||
| 5019 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 5020 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
| 5021 | // .. .. ==> 0XF8006120[1:1] = 0x00000000U | ||
| 5022 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 5023 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
| 5024 | // .. .. ==> 0XF8006120[2:2] = 0x00000000U | ||
| 5025 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 5026 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
| 5027 | // .. .. ==> 0XF8006120[3:3] = 0x00000000U | ||
| 5028 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 5029 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
| 5030 | // .. .. ==> 0XF8006120[4:4] = 0x00000000U | ||
| 5031 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 5032 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
| 5033 | // .. .. ==> 0XF8006120[5:5] = 0x00000000U | ||
| 5034 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
| 5035 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
| 5036 | // .. .. ==> 0XF8006120[14:6] = 0x00000000U | ||
| 5037 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
| 5038 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
| 5039 | // .. .. ==> 0XF8006120[23:15] = 0x00000000U | ||
| 5040 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
| 5041 | // .. .. reg_phy_dq_offset = 0x40 | ||
| 5042 | // .. .. ==> 0XF8006120[30:24] = 0x00000040U | ||
| 5043 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
| 5044 | // .. .. | ||
| 5045 | EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), | ||
| 5046 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
| 5047 | // .. .. ==> 0XF8006124[0:0] = 0x00000001U | ||
| 5048 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 5049 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
| 5050 | // .. .. ==> 0XF8006124[1:1] = 0x00000000U | ||
| 5051 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 5052 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
| 5053 | // .. .. ==> 0XF8006124[2:2] = 0x00000000U | ||
| 5054 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 5055 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
| 5056 | // .. .. ==> 0XF8006124[3:3] = 0x00000000U | ||
| 5057 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 5058 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
| 5059 | // .. .. ==> 0XF8006124[4:4] = 0x00000000U | ||
| 5060 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 5061 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
| 5062 | // .. .. ==> 0XF8006124[5:5] = 0x00000000U | ||
| 5063 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
| 5064 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
| 5065 | // .. .. ==> 0XF8006124[14:6] = 0x00000000U | ||
| 5066 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
| 5067 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
| 5068 | // .. .. ==> 0XF8006124[23:15] = 0x00000000U | ||
| 5069 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
| 5070 | // .. .. reg_phy_dq_offset = 0x40 | ||
| 5071 | // .. .. ==> 0XF8006124[30:24] = 0x00000040U | ||
| 5072 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
| 5073 | // .. .. | ||
| 5074 | EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), | ||
| 5075 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
| 5076 | // .. .. ==> 0XF800612C[9:0] = 0x00000000U | ||
| 5077 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
| 5078 | // .. .. reg_phy_gatelvl_init_ratio = 0x8f | ||
| 5079 | // .. .. ==> 0XF800612C[19:10] = 0x0000008FU | ||
| 5080 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U | ||
| 5081 | // .. .. | ||
| 5082 | EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U), | ||
| 5083 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
| 5084 | // .. .. ==> 0XF8006130[9:0] = 0x00000000U | ||
| 5085 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
| 5086 | // .. .. reg_phy_gatelvl_init_ratio = 0x8a | ||
| 5087 | // .. .. ==> 0XF8006130[19:10] = 0x0000008AU | ||
| 5088 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U | ||
| 5089 | // .. .. | ||
| 5090 | EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U), | ||
| 5091 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
| 5092 | // .. .. ==> 0XF8006134[9:0] = 0x00000000U | ||
| 5093 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
| 5094 | // .. .. reg_phy_gatelvl_init_ratio = 0x8b | ||
| 5095 | // .. .. ==> 0XF8006134[19:10] = 0x0000008BU | ||
| 5096 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U | ||
| 5097 | // .. .. | ||
| 5098 | EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U), | ||
| 5099 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
| 5100 | // .. .. ==> 0XF8006138[9:0] = 0x00000000U | ||
| 5101 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
| 5102 | // .. .. reg_phy_gatelvl_init_ratio = 0x92 | ||
| 5103 | // .. .. ==> 0XF8006138[19:10] = 0x00000092U | ||
| 5104 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U | ||
| 5105 | // .. .. | ||
| 5106 | EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U), | ||
| 5107 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
| 5108 | // .. .. ==> 0XF8006140[9:0] = 0x00000035U | ||
| 5109 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
| 5110 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
| 5111 | // .. .. ==> 0XF8006140[10:10] = 0x00000000U | ||
| 5112 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 5113 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
| 5114 | // .. .. ==> 0XF8006140[19:11] = 0x00000000U | ||
| 5115 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 5116 | // .. .. | ||
| 5117 | EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), | ||
| 5118 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
| 5119 | // .. .. ==> 0XF8006144[9:0] = 0x00000035U | ||
| 5120 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
| 5121 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
| 5122 | // .. .. ==> 0XF8006144[10:10] = 0x00000000U | ||
| 5123 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 5124 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
| 5125 | // .. .. ==> 0XF8006144[19:11] = 0x00000000U | ||
| 5126 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 5127 | // .. .. | ||
| 5128 | EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), | ||
| 5129 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
| 5130 | // .. .. ==> 0XF8006148[9:0] = 0x00000035U | ||
| 5131 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
| 5132 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
| 5133 | // .. .. ==> 0XF8006148[10:10] = 0x00000000U | ||
| 5134 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 5135 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
| 5136 | // .. .. ==> 0XF8006148[19:11] = 0x00000000U | ||
| 5137 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 5138 | // .. .. | ||
| 5139 | EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), | ||
| 5140 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
| 5141 | // .. .. ==> 0XF800614C[9:0] = 0x00000035U | ||
| 5142 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
| 5143 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
| 5144 | // .. .. ==> 0XF800614C[10:10] = 0x00000000U | ||
| 5145 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 5146 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
| 5147 | // .. .. ==> 0XF800614C[19:11] = 0x00000000U | ||
| 5148 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 5149 | // .. .. | ||
| 5150 | EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), | ||
| 5151 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 | ||
| 5152 | // .. .. ==> 0XF8006154[9:0] = 0x00000077U | ||
| 5153 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U | ||
| 5154 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
| 5155 | // .. .. ==> 0XF8006154[10:10] = 0x00000000U | ||
| 5156 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 5157 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
| 5158 | // .. .. ==> 0XF8006154[19:11] = 0x00000000U | ||
| 5159 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 5160 | // .. .. | ||
| 5161 | EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U), | ||
| 5162 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c | ||
| 5163 | // .. .. ==> 0XF8006158[9:0] = 0x0000007CU | ||
| 5164 | // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU | ||
| 5165 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
| 5166 | // .. .. ==> 0XF8006158[10:10] = 0x00000000U | ||
| 5167 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 5168 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
| 5169 | // .. .. ==> 0XF8006158[19:11] = 0x00000000U | ||
| 5170 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 5171 | // .. .. | ||
| 5172 | EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), | ||
| 5173 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c | ||
| 5174 | // .. .. ==> 0XF800615C[9:0] = 0x0000007CU | ||
| 5175 | // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU | ||
| 5176 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
| 5177 | // .. .. ==> 0XF800615C[10:10] = 0x00000000U | ||
| 5178 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 5179 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
| 5180 | // .. .. ==> 0XF800615C[19:11] = 0x00000000U | ||
| 5181 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 5182 | // .. .. | ||
| 5183 | EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU), | ||
| 5184 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x75 | ||
| 5185 | // .. .. ==> 0XF8006160[9:0] = 0x00000075U | ||
| 5186 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U | ||
| 5187 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
| 5188 | // .. .. ==> 0XF8006160[10:10] = 0x00000000U | ||
| 5189 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 5190 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
| 5191 | // .. .. ==> 0XF8006160[19:11] = 0x00000000U | ||
| 5192 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 5193 | // .. .. | ||
| 5194 | EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U), | ||
| 5195 | // .. .. reg_phy_fifo_we_slave_ratio = 0xe4 | ||
| 5196 | // .. .. ==> 0XF8006168[10:0] = 0x000000E4U | ||
| 5197 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U | ||
| 5198 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
| 5199 | // .. .. ==> 0XF8006168[11:11] = 0x00000000U | ||
| 5200 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 5201 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
| 5202 | // .. .. ==> 0XF8006168[20:12] = 0x00000000U | ||
| 5203 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
| 5204 | // .. .. | ||
| 5205 | EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U), | ||
| 5206 | // .. .. reg_phy_fifo_we_slave_ratio = 0xdf | ||
| 5207 | // .. .. ==> 0XF800616C[10:0] = 0x000000DFU | ||
| 5208 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU | ||
| 5209 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
| 5210 | // .. .. ==> 0XF800616C[11:11] = 0x00000000U | ||
| 5211 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 5212 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
| 5213 | // .. .. ==> 0XF800616C[20:12] = 0x00000000U | ||
| 5214 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
| 5215 | // .. .. | ||
| 5216 | EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU), | ||
| 5217 | // .. .. reg_phy_fifo_we_slave_ratio = 0xe0 | ||
| 5218 | // .. .. ==> 0XF8006170[10:0] = 0x000000E0U | ||
| 5219 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U | ||
| 5220 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
| 5221 | // .. .. ==> 0XF8006170[11:11] = 0x00000000U | ||
| 5222 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 5223 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
| 5224 | // .. .. ==> 0XF8006170[20:12] = 0x00000000U | ||
| 5225 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
| 5226 | // .. .. | ||
| 5227 | EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U), | ||
| 5228 | // .. .. reg_phy_fifo_we_slave_ratio = 0xe7 | ||
| 5229 | // .. .. ==> 0XF8006174[10:0] = 0x000000E7U | ||
| 5230 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U | ||
| 5231 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
| 5232 | // .. .. ==> 0XF8006174[11:11] = 0x00000000U | ||
| 5233 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 5234 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
| 5235 | // .. .. ==> 0XF8006174[20:12] = 0x00000000U | ||
| 5236 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
| 5237 | // .. .. | ||
| 5238 | EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U), | ||
| 5239 | // .. .. reg_phy_wr_data_slave_ratio = 0xb7 | ||
| 5240 | // .. .. ==> 0XF800617C[9:0] = 0x000000B7U | ||
| 5241 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U | ||
| 5242 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
| 5243 | // .. .. ==> 0XF800617C[10:10] = 0x00000000U | ||
| 5244 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 5245 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
| 5246 | // .. .. ==> 0XF800617C[19:11] = 0x00000000U | ||
| 5247 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 5248 | // .. .. | ||
| 5249 | EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U), | ||
| 5250 | // .. .. reg_phy_wr_data_slave_ratio = 0xbc | ||
| 5251 | // .. .. ==> 0XF8006180[9:0] = 0x000000BCU | ||
| 5252 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU | ||
| 5253 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
| 5254 | // .. .. ==> 0XF8006180[10:10] = 0x00000000U | ||
| 5255 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 5256 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
| 5257 | // .. .. ==> 0XF8006180[19:11] = 0x00000000U | ||
| 5258 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 5259 | // .. .. | ||
| 5260 | EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), | ||
| 5261 | // .. .. reg_phy_wr_data_slave_ratio = 0xbc | ||
| 5262 | // .. .. ==> 0XF8006184[9:0] = 0x000000BCU | ||
| 5263 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU | ||
| 5264 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
| 5265 | // .. .. ==> 0XF8006184[10:10] = 0x00000000U | ||
| 5266 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 5267 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
| 5268 | // .. .. ==> 0XF8006184[19:11] = 0x00000000U | ||
| 5269 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 5270 | // .. .. | ||
| 5271 | EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU), | ||
| 5272 | // .. .. reg_phy_wr_data_slave_ratio = 0xb5 | ||
| 5273 | // .. .. ==> 0XF8006188[9:0] = 0x000000B5U | ||
| 5274 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U | ||
| 5275 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
| 5276 | // .. .. ==> 0XF8006188[10:10] = 0x00000000U | ||
| 5277 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 5278 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
| 5279 | // .. .. ==> 0XF8006188[19:11] = 0x00000000U | ||
| 5280 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 5281 | // .. .. | ||
| 5282 | EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U), | ||
| 5283 | // .. .. reg_phy_loopback = 0x0 | ||
| 5284 | // .. .. ==> 0XF8006190[0:0] = 0x00000000U | ||
| 5285 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 5286 | // .. .. reg_phy_bl2 = 0x0 | ||
| 5287 | // .. .. ==> 0XF8006190[1:1] = 0x00000000U | ||
| 5288 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 5289 | // .. .. reg_phy_at_spd_atpg = 0x0 | ||
| 5290 | // .. .. ==> 0XF8006190[2:2] = 0x00000000U | ||
| 5291 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 5292 | // .. .. reg_phy_bist_enable = 0x0 | ||
| 5293 | // .. .. ==> 0XF8006190[3:3] = 0x00000000U | ||
| 5294 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 5295 | // .. .. reg_phy_bist_force_err = 0x0 | ||
| 5296 | // .. .. ==> 0XF8006190[4:4] = 0x00000000U | ||
| 5297 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 5298 | // .. .. reg_phy_bist_mode = 0x0 | ||
| 5299 | // .. .. ==> 0XF8006190[6:5] = 0x00000000U | ||
| 5300 | // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
| 5301 | // .. .. reg_phy_invert_clkout = 0x1 | ||
| 5302 | // .. .. ==> 0XF8006190[7:7] = 0x00000001U | ||
| 5303 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
| 5304 | // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 | ||
| 5305 | // .. .. ==> 0XF8006190[8:8] = 0x00000000U | ||
| 5306 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 5307 | // .. .. reg_phy_sel_logic = 0x0 | ||
| 5308 | // .. .. ==> 0XF8006190[9:9] = 0x00000000U | ||
| 5309 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
| 5310 | // .. .. reg_phy_ctrl_slave_ratio = 0x100 | ||
| 5311 | // .. .. ==> 0XF8006190[19:10] = 0x00000100U | ||
| 5312 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U | ||
| 5313 | // .. .. reg_phy_ctrl_slave_force = 0x0 | ||
| 5314 | // .. .. ==> 0XF8006190[20:20] = 0x00000000U | ||
| 5315 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
| 5316 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | ||
| 5317 | // .. .. ==> 0XF8006190[27:21] = 0x00000000U | ||
| 5318 | // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U | ||
| 5319 | // .. .. reg_phy_use_rank0_delays = 0x1 | ||
| 5320 | // .. .. ==> 0XF8006190[28:28] = 0x00000001U | ||
| 5321 | // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | ||
| 5322 | // .. .. reg_phy_lpddr = 0x0 | ||
| 5323 | // .. .. ==> 0XF8006190[29:29] = 0x00000000U | ||
| 5324 | // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U | ||
| 5325 | // .. .. reg_phy_cmd_latency = 0x0 | ||
| 5326 | // .. .. ==> 0XF8006190[30:30] = 0x00000000U | ||
| 5327 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | ||
| 5328 | // .. .. reg_phy_int_lpbk = 0x0 | ||
| 5329 | // .. .. ==> 0XF8006190[31:31] = 0x00000000U | ||
| 5330 | // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U | ||
| 5331 | // .. .. | ||
| 5332 | EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), | ||
| 5333 | // .. .. reg_phy_wr_rl_delay = 0x2 | ||
| 5334 | // .. .. ==> 0XF8006194[4:0] = 0x00000002U | ||
| 5335 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U | ||
| 5336 | // .. .. reg_phy_rd_rl_delay = 0x4 | ||
| 5337 | // .. .. ==> 0XF8006194[9:5] = 0x00000004U | ||
| 5338 | // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U | ||
| 5339 | // .. .. reg_phy_dll_lock_diff = 0xf | ||
| 5340 | // .. .. ==> 0XF8006194[13:10] = 0x0000000FU | ||
| 5341 | // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U | ||
| 5342 | // .. .. reg_phy_use_wr_level = 0x1 | ||
| 5343 | // .. .. ==> 0XF8006194[14:14] = 0x00000001U | ||
| 5344 | // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U | ||
| 5345 | // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 | ||
| 5346 | // .. .. ==> 0XF8006194[15:15] = 0x00000001U | ||
| 5347 | // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U | ||
| 5348 | // .. .. reg_phy_use_rd_data_eye_level = 0x1 | ||
| 5349 | // .. .. ==> 0XF8006194[16:16] = 0x00000001U | ||
| 5350 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | ||
| 5351 | // .. .. reg_phy_dis_calib_rst = 0x0 | ||
| 5352 | // .. .. ==> 0XF8006194[17:17] = 0x00000000U | ||
| 5353 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 5354 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | ||
| 5355 | // .. .. ==> 0XF8006194[19:18] = 0x00000000U | ||
| 5356 | // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U | ||
| 5357 | // .. .. | ||
| 5358 | EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), | ||
| 5359 | // .. .. reg_arb_page_addr_mask = 0x0 | ||
| 5360 | // .. .. ==> 0XF8006204[31:0] = 0x00000000U | ||
| 5361 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
| 5362 | // .. .. | ||
| 5363 | EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), | ||
| 5364 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
| 5365 | // .. .. ==> 0XF8006208[9:0] = 0x000003FFU | ||
| 5366 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 5367 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
| 5368 | // .. .. ==> 0XF8006208[16:16] = 0x00000000U | ||
| 5369 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 5370 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
| 5371 | // .. .. ==> 0XF8006208[17:17] = 0x00000000U | ||
| 5372 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 5373 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
| 5374 | // .. .. ==> 0XF8006208[18:18] = 0x00000000U | ||
| 5375 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 5376 | // .. .. reg_arb_dis_rmw_portn = 0x1 | ||
| 5377 | // .. .. ==> 0XF8006208[19:19] = 0x00000001U | ||
| 5378 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
| 5379 | // .. .. | ||
| 5380 | EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), | ||
| 5381 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
| 5382 | // .. .. ==> 0XF800620C[9:0] = 0x000003FFU | ||
| 5383 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 5384 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
| 5385 | // .. .. ==> 0XF800620C[16:16] = 0x00000000U | ||
| 5386 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 5387 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
| 5388 | // .. .. ==> 0XF800620C[17:17] = 0x00000000U | ||
| 5389 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 5390 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
| 5391 | // .. .. ==> 0XF800620C[18:18] = 0x00000000U | ||
| 5392 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 5393 | // .. .. reg_arb_dis_rmw_portn = 0x1 | ||
| 5394 | // .. .. ==> 0XF800620C[19:19] = 0x00000001U | ||
| 5395 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
| 5396 | // .. .. | ||
| 5397 | EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), | ||
| 5398 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
| 5399 | // .. .. ==> 0XF8006210[9:0] = 0x000003FFU | ||
| 5400 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 5401 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
| 5402 | // .. .. ==> 0XF8006210[16:16] = 0x00000000U | ||
| 5403 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 5404 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
| 5405 | // .. .. ==> 0XF8006210[17:17] = 0x00000000U | ||
| 5406 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 5407 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
| 5408 | // .. .. ==> 0XF8006210[18:18] = 0x00000000U | ||
| 5409 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 5410 | // .. .. reg_arb_dis_rmw_portn = 0x1 | ||
| 5411 | // .. .. ==> 0XF8006210[19:19] = 0x00000001U | ||
| 5412 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
| 5413 | // .. .. | ||
| 5414 | EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), | ||
| 5415 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
| 5416 | // .. .. ==> 0XF8006214[9:0] = 0x000003FFU | ||
| 5417 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 5418 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
| 5419 | // .. .. ==> 0XF8006214[16:16] = 0x00000000U | ||
| 5420 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 5421 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
| 5422 | // .. .. ==> 0XF8006214[17:17] = 0x00000000U | ||
| 5423 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 5424 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
| 5425 | // .. .. ==> 0XF8006214[18:18] = 0x00000000U | ||
| 5426 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 5427 | // .. .. reg_arb_dis_rmw_portn = 0x1 | ||
| 5428 | // .. .. ==> 0XF8006214[19:19] = 0x00000001U | ||
| 5429 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
| 5430 | // .. .. | ||
| 5431 | EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), | ||
| 5432 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
| 5433 | // .. .. ==> 0XF8006218[9:0] = 0x000003FFU | ||
| 5434 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 5435 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
| 5436 | // .. .. ==> 0XF8006218[16:16] = 0x00000000U | ||
| 5437 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 5438 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
| 5439 | // .. .. ==> 0XF8006218[17:17] = 0x00000000U | ||
| 5440 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 5441 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
| 5442 | // .. .. ==> 0XF8006218[18:18] = 0x00000000U | ||
| 5443 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 5444 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
| 5445 | // .. .. ==> 0XF8006218[19:19] = 0x00000000U | ||
| 5446 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
| 5447 | // .. .. | ||
| 5448 | EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), | ||
| 5449 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
| 5450 | // .. .. ==> 0XF800621C[9:0] = 0x000003FFU | ||
| 5451 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 5452 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
| 5453 | // .. .. ==> 0XF800621C[16:16] = 0x00000000U | ||
| 5454 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 5455 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
| 5456 | // .. .. ==> 0XF800621C[17:17] = 0x00000000U | ||
| 5457 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 5458 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
| 5459 | // .. .. ==> 0XF800621C[18:18] = 0x00000000U | ||
| 5460 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 5461 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
| 5462 | // .. .. ==> 0XF800621C[19:19] = 0x00000000U | ||
| 5463 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
| 5464 | // .. .. | ||
| 5465 | EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), | ||
| 5466 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
| 5467 | // .. .. ==> 0XF8006220[9:0] = 0x000003FFU | ||
| 5468 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 5469 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
| 5470 | // .. .. ==> 0XF8006220[16:16] = 0x00000000U | ||
| 5471 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 5472 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
| 5473 | // .. .. ==> 0XF8006220[17:17] = 0x00000000U | ||
| 5474 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 5475 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
| 5476 | // .. .. ==> 0XF8006220[18:18] = 0x00000000U | ||
| 5477 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 5478 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
| 5479 | // .. .. ==> 0XF8006220[19:19] = 0x00000000U | ||
| 5480 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
| 5481 | // .. .. | ||
| 5482 | EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), | ||
| 5483 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
| 5484 | // .. .. ==> 0XF8006224[9:0] = 0x000003FFU | ||
| 5485 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 5486 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
| 5487 | // .. .. ==> 0XF8006224[16:16] = 0x00000000U | ||
| 5488 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 5489 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
| 5490 | // .. .. ==> 0XF8006224[17:17] = 0x00000000U | ||
| 5491 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 5492 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
| 5493 | // .. .. ==> 0XF8006224[18:18] = 0x00000000U | ||
| 5494 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 5495 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
| 5496 | // .. .. ==> 0XF8006224[19:19] = 0x00000000U | ||
| 5497 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
| 5498 | // .. .. | ||
| 5499 | EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), | ||
| 5500 | // .. .. reg_ddrc_lpddr2 = 0x0 | ||
| 5501 | // .. .. ==> 0XF80062A8[0:0] = 0x00000000U | ||
| 5502 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 5503 | // .. .. reg_ddrc_per_bank_refresh = 0x0 | ||
| 5504 | // .. .. ==> 0XF80062A8[1:1] = 0x00000000U | ||
| 5505 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 5506 | // .. .. reg_ddrc_derate_enable = 0x0 | ||
| 5507 | // .. .. ==> 0XF80062A8[2:2] = 0x00000000U | ||
| 5508 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 5509 | // .. .. reg_ddrc_mr4_margin = 0x0 | ||
| 5510 | // .. .. ==> 0XF80062A8[11:4] = 0x00000000U | ||
| 5511 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U | ||
| 5512 | // .. .. | ||
| 5513 | EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), | ||
| 5514 | // .. .. reg_ddrc_mr4_read_interval = 0x0 | ||
| 5515 | // .. .. ==> 0XF80062AC[31:0] = 0x00000000U | ||
| 5516 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
| 5517 | // .. .. | ||
| 5518 | EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), | ||
| 5519 | // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 | ||
| 5520 | // .. .. ==> 0XF80062B0[3:0] = 0x00000005U | ||
| 5521 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U | ||
| 5522 | // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 | ||
| 5523 | // .. .. ==> 0XF80062B0[11:4] = 0x00000012U | ||
| 5524 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U | ||
| 5525 | // .. .. reg_ddrc_t_mrw = 0x5 | ||
| 5526 | // .. .. ==> 0XF80062B0[21:12] = 0x00000005U | ||
| 5527 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U | ||
| 5528 | // .. .. | ||
| 5529 | EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), | ||
| 5530 | // .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 | ||
| 5531 | // .. .. ==> 0XF80062B4[7:0] = 0x000000A6U | ||
| 5532 | // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U | ||
| 5533 | // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 | ||
| 5534 | // .. .. ==> 0XF80062B4[17:8] = 0x00000012U | ||
| 5535 | // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U | ||
| 5536 | // .. .. | ||
| 5537 | EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U), | ||
| 5538 | // .. .. START: POLL ON DCI STATUS | ||
| 5539 | // .. .. DONE = 1 | ||
| 5540 | // .. .. ==> 0XF8000B74[13:13] = 0x00000001U | ||
| 5541 | // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 5542 | // .. .. | ||
| 5543 | EMIT_MASKPOLL(0XF8000B74, 0x00002000U), | ||
| 5544 | // .. .. FINISH: POLL ON DCI STATUS | ||
| 5545 | // .. .. START: UNLOCK DDR | ||
| 5546 | // .. .. reg_ddrc_soft_rstb = 0x1 | ||
| 5547 | // .. .. ==> 0XF8006000[0:0] = 0x00000001U | ||
| 5548 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 5549 | // .. .. reg_ddrc_powerdown_en = 0x0 | ||
| 5550 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | ||
| 5551 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 5552 | // .. .. reg_ddrc_data_bus_width = 0x0 | ||
| 5553 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | ||
| 5554 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | ||
| 5555 | // .. .. reg_ddrc_burst8_refresh = 0x0 | ||
| 5556 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | ||
| 5557 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
| 5558 | // .. .. reg_ddrc_rdwr_idle_gap = 1 | ||
| 5559 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | ||
| 5560 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | ||
| 5561 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | ||
| 5562 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | ||
| 5563 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
| 5564 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | ||
| 5565 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | ||
| 5566 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
| 5567 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | ||
| 5568 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | ||
| 5569 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 5570 | // .. .. | ||
| 5571 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), | ||
| 5572 | // .. .. FINISH: UNLOCK DDR | ||
| 5573 | // .. .. START: CHECK DDR STATUS | ||
| 5574 | // .. .. ddrc_reg_operating_mode = 1 | ||
| 5575 | // .. .. ==> 0XF8006054[2:0] = 0x00000001U | ||
| 5576 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U | ||
| 5577 | // .. .. | ||
| 5578 | EMIT_MASKPOLL(0XF8006054, 0x00000007U), | ||
| 5579 | // .. .. FINISH: CHECK DDR STATUS | ||
| 5580 | // .. FINISH: DDR INITIALIZATION | ||
| 5581 | // FINISH: top | ||
| 5582 | // | ||
| 5583 | EMIT_EXIT(), | ||
| 5584 | |||
| 5585 | // | ||
| 5586 | }; | ||
| 5587 | |||
| 5588 | unsigned long ps7_mio_init_data_2_0[] = { | ||
| 5589 | // START: top | ||
| 5590 | // .. START: SLCR SETTINGS | ||
| 5591 | // .. UNLOCK_KEY = 0XDF0D | ||
| 5592 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
| 5593 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
| 5594 | // .. | ||
| 5595 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
| 5596 | // .. FINISH: SLCR SETTINGS | ||
| 5597 | // .. START: OCM REMAPPING | ||
| 5598 | // .. VREF_EN = 0x1 | ||
| 5599 | // .. ==> 0XF8000B00[0:0] = 0x00000001U | ||
| 5600 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 5601 | // .. VREF_PULLUP_EN = 0x0 | ||
| 5602 | // .. ==> 0XF8000B00[1:1] = 0x00000000U | ||
| 5603 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 5604 | // .. CLK_PULLUP_EN = 0x0 | ||
| 5605 | // .. ==> 0XF8000B00[8:8] = 0x00000000U | ||
| 5606 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 5607 | // .. SRSTN_PULLUP_EN = 0x0 | ||
| 5608 | // .. ==> 0XF8000B00[9:9] = 0x00000000U | ||
| 5609 | // .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
| 5610 | // .. | ||
| 5611 | EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), | ||
| 5612 | // .. FINISH: OCM REMAPPING | ||
| 5613 | // .. START: DDRIOB SETTINGS | ||
| 5614 | // .. INP_POWER = 0x0 | ||
| 5615 | // .. ==> 0XF8000B40[0:0] = 0x00000000U | ||
| 5616 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 5617 | // .. INP_TYPE = 0x0 | ||
| 5618 | // .. ==> 0XF8000B40[2:1] = 0x00000000U | ||
| 5619 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
| 5620 | // .. DCI_UPDATE = 0x0 | ||
| 5621 | // .. ==> 0XF8000B40[3:3] = 0x00000000U | ||
| 5622 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 5623 | // .. TERM_EN = 0x0 | ||
| 5624 | // .. ==> 0XF8000B40[4:4] = 0x00000000U | ||
| 5625 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 5626 | // .. DCR_TYPE = 0x0 | ||
| 5627 | // .. ==> 0XF8000B40[6:5] = 0x00000000U | ||
| 5628 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
| 5629 | // .. IBUF_DISABLE_MODE = 0x0 | ||
| 5630 | // .. ==> 0XF8000B40[7:7] = 0x00000000U | ||
| 5631 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 5632 | // .. TERM_DISABLE_MODE = 0x0 | ||
| 5633 | // .. ==> 0XF8000B40[8:8] = 0x00000000U | ||
| 5634 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 5635 | // .. OUTPUT_EN = 0x3 | ||
| 5636 | // .. ==> 0XF8000B40[10:9] = 0x00000003U | ||
| 5637 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 5638 | // .. PULLUP_EN = 0x0 | ||
| 5639 | // .. ==> 0XF8000B40[11:11] = 0x00000000U | ||
| 5640 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 5641 | // .. | ||
| 5642 | EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), | ||
| 5643 | // .. INP_POWER = 0x0 | ||
| 5644 | // .. ==> 0XF8000B44[0:0] = 0x00000000U | ||
| 5645 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 5646 | // .. INP_TYPE = 0x0 | ||
| 5647 | // .. ==> 0XF8000B44[2:1] = 0x00000000U | ||
| 5648 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
| 5649 | // .. DCI_UPDATE = 0x0 | ||
| 5650 | // .. ==> 0XF8000B44[3:3] = 0x00000000U | ||
| 5651 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 5652 | // .. TERM_EN = 0x0 | ||
| 5653 | // .. ==> 0XF8000B44[4:4] = 0x00000000U | ||
| 5654 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 5655 | // .. DCR_TYPE = 0x0 | ||
| 5656 | // .. ==> 0XF8000B44[6:5] = 0x00000000U | ||
| 5657 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
| 5658 | // .. IBUF_DISABLE_MODE = 0x0 | ||
| 5659 | // .. ==> 0XF8000B44[7:7] = 0x00000000U | ||
| 5660 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 5661 | // .. TERM_DISABLE_MODE = 0x0 | ||
| 5662 | // .. ==> 0XF8000B44[8:8] = 0x00000000U | ||
| 5663 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 5664 | // .. OUTPUT_EN = 0x3 | ||
| 5665 | // .. ==> 0XF8000B44[10:9] = 0x00000003U | ||
| 5666 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 5667 | // .. PULLUP_EN = 0x0 | ||
| 5668 | // .. ==> 0XF8000B44[11:11] = 0x00000000U | ||
| 5669 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 5670 | // .. | ||
| 5671 | EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), | ||
| 5672 | // .. INP_POWER = 0x0 | ||
| 5673 | // .. ==> 0XF8000B48[0:0] = 0x00000000U | ||
| 5674 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 5675 | // .. INP_TYPE = 0x1 | ||
| 5676 | // .. ==> 0XF8000B48[2:1] = 0x00000001U | ||
| 5677 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | ||
| 5678 | // .. DCI_UPDATE = 0x0 | ||
| 5679 | // .. ==> 0XF8000B48[3:3] = 0x00000000U | ||
| 5680 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 5681 | // .. TERM_EN = 0x1 | ||
| 5682 | // .. ==> 0XF8000B48[4:4] = 0x00000001U | ||
| 5683 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 5684 | // .. DCR_TYPE = 0x3 | ||
| 5685 | // .. ==> 0XF8000B48[6:5] = 0x00000003U | ||
| 5686 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
| 5687 | // .. IBUF_DISABLE_MODE = 0 | ||
| 5688 | // .. ==> 0XF8000B48[7:7] = 0x00000000U | ||
| 5689 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 5690 | // .. TERM_DISABLE_MODE = 0 | ||
| 5691 | // .. ==> 0XF8000B48[8:8] = 0x00000000U | ||
| 5692 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 5693 | // .. OUTPUT_EN = 0x3 | ||
| 5694 | // .. ==> 0XF8000B48[10:9] = 0x00000003U | ||
| 5695 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 5696 | // .. PULLUP_EN = 0x0 | ||
| 5697 | // .. ==> 0XF8000B48[11:11] = 0x00000000U | ||
| 5698 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 5699 | // .. | ||
| 5700 | EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), | ||
| 5701 | // .. INP_POWER = 0x0 | ||
| 5702 | // .. ==> 0XF8000B4C[0:0] = 0x00000000U | ||
| 5703 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 5704 | // .. INP_TYPE = 0x1 | ||
| 5705 | // .. ==> 0XF8000B4C[2:1] = 0x00000001U | ||
| 5706 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | ||
| 5707 | // .. DCI_UPDATE = 0x0 | ||
| 5708 | // .. ==> 0XF8000B4C[3:3] = 0x00000000U | ||
| 5709 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 5710 | // .. TERM_EN = 0x1 | ||
| 5711 | // .. ==> 0XF8000B4C[4:4] = 0x00000001U | ||
| 5712 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 5713 | // .. DCR_TYPE = 0x3 | ||
| 5714 | // .. ==> 0XF8000B4C[6:5] = 0x00000003U | ||
| 5715 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
| 5716 | // .. IBUF_DISABLE_MODE = 0 | ||
| 5717 | // .. ==> 0XF8000B4C[7:7] = 0x00000000U | ||
| 5718 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 5719 | // .. TERM_DISABLE_MODE = 0 | ||
| 5720 | // .. ==> 0XF8000B4C[8:8] = 0x00000000U | ||
| 5721 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 5722 | // .. OUTPUT_EN = 0x3 | ||
| 5723 | // .. ==> 0XF8000B4C[10:9] = 0x00000003U | ||
| 5724 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 5725 | // .. PULLUP_EN = 0x0 | ||
| 5726 | // .. ==> 0XF8000B4C[11:11] = 0x00000000U | ||
| 5727 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 5728 | // .. | ||
| 5729 | EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), | ||
| 5730 | // .. INP_POWER = 0x0 | ||
| 5731 | // .. ==> 0XF8000B50[0:0] = 0x00000000U | ||
| 5732 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 5733 | // .. INP_TYPE = 0x2 | ||
| 5734 | // .. ==> 0XF8000B50[2:1] = 0x00000002U | ||
| 5735 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | ||
| 5736 | // .. DCI_UPDATE = 0x0 | ||
| 5737 | // .. ==> 0XF8000B50[3:3] = 0x00000000U | ||
| 5738 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 5739 | // .. TERM_EN = 0x1 | ||
| 5740 | // .. ==> 0XF8000B50[4:4] = 0x00000001U | ||
| 5741 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 5742 | // .. DCR_TYPE = 0x3 | ||
| 5743 | // .. ==> 0XF8000B50[6:5] = 0x00000003U | ||
| 5744 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
| 5745 | // .. IBUF_DISABLE_MODE = 0 | ||
| 5746 | // .. ==> 0XF8000B50[7:7] = 0x00000000U | ||
| 5747 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 5748 | // .. TERM_DISABLE_MODE = 0 | ||
| 5749 | // .. ==> 0XF8000B50[8:8] = 0x00000000U | ||
| 5750 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 5751 | // .. OUTPUT_EN = 0x3 | ||
| 5752 | // .. ==> 0XF8000B50[10:9] = 0x00000003U | ||
| 5753 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 5754 | // .. PULLUP_EN = 0x0 | ||
| 5755 | // .. ==> 0XF8000B50[11:11] = 0x00000000U | ||
| 5756 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 5757 | // .. | ||
| 5758 | EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), | ||
| 5759 | // .. INP_POWER = 0x0 | ||
| 5760 | // .. ==> 0XF8000B54[0:0] = 0x00000000U | ||
| 5761 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 5762 | // .. INP_TYPE = 0x2 | ||
| 5763 | // .. ==> 0XF8000B54[2:1] = 0x00000002U | ||
| 5764 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | ||
| 5765 | // .. DCI_UPDATE = 0x0 | ||
| 5766 | // .. ==> 0XF8000B54[3:3] = 0x00000000U | ||
| 5767 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 5768 | // .. TERM_EN = 0x1 | ||
| 5769 | // .. ==> 0XF8000B54[4:4] = 0x00000001U | ||
| 5770 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 5771 | // .. DCR_TYPE = 0x3 | ||
| 5772 | // .. ==> 0XF8000B54[6:5] = 0x00000003U | ||
| 5773 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
| 5774 | // .. IBUF_DISABLE_MODE = 0 | ||
| 5775 | // .. ==> 0XF8000B54[7:7] = 0x00000000U | ||
| 5776 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 5777 | // .. TERM_DISABLE_MODE = 0 | ||
| 5778 | // .. ==> 0XF8000B54[8:8] = 0x00000000U | ||
| 5779 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 5780 | // .. OUTPUT_EN = 0x3 | ||
| 5781 | // .. ==> 0XF8000B54[10:9] = 0x00000003U | ||
| 5782 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 5783 | // .. PULLUP_EN = 0x0 | ||
| 5784 | // .. ==> 0XF8000B54[11:11] = 0x00000000U | ||
| 5785 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 5786 | // .. | ||
| 5787 | EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), | ||
| 5788 | // .. INP_POWER = 0x0 | ||
| 5789 | // .. ==> 0XF8000B58[0:0] = 0x00000000U | ||
| 5790 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 5791 | // .. INP_TYPE = 0x0 | ||
| 5792 | // .. ==> 0XF8000B58[2:1] = 0x00000000U | ||
| 5793 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
| 5794 | // .. DCI_UPDATE = 0x0 | ||
| 5795 | // .. ==> 0XF8000B58[3:3] = 0x00000000U | ||
| 5796 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 5797 | // .. TERM_EN = 0x0 | ||
| 5798 | // .. ==> 0XF8000B58[4:4] = 0x00000000U | ||
| 5799 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 5800 | // .. DCR_TYPE = 0x0 | ||
| 5801 | // .. ==> 0XF8000B58[6:5] = 0x00000000U | ||
| 5802 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
| 5803 | // .. IBUF_DISABLE_MODE = 0x0 | ||
| 5804 | // .. ==> 0XF8000B58[7:7] = 0x00000000U | ||
| 5805 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 5806 | // .. TERM_DISABLE_MODE = 0x0 | ||
| 5807 | // .. ==> 0XF8000B58[8:8] = 0x00000000U | ||
| 5808 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 5809 | // .. OUTPUT_EN = 0x3 | ||
| 5810 | // .. ==> 0XF8000B58[10:9] = 0x00000003U | ||
| 5811 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 5812 | // .. PULLUP_EN = 0x0 | ||
| 5813 | // .. ==> 0XF8000B58[11:11] = 0x00000000U | ||
| 5814 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 5815 | // .. | ||
| 5816 | EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), | ||
| 5817 | // .. DRIVE_P = 0x1c | ||
| 5818 | // .. ==> 0XF8000B5C[6:0] = 0x0000001CU | ||
| 5819 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
| 5820 | // .. DRIVE_N = 0xc | ||
| 5821 | // .. ==> 0XF8000B5C[13:7] = 0x0000000CU | ||
| 5822 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
| 5823 | // .. SLEW_P = 0x3 | ||
| 5824 | // .. ==> 0XF8000B5C[18:14] = 0x00000003U | ||
| 5825 | // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U | ||
| 5826 | // .. SLEW_N = 0x3 | ||
| 5827 | // .. ==> 0XF8000B5C[23:19] = 0x00000003U | ||
| 5828 | // .. ==> MASK : 0x00F80000U VAL : 0x00180000U | ||
| 5829 | // .. GTL = 0x0 | ||
| 5830 | // .. ==> 0XF8000B5C[26:24] = 0x00000000U | ||
| 5831 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
| 5832 | // .. RTERM = 0x0 | ||
| 5833 | // .. ==> 0XF8000B5C[31:27] = 0x00000000U | ||
| 5834 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
| 5835 | // .. | ||
| 5836 | EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), | ||
| 5837 | // .. DRIVE_P = 0x1c | ||
| 5838 | // .. ==> 0XF8000B60[6:0] = 0x0000001CU | ||
| 5839 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
| 5840 | // .. DRIVE_N = 0xc | ||
| 5841 | // .. ==> 0XF8000B60[13:7] = 0x0000000CU | ||
| 5842 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
| 5843 | // .. SLEW_P = 0x6 | ||
| 5844 | // .. ==> 0XF8000B60[18:14] = 0x00000006U | ||
| 5845 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
| 5846 | // .. SLEW_N = 0x1f | ||
| 5847 | // .. ==> 0XF8000B60[23:19] = 0x0000001FU | ||
| 5848 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
| 5849 | // .. GTL = 0x0 | ||
| 5850 | // .. ==> 0XF8000B60[26:24] = 0x00000000U | ||
| 5851 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
| 5852 | // .. RTERM = 0x0 | ||
| 5853 | // .. ==> 0XF8000B60[31:27] = 0x00000000U | ||
| 5854 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
| 5855 | // .. | ||
| 5856 | EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), | ||
| 5857 | // .. DRIVE_P = 0x1c | ||
| 5858 | // .. ==> 0XF8000B64[6:0] = 0x0000001CU | ||
| 5859 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
| 5860 | // .. DRIVE_N = 0xc | ||
| 5861 | // .. ==> 0XF8000B64[13:7] = 0x0000000CU | ||
| 5862 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
| 5863 | // .. SLEW_P = 0x6 | ||
| 5864 | // .. ==> 0XF8000B64[18:14] = 0x00000006U | ||
| 5865 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
| 5866 | // .. SLEW_N = 0x1f | ||
| 5867 | // .. ==> 0XF8000B64[23:19] = 0x0000001FU | ||
| 5868 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
| 5869 | // .. GTL = 0x0 | ||
| 5870 | // .. ==> 0XF8000B64[26:24] = 0x00000000U | ||
| 5871 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
| 5872 | // .. RTERM = 0x0 | ||
| 5873 | // .. ==> 0XF8000B64[31:27] = 0x00000000U | ||
| 5874 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
| 5875 | // .. | ||
| 5876 | EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), | ||
| 5877 | // .. DRIVE_P = 0x1c | ||
| 5878 | // .. ==> 0XF8000B68[6:0] = 0x0000001CU | ||
| 5879 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
| 5880 | // .. DRIVE_N = 0xc | ||
| 5881 | // .. ==> 0XF8000B68[13:7] = 0x0000000CU | ||
| 5882 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
| 5883 | // .. SLEW_P = 0x6 | ||
| 5884 | // .. ==> 0XF8000B68[18:14] = 0x00000006U | ||
| 5885 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
| 5886 | // .. SLEW_N = 0x1f | ||
| 5887 | // .. ==> 0XF8000B68[23:19] = 0x0000001FU | ||
| 5888 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
| 5889 | // .. GTL = 0x0 | ||
| 5890 | // .. ==> 0XF8000B68[26:24] = 0x00000000U | ||
| 5891 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
| 5892 | // .. RTERM = 0x0 | ||
| 5893 | // .. ==> 0XF8000B68[31:27] = 0x00000000U | ||
| 5894 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
| 5895 | // .. | ||
| 5896 | EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), | ||
| 5897 | // .. VREF_INT_EN = 0x0 | ||
| 5898 | // .. ==> 0XF8000B6C[0:0] = 0x00000000U | ||
| 5899 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 5900 | // .. VREF_SEL = 0x0 | ||
| 5901 | // .. ==> 0XF8000B6C[4:1] = 0x00000000U | ||
| 5902 | // .. ==> MASK : 0x0000001EU VAL : 0x00000000U | ||
| 5903 | // .. VREF_EXT_EN = 0x3 | ||
| 5904 | // .. ==> 0XF8000B6C[6:5] = 0x00000003U | ||
| 5905 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
| 5906 | // .. VREF_PULLUP_EN = 0x0 | ||
| 5907 | // .. ==> 0XF8000B6C[8:7] = 0x00000000U | ||
| 5908 | // .. ==> MASK : 0x00000180U VAL : 0x00000000U | ||
| 5909 | // .. REFIO_EN = 0x1 | ||
| 5910 | // .. ==> 0XF8000B6C[9:9] = 0x00000001U | ||
| 5911 | // .. ==> MASK : 0x00000200U VAL : 0x00000200U | ||
| 5912 | // .. REFIO_TEST = 0x0 | ||
| 5913 | // .. ==> 0XF8000B6C[11:10] = 0x00000000U | ||
| 5914 | // .. ==> MASK : 0x00000C00U VAL : 0x00000000U | ||
| 5915 | // .. REFIO_PULLUP_EN = 0x0 | ||
| 5916 | // .. ==> 0XF8000B6C[12:12] = 0x00000000U | ||
| 5917 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 5918 | // .. DRST_B_PULLUP_EN = 0x0 | ||
| 5919 | // .. ==> 0XF8000B6C[13:13] = 0x00000000U | ||
| 5920 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 5921 | // .. CKE_PULLUP_EN = 0x0 | ||
| 5922 | // .. ==> 0XF8000B6C[14:14] = 0x00000000U | ||
| 5923 | // .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
| 5924 | // .. | ||
| 5925 | EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), | ||
| 5926 | // .. .. START: ASSERT RESET | ||
| 5927 | // .. .. RESET = 1 | ||
| 5928 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | ||
| 5929 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 5930 | // .. .. VRN_OUT = 0x1 | ||
| 5931 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | ||
| 5932 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | ||
| 5933 | // .. .. | ||
| 5934 | EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), | ||
| 5935 | // .. .. FINISH: ASSERT RESET | ||
| 5936 | // .. .. START: DEASSERT RESET | ||
| 5937 | // .. .. RESET = 0 | ||
| 5938 | // .. .. ==> 0XF8000B70[0:0] = 0x00000000U | ||
| 5939 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 5940 | // .. .. VRN_OUT = 0x1 | ||
| 5941 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | ||
| 5942 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | ||
| 5943 | // .. .. | ||
| 5944 | EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), | ||
| 5945 | // .. .. FINISH: DEASSERT RESET | ||
| 5946 | // .. .. RESET = 0x1 | ||
| 5947 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | ||
| 5948 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 5949 | // .. .. ENABLE = 0x1 | ||
| 5950 | // .. .. ==> 0XF8000B70[1:1] = 0x00000001U | ||
| 5951 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 5952 | // .. .. VRP_TRI = 0x0 | ||
| 5953 | // .. .. ==> 0XF8000B70[2:2] = 0x00000000U | ||
| 5954 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 5955 | // .. .. VRN_TRI = 0x0 | ||
| 5956 | // .. .. ==> 0XF8000B70[3:3] = 0x00000000U | ||
| 5957 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 5958 | // .. .. VRP_OUT = 0x0 | ||
| 5959 | // .. .. ==> 0XF8000B70[4:4] = 0x00000000U | ||
| 5960 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 5961 | // .. .. VRN_OUT = 0x1 | ||
| 5962 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | ||
| 5963 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | ||
| 5964 | // .. .. NREF_OPT1 = 0x0 | ||
| 5965 | // .. .. ==> 0XF8000B70[7:6] = 0x00000000U | ||
| 5966 | // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U | ||
| 5967 | // .. .. NREF_OPT2 = 0x0 | ||
| 5968 | // .. .. ==> 0XF8000B70[10:8] = 0x00000000U | ||
| 5969 | // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U | ||
| 5970 | // .. .. NREF_OPT4 = 0x1 | ||
| 5971 | // .. .. ==> 0XF8000B70[13:11] = 0x00000001U | ||
| 5972 | // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U | ||
| 5973 | // .. .. PREF_OPT1 = 0x0 | ||
| 5974 | // .. .. ==> 0XF8000B70[16:14] = 0x00000000U | ||
| 5975 | // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U | ||
| 5976 | // .. .. PREF_OPT2 = 0x0 | ||
| 5977 | // .. .. ==> 0XF8000B70[19:17] = 0x00000000U | ||
| 5978 | // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U | ||
| 5979 | // .. .. UPDATE_CONTROL = 0x0 | ||
| 5980 | // .. .. ==> 0XF8000B70[20:20] = 0x00000000U | ||
| 5981 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
| 5982 | // .. .. INIT_COMPLETE = 0x0 | ||
| 5983 | // .. .. ==> 0XF8000B70[21:21] = 0x00000000U | ||
| 5984 | // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U | ||
| 5985 | // .. .. TST_CLK = 0x0 | ||
| 5986 | // .. .. ==> 0XF8000B70[22:22] = 0x00000000U | ||
| 5987 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
| 5988 | // .. .. TST_HLN = 0x0 | ||
| 5989 | // .. .. ==> 0XF8000B70[23:23] = 0x00000000U | ||
| 5990 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
| 5991 | // .. .. TST_HLP = 0x0 | ||
| 5992 | // .. .. ==> 0XF8000B70[24:24] = 0x00000000U | ||
| 5993 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
| 5994 | // .. .. TST_RST = 0x0 | ||
| 5995 | // .. .. ==> 0XF8000B70[25:25] = 0x00000000U | ||
| 5996 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
| 5997 | // .. .. INT_DCI_EN = 0x0 | ||
| 5998 | // .. .. ==> 0XF8000B70[26:26] = 0x00000000U | ||
| 5999 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | ||
| 6000 | // .. .. | ||
| 6001 | EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), | ||
| 6002 | // .. FINISH: DDRIOB SETTINGS | ||
| 6003 | // .. START: MIO PROGRAMMING | ||
| 6004 | // .. TRI_ENABLE = 0 | ||
| 6005 | // .. ==> 0XF8000704[0:0] = 0x00000000U | ||
| 6006 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6007 | // .. L0_SEL = 1 | ||
| 6008 | // .. ==> 0XF8000704[1:1] = 0x00000001U | ||
| 6009 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6010 | // .. L1_SEL = 0 | ||
| 6011 | // .. ==> 0XF8000704[2:2] = 0x00000000U | ||
| 6012 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6013 | // .. L2_SEL = 0 | ||
| 6014 | // .. ==> 0XF8000704[4:3] = 0x00000000U | ||
| 6015 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6016 | // .. L3_SEL = 0 | ||
| 6017 | // .. ==> 0XF8000704[7:5] = 0x00000000U | ||
| 6018 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6019 | // .. Speed = 1 | ||
| 6020 | // .. ==> 0XF8000704[8:8] = 0x00000001U | ||
| 6021 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6022 | // .. IO_Type = 3 | ||
| 6023 | // .. ==> 0XF8000704[11:9] = 0x00000003U | ||
| 6024 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 6025 | // .. PULLUP = 0 | ||
| 6026 | // .. ==> 0XF8000704[12:12] = 0x00000000U | ||
| 6027 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6028 | // .. DisableRcvr = 0 | ||
| 6029 | // .. ==> 0XF8000704[13:13] = 0x00000000U | ||
| 6030 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6031 | // .. | ||
| 6032 | EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U), | ||
| 6033 | // .. TRI_ENABLE = 0 | ||
| 6034 | // .. ==> 0XF8000708[0:0] = 0x00000000U | ||
| 6035 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6036 | // .. L0_SEL = 1 | ||
| 6037 | // .. ==> 0XF8000708[1:1] = 0x00000001U | ||
| 6038 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6039 | // .. L1_SEL = 0 | ||
| 6040 | // .. ==> 0XF8000708[2:2] = 0x00000000U | ||
| 6041 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6042 | // .. L2_SEL = 0 | ||
| 6043 | // .. ==> 0XF8000708[4:3] = 0x00000000U | ||
| 6044 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6045 | // .. L3_SEL = 0 | ||
| 6046 | // .. ==> 0XF8000708[7:5] = 0x00000000U | ||
| 6047 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6048 | // .. Speed = 1 | ||
| 6049 | // .. ==> 0XF8000708[8:8] = 0x00000001U | ||
| 6050 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6051 | // .. IO_Type = 3 | ||
| 6052 | // .. ==> 0XF8000708[11:9] = 0x00000003U | ||
| 6053 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 6054 | // .. PULLUP = 0 | ||
| 6055 | // .. ==> 0XF8000708[12:12] = 0x00000000U | ||
| 6056 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6057 | // .. DisableRcvr = 0 | ||
| 6058 | // .. ==> 0XF8000708[13:13] = 0x00000000U | ||
| 6059 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6060 | // .. | ||
| 6061 | EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U), | ||
| 6062 | // .. TRI_ENABLE = 0 | ||
| 6063 | // .. ==> 0XF800070C[0:0] = 0x00000000U | ||
| 6064 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6065 | // .. L0_SEL = 1 | ||
| 6066 | // .. ==> 0XF800070C[1:1] = 0x00000001U | ||
| 6067 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6068 | // .. L1_SEL = 0 | ||
| 6069 | // .. ==> 0XF800070C[2:2] = 0x00000000U | ||
| 6070 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6071 | // .. L2_SEL = 0 | ||
| 6072 | // .. ==> 0XF800070C[4:3] = 0x00000000U | ||
| 6073 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6074 | // .. L3_SEL = 0 | ||
| 6075 | // .. ==> 0XF800070C[7:5] = 0x00000000U | ||
| 6076 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6077 | // .. Speed = 1 | ||
| 6078 | // .. ==> 0XF800070C[8:8] = 0x00000001U | ||
| 6079 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6080 | // .. IO_Type = 3 | ||
| 6081 | // .. ==> 0XF800070C[11:9] = 0x00000003U | ||
| 6082 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 6083 | // .. PULLUP = 0 | ||
| 6084 | // .. ==> 0XF800070C[12:12] = 0x00000000U | ||
| 6085 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6086 | // .. DisableRcvr = 0 | ||
| 6087 | // .. ==> 0XF800070C[13:13] = 0x00000000U | ||
| 6088 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6089 | // .. | ||
| 6090 | EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U), | ||
| 6091 | // .. TRI_ENABLE = 0 | ||
| 6092 | // .. ==> 0XF8000710[0:0] = 0x00000000U | ||
| 6093 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6094 | // .. L0_SEL = 1 | ||
| 6095 | // .. ==> 0XF8000710[1:1] = 0x00000001U | ||
| 6096 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6097 | // .. L1_SEL = 0 | ||
| 6098 | // .. ==> 0XF8000710[2:2] = 0x00000000U | ||
| 6099 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6100 | // .. L2_SEL = 0 | ||
| 6101 | // .. ==> 0XF8000710[4:3] = 0x00000000U | ||
| 6102 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6103 | // .. L3_SEL = 0 | ||
| 6104 | // .. ==> 0XF8000710[7:5] = 0x00000000U | ||
| 6105 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6106 | // .. Speed = 1 | ||
| 6107 | // .. ==> 0XF8000710[8:8] = 0x00000001U | ||
| 6108 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6109 | // .. IO_Type = 3 | ||
| 6110 | // .. ==> 0XF8000710[11:9] = 0x00000003U | ||
| 6111 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 6112 | // .. PULLUP = 0 | ||
| 6113 | // .. ==> 0XF8000710[12:12] = 0x00000000U | ||
| 6114 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6115 | // .. DisableRcvr = 0 | ||
| 6116 | // .. ==> 0XF8000710[13:13] = 0x00000000U | ||
| 6117 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6118 | // .. | ||
| 6119 | EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U), | ||
| 6120 | // .. TRI_ENABLE = 0 | ||
| 6121 | // .. ==> 0XF8000714[0:0] = 0x00000000U | ||
| 6122 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6123 | // .. L0_SEL = 1 | ||
| 6124 | // .. ==> 0XF8000714[1:1] = 0x00000001U | ||
| 6125 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6126 | // .. L1_SEL = 0 | ||
| 6127 | // .. ==> 0XF8000714[2:2] = 0x00000000U | ||
| 6128 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6129 | // .. L2_SEL = 0 | ||
| 6130 | // .. ==> 0XF8000714[4:3] = 0x00000000U | ||
| 6131 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6132 | // .. L3_SEL = 0 | ||
| 6133 | // .. ==> 0XF8000714[7:5] = 0x00000000U | ||
| 6134 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6135 | // .. Speed = 1 | ||
| 6136 | // .. ==> 0XF8000714[8:8] = 0x00000001U | ||
| 6137 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6138 | // .. IO_Type = 3 | ||
| 6139 | // .. ==> 0XF8000714[11:9] = 0x00000003U | ||
| 6140 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 6141 | // .. PULLUP = 0 | ||
| 6142 | // .. ==> 0XF8000714[12:12] = 0x00000000U | ||
| 6143 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6144 | // .. DisableRcvr = 0 | ||
| 6145 | // .. ==> 0XF8000714[13:13] = 0x00000000U | ||
| 6146 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6147 | // .. | ||
| 6148 | EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U), | ||
| 6149 | // .. TRI_ENABLE = 0 | ||
| 6150 | // .. ==> 0XF8000718[0:0] = 0x00000000U | ||
| 6151 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6152 | // .. L0_SEL = 1 | ||
| 6153 | // .. ==> 0XF8000718[1:1] = 0x00000001U | ||
| 6154 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6155 | // .. L1_SEL = 0 | ||
| 6156 | // .. ==> 0XF8000718[2:2] = 0x00000000U | ||
| 6157 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6158 | // .. L2_SEL = 0 | ||
| 6159 | // .. ==> 0XF8000718[4:3] = 0x00000000U | ||
| 6160 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6161 | // .. L3_SEL = 0 | ||
| 6162 | // .. ==> 0XF8000718[7:5] = 0x00000000U | ||
| 6163 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6164 | // .. Speed = 1 | ||
| 6165 | // .. ==> 0XF8000718[8:8] = 0x00000001U | ||
| 6166 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6167 | // .. IO_Type = 3 | ||
| 6168 | // .. ==> 0XF8000718[11:9] = 0x00000003U | ||
| 6169 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 6170 | // .. PULLUP = 0 | ||
| 6171 | // .. ==> 0XF8000718[12:12] = 0x00000000U | ||
| 6172 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6173 | // .. DisableRcvr = 0 | ||
| 6174 | // .. ==> 0XF8000718[13:13] = 0x00000000U | ||
| 6175 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6176 | // .. | ||
| 6177 | EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U), | ||
| 6178 | // .. TRI_ENABLE = 0 | ||
| 6179 | // .. ==> 0XF8000740[0:0] = 0x00000000U | ||
| 6180 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6181 | // .. L0_SEL = 1 | ||
| 6182 | // .. ==> 0XF8000740[1:1] = 0x00000001U | ||
| 6183 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6184 | // .. L1_SEL = 0 | ||
| 6185 | // .. ==> 0XF8000740[2:2] = 0x00000000U | ||
| 6186 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6187 | // .. L2_SEL = 0 | ||
| 6188 | // .. ==> 0XF8000740[4:3] = 0x00000000U | ||
| 6189 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6190 | // .. L3_SEL = 0 | ||
| 6191 | // .. ==> 0XF8000740[7:5] = 0x00000000U | ||
| 6192 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6193 | // .. Speed = 1 | ||
| 6194 | // .. ==> 0XF8000740[8:8] = 0x00000001U | ||
| 6195 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6196 | // .. IO_Type = 4 | ||
| 6197 | // .. ==> 0XF8000740[11:9] = 0x00000004U | ||
| 6198 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 6199 | // .. PULLUP = 0 | ||
| 6200 | // .. ==> 0XF8000740[12:12] = 0x00000000U | ||
| 6201 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6202 | // .. DisableRcvr = 1 | ||
| 6203 | // .. ==> 0XF8000740[13:13] = 0x00000001U | ||
| 6204 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 6205 | // .. | ||
| 6206 | EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U), | ||
| 6207 | // .. TRI_ENABLE = 0 | ||
| 6208 | // .. ==> 0XF8000744[0:0] = 0x00000000U | ||
| 6209 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6210 | // .. L0_SEL = 1 | ||
| 6211 | // .. ==> 0XF8000744[1:1] = 0x00000001U | ||
| 6212 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6213 | // .. L1_SEL = 0 | ||
| 6214 | // .. ==> 0XF8000744[2:2] = 0x00000000U | ||
| 6215 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6216 | // .. L2_SEL = 0 | ||
| 6217 | // .. ==> 0XF8000744[4:3] = 0x00000000U | ||
| 6218 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6219 | // .. L3_SEL = 0 | ||
| 6220 | // .. ==> 0XF8000744[7:5] = 0x00000000U | ||
| 6221 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6222 | // .. Speed = 1 | ||
| 6223 | // .. ==> 0XF8000744[8:8] = 0x00000001U | ||
| 6224 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6225 | // .. IO_Type = 4 | ||
| 6226 | // .. ==> 0XF8000744[11:9] = 0x00000004U | ||
| 6227 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 6228 | // .. PULLUP = 0 | ||
| 6229 | // .. ==> 0XF8000744[12:12] = 0x00000000U | ||
| 6230 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6231 | // .. DisableRcvr = 1 | ||
| 6232 | // .. ==> 0XF8000744[13:13] = 0x00000001U | ||
| 6233 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 6234 | // .. | ||
| 6235 | EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U), | ||
| 6236 | // .. TRI_ENABLE = 0 | ||
| 6237 | // .. ==> 0XF8000748[0:0] = 0x00000000U | ||
| 6238 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6239 | // .. L0_SEL = 1 | ||
| 6240 | // .. ==> 0XF8000748[1:1] = 0x00000001U | ||
| 6241 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6242 | // .. L1_SEL = 0 | ||
| 6243 | // .. ==> 0XF8000748[2:2] = 0x00000000U | ||
| 6244 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6245 | // .. L2_SEL = 0 | ||
| 6246 | // .. ==> 0XF8000748[4:3] = 0x00000000U | ||
| 6247 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6248 | // .. L3_SEL = 0 | ||
| 6249 | // .. ==> 0XF8000748[7:5] = 0x00000000U | ||
| 6250 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6251 | // .. Speed = 1 | ||
| 6252 | // .. ==> 0XF8000748[8:8] = 0x00000001U | ||
| 6253 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6254 | // .. IO_Type = 4 | ||
| 6255 | // .. ==> 0XF8000748[11:9] = 0x00000004U | ||
| 6256 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 6257 | // .. PULLUP = 0 | ||
| 6258 | // .. ==> 0XF8000748[12:12] = 0x00000000U | ||
| 6259 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6260 | // .. DisableRcvr = 1 | ||
| 6261 | // .. ==> 0XF8000748[13:13] = 0x00000001U | ||
| 6262 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 6263 | // .. | ||
| 6264 | EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U), | ||
| 6265 | // .. TRI_ENABLE = 0 | ||
| 6266 | // .. ==> 0XF800074C[0:0] = 0x00000000U | ||
| 6267 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6268 | // .. L0_SEL = 1 | ||
| 6269 | // .. ==> 0XF800074C[1:1] = 0x00000001U | ||
| 6270 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6271 | // .. L1_SEL = 0 | ||
| 6272 | // .. ==> 0XF800074C[2:2] = 0x00000000U | ||
| 6273 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6274 | // .. L2_SEL = 0 | ||
| 6275 | // .. ==> 0XF800074C[4:3] = 0x00000000U | ||
| 6276 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6277 | // .. L3_SEL = 0 | ||
| 6278 | // .. ==> 0XF800074C[7:5] = 0x00000000U | ||
| 6279 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6280 | // .. Speed = 1 | ||
| 6281 | // .. ==> 0XF800074C[8:8] = 0x00000001U | ||
| 6282 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6283 | // .. IO_Type = 4 | ||
| 6284 | // .. ==> 0XF800074C[11:9] = 0x00000004U | ||
| 6285 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 6286 | // .. PULLUP = 0 | ||
| 6287 | // .. ==> 0XF800074C[12:12] = 0x00000000U | ||
| 6288 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6289 | // .. DisableRcvr = 1 | ||
| 6290 | // .. ==> 0XF800074C[13:13] = 0x00000001U | ||
| 6291 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 6292 | // .. | ||
| 6293 | EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U), | ||
| 6294 | // .. TRI_ENABLE = 0 | ||
| 6295 | // .. ==> 0XF8000750[0:0] = 0x00000000U | ||
| 6296 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6297 | // .. L0_SEL = 1 | ||
| 6298 | // .. ==> 0XF8000750[1:1] = 0x00000001U | ||
| 6299 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6300 | // .. L1_SEL = 0 | ||
| 6301 | // .. ==> 0XF8000750[2:2] = 0x00000000U | ||
| 6302 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6303 | // .. L2_SEL = 0 | ||
| 6304 | // .. ==> 0XF8000750[4:3] = 0x00000000U | ||
| 6305 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6306 | // .. L3_SEL = 0 | ||
| 6307 | // .. ==> 0XF8000750[7:5] = 0x00000000U | ||
| 6308 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6309 | // .. Speed = 1 | ||
| 6310 | // .. ==> 0XF8000750[8:8] = 0x00000001U | ||
| 6311 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6312 | // .. IO_Type = 4 | ||
| 6313 | // .. ==> 0XF8000750[11:9] = 0x00000004U | ||
| 6314 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 6315 | // .. PULLUP = 0 | ||
| 6316 | // .. ==> 0XF8000750[12:12] = 0x00000000U | ||
| 6317 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6318 | // .. DisableRcvr = 1 | ||
| 6319 | // .. ==> 0XF8000750[13:13] = 0x00000001U | ||
| 6320 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 6321 | // .. | ||
| 6322 | EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U), | ||
| 6323 | // .. TRI_ENABLE = 0 | ||
| 6324 | // .. ==> 0XF8000754[0:0] = 0x00000000U | ||
| 6325 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6326 | // .. L0_SEL = 1 | ||
| 6327 | // .. ==> 0XF8000754[1:1] = 0x00000001U | ||
| 6328 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6329 | // .. L1_SEL = 0 | ||
| 6330 | // .. ==> 0XF8000754[2:2] = 0x00000000U | ||
| 6331 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6332 | // .. L2_SEL = 0 | ||
| 6333 | // .. ==> 0XF8000754[4:3] = 0x00000000U | ||
| 6334 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6335 | // .. L3_SEL = 0 | ||
| 6336 | // .. ==> 0XF8000754[7:5] = 0x00000000U | ||
| 6337 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6338 | // .. Speed = 1 | ||
| 6339 | // .. ==> 0XF8000754[8:8] = 0x00000001U | ||
| 6340 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6341 | // .. IO_Type = 4 | ||
| 6342 | // .. ==> 0XF8000754[11:9] = 0x00000004U | ||
| 6343 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 6344 | // .. PULLUP = 0 | ||
| 6345 | // .. ==> 0XF8000754[12:12] = 0x00000000U | ||
| 6346 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6347 | // .. DisableRcvr = 1 | ||
| 6348 | // .. ==> 0XF8000754[13:13] = 0x00000001U | ||
| 6349 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 6350 | // .. | ||
| 6351 | EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U), | ||
| 6352 | // .. TRI_ENABLE = 1 | ||
| 6353 | // .. ==> 0XF8000758[0:0] = 0x00000001U | ||
| 6354 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 6355 | // .. L0_SEL = 1 | ||
| 6356 | // .. ==> 0XF8000758[1:1] = 0x00000001U | ||
| 6357 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6358 | // .. L1_SEL = 0 | ||
| 6359 | // .. ==> 0XF8000758[2:2] = 0x00000000U | ||
| 6360 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6361 | // .. L2_SEL = 0 | ||
| 6362 | // .. ==> 0XF8000758[4:3] = 0x00000000U | ||
| 6363 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6364 | // .. L3_SEL = 0 | ||
| 6365 | // .. ==> 0XF8000758[7:5] = 0x00000000U | ||
| 6366 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6367 | // .. Speed = 1 | ||
| 6368 | // .. ==> 0XF8000758[8:8] = 0x00000001U | ||
| 6369 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6370 | // .. IO_Type = 4 | ||
| 6371 | // .. ==> 0XF8000758[11:9] = 0x00000004U | ||
| 6372 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 6373 | // .. PULLUP = 0 | ||
| 6374 | // .. ==> 0XF8000758[12:12] = 0x00000000U | ||
| 6375 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6376 | // .. DisableRcvr = 0 | ||
| 6377 | // .. ==> 0XF8000758[13:13] = 0x00000000U | ||
| 6378 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6379 | // .. | ||
| 6380 | EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U), | ||
| 6381 | // .. TRI_ENABLE = 1 | ||
| 6382 | // .. ==> 0XF800075C[0:0] = 0x00000001U | ||
| 6383 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 6384 | // .. L0_SEL = 1 | ||
| 6385 | // .. ==> 0XF800075C[1:1] = 0x00000001U | ||
| 6386 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6387 | // .. L1_SEL = 0 | ||
| 6388 | // .. ==> 0XF800075C[2:2] = 0x00000000U | ||
| 6389 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6390 | // .. L2_SEL = 0 | ||
| 6391 | // .. ==> 0XF800075C[4:3] = 0x00000000U | ||
| 6392 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6393 | // .. L3_SEL = 0 | ||
| 6394 | // .. ==> 0XF800075C[7:5] = 0x00000000U | ||
| 6395 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6396 | // .. Speed = 1 | ||
| 6397 | // .. ==> 0XF800075C[8:8] = 0x00000001U | ||
| 6398 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6399 | // .. IO_Type = 4 | ||
| 6400 | // .. ==> 0XF800075C[11:9] = 0x00000004U | ||
| 6401 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 6402 | // .. PULLUP = 0 | ||
| 6403 | // .. ==> 0XF800075C[12:12] = 0x00000000U | ||
| 6404 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6405 | // .. DisableRcvr = 0 | ||
| 6406 | // .. ==> 0XF800075C[13:13] = 0x00000000U | ||
| 6407 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6408 | // .. | ||
| 6409 | EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U), | ||
| 6410 | // .. TRI_ENABLE = 1 | ||
| 6411 | // .. ==> 0XF8000760[0:0] = 0x00000001U | ||
| 6412 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 6413 | // .. L0_SEL = 1 | ||
| 6414 | // .. ==> 0XF8000760[1:1] = 0x00000001U | ||
| 6415 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6416 | // .. L1_SEL = 0 | ||
| 6417 | // .. ==> 0XF8000760[2:2] = 0x00000000U | ||
| 6418 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6419 | // .. L2_SEL = 0 | ||
| 6420 | // .. ==> 0XF8000760[4:3] = 0x00000000U | ||
| 6421 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6422 | // .. L3_SEL = 0 | ||
| 6423 | // .. ==> 0XF8000760[7:5] = 0x00000000U | ||
| 6424 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6425 | // .. Speed = 1 | ||
| 6426 | // .. ==> 0XF8000760[8:8] = 0x00000001U | ||
| 6427 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6428 | // .. IO_Type = 4 | ||
| 6429 | // .. ==> 0XF8000760[11:9] = 0x00000004U | ||
| 6430 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 6431 | // .. PULLUP = 0 | ||
| 6432 | // .. ==> 0XF8000760[12:12] = 0x00000000U | ||
| 6433 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6434 | // .. DisableRcvr = 0 | ||
| 6435 | // .. ==> 0XF8000760[13:13] = 0x00000000U | ||
| 6436 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6437 | // .. | ||
| 6438 | EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U), | ||
| 6439 | // .. TRI_ENABLE = 1 | ||
| 6440 | // .. ==> 0XF8000764[0:0] = 0x00000001U | ||
| 6441 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 6442 | // .. L0_SEL = 1 | ||
| 6443 | // .. ==> 0XF8000764[1:1] = 0x00000001U | ||
| 6444 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6445 | // .. L1_SEL = 0 | ||
| 6446 | // .. ==> 0XF8000764[2:2] = 0x00000000U | ||
| 6447 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6448 | // .. L2_SEL = 0 | ||
| 6449 | // .. ==> 0XF8000764[4:3] = 0x00000000U | ||
| 6450 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6451 | // .. L3_SEL = 0 | ||
| 6452 | // .. ==> 0XF8000764[7:5] = 0x00000000U | ||
| 6453 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6454 | // .. Speed = 1 | ||
| 6455 | // .. ==> 0XF8000764[8:8] = 0x00000001U | ||
| 6456 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6457 | // .. IO_Type = 4 | ||
| 6458 | // .. ==> 0XF8000764[11:9] = 0x00000004U | ||
| 6459 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 6460 | // .. PULLUP = 0 | ||
| 6461 | // .. ==> 0XF8000764[12:12] = 0x00000000U | ||
| 6462 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6463 | // .. DisableRcvr = 0 | ||
| 6464 | // .. ==> 0XF8000764[13:13] = 0x00000000U | ||
| 6465 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6466 | // .. | ||
| 6467 | EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U), | ||
| 6468 | // .. TRI_ENABLE = 1 | ||
| 6469 | // .. ==> 0XF8000768[0:0] = 0x00000001U | ||
| 6470 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 6471 | // .. L0_SEL = 1 | ||
| 6472 | // .. ==> 0XF8000768[1:1] = 0x00000001U | ||
| 6473 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6474 | // .. L1_SEL = 0 | ||
| 6475 | // .. ==> 0XF8000768[2:2] = 0x00000000U | ||
| 6476 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6477 | // .. L2_SEL = 0 | ||
| 6478 | // .. ==> 0XF8000768[4:3] = 0x00000000U | ||
| 6479 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6480 | // .. L3_SEL = 0 | ||
| 6481 | // .. ==> 0XF8000768[7:5] = 0x00000000U | ||
| 6482 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6483 | // .. Speed = 1 | ||
| 6484 | // .. ==> 0XF8000768[8:8] = 0x00000001U | ||
| 6485 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6486 | // .. IO_Type = 4 | ||
| 6487 | // .. ==> 0XF8000768[11:9] = 0x00000004U | ||
| 6488 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 6489 | // .. PULLUP = 0 | ||
| 6490 | // .. ==> 0XF8000768[12:12] = 0x00000000U | ||
| 6491 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6492 | // .. DisableRcvr = 0 | ||
| 6493 | // .. ==> 0XF8000768[13:13] = 0x00000000U | ||
| 6494 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6495 | // .. | ||
| 6496 | EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U), | ||
| 6497 | // .. TRI_ENABLE = 1 | ||
| 6498 | // .. ==> 0XF800076C[0:0] = 0x00000001U | ||
| 6499 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 6500 | // .. L0_SEL = 1 | ||
| 6501 | // .. ==> 0XF800076C[1:1] = 0x00000001U | ||
| 6502 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 6503 | // .. L1_SEL = 0 | ||
| 6504 | // .. ==> 0XF800076C[2:2] = 0x00000000U | ||
| 6505 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6506 | // .. L2_SEL = 0 | ||
| 6507 | // .. ==> 0XF800076C[4:3] = 0x00000000U | ||
| 6508 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6509 | // .. L3_SEL = 0 | ||
| 6510 | // .. ==> 0XF800076C[7:5] = 0x00000000U | ||
| 6511 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6512 | // .. Speed = 1 | ||
| 6513 | // .. ==> 0XF800076C[8:8] = 0x00000001U | ||
| 6514 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6515 | // .. IO_Type = 4 | ||
| 6516 | // .. ==> 0XF800076C[11:9] = 0x00000004U | ||
| 6517 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 6518 | // .. PULLUP = 0 | ||
| 6519 | // .. ==> 0XF800076C[12:12] = 0x00000000U | ||
| 6520 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6521 | // .. DisableRcvr = 0 | ||
| 6522 | // .. ==> 0XF800076C[13:13] = 0x00000000U | ||
| 6523 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6524 | // .. | ||
| 6525 | EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U), | ||
| 6526 | // .. TRI_ENABLE = 0 | ||
| 6527 | // .. ==> 0XF8000770[0:0] = 0x00000000U | ||
| 6528 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6529 | // .. L0_SEL = 0 | ||
| 6530 | // .. ==> 0XF8000770[1:1] = 0x00000000U | ||
| 6531 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6532 | // .. L1_SEL = 1 | ||
| 6533 | // .. ==> 0XF8000770[2:2] = 0x00000001U | ||
| 6534 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 6535 | // .. L2_SEL = 0 | ||
| 6536 | // .. ==> 0XF8000770[4:3] = 0x00000000U | ||
| 6537 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6538 | // .. L3_SEL = 0 | ||
| 6539 | // .. ==> 0XF8000770[7:5] = 0x00000000U | ||
| 6540 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6541 | // .. Speed = 1 | ||
| 6542 | // .. ==> 0XF8000770[8:8] = 0x00000001U | ||
| 6543 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6544 | // .. IO_Type = 1 | ||
| 6545 | // .. ==> 0XF8000770[11:9] = 0x00000001U | ||
| 6546 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 6547 | // .. PULLUP = 0 | ||
| 6548 | // .. ==> 0XF8000770[12:12] = 0x00000000U | ||
| 6549 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6550 | // .. DisableRcvr = 0 | ||
| 6551 | // .. ==> 0XF8000770[13:13] = 0x00000000U | ||
| 6552 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6553 | // .. | ||
| 6554 | EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U), | ||
| 6555 | // .. TRI_ENABLE = 1 | ||
| 6556 | // .. ==> 0XF8000774[0:0] = 0x00000001U | ||
| 6557 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 6558 | // .. L0_SEL = 0 | ||
| 6559 | // .. ==> 0XF8000774[1:1] = 0x00000000U | ||
| 6560 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6561 | // .. L1_SEL = 1 | ||
| 6562 | // .. ==> 0XF8000774[2:2] = 0x00000001U | ||
| 6563 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 6564 | // .. L2_SEL = 0 | ||
| 6565 | // .. ==> 0XF8000774[4:3] = 0x00000000U | ||
| 6566 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6567 | // .. L3_SEL = 0 | ||
| 6568 | // .. ==> 0XF8000774[7:5] = 0x00000000U | ||
| 6569 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6570 | // .. Speed = 1 | ||
| 6571 | // .. ==> 0XF8000774[8:8] = 0x00000001U | ||
| 6572 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6573 | // .. IO_Type = 1 | ||
| 6574 | // .. ==> 0XF8000774[11:9] = 0x00000001U | ||
| 6575 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 6576 | // .. PULLUP = 0 | ||
| 6577 | // .. ==> 0XF8000774[12:12] = 0x00000000U | ||
| 6578 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6579 | // .. DisableRcvr = 0 | ||
| 6580 | // .. ==> 0XF8000774[13:13] = 0x00000000U | ||
| 6581 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6582 | // .. | ||
| 6583 | EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U), | ||
| 6584 | // .. TRI_ENABLE = 0 | ||
| 6585 | // .. ==> 0XF8000778[0:0] = 0x00000000U | ||
| 6586 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6587 | // .. L0_SEL = 0 | ||
| 6588 | // .. ==> 0XF8000778[1:1] = 0x00000000U | ||
| 6589 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6590 | // .. L1_SEL = 1 | ||
| 6591 | // .. ==> 0XF8000778[2:2] = 0x00000001U | ||
| 6592 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 6593 | // .. L2_SEL = 0 | ||
| 6594 | // .. ==> 0XF8000778[4:3] = 0x00000000U | ||
| 6595 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6596 | // .. L3_SEL = 0 | ||
| 6597 | // .. ==> 0XF8000778[7:5] = 0x00000000U | ||
| 6598 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6599 | // .. Speed = 1 | ||
| 6600 | // .. ==> 0XF8000778[8:8] = 0x00000001U | ||
| 6601 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6602 | // .. IO_Type = 1 | ||
| 6603 | // .. ==> 0XF8000778[11:9] = 0x00000001U | ||
| 6604 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 6605 | // .. PULLUP = 0 | ||
| 6606 | // .. ==> 0XF8000778[12:12] = 0x00000000U | ||
| 6607 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6608 | // .. DisableRcvr = 0 | ||
| 6609 | // .. ==> 0XF8000778[13:13] = 0x00000000U | ||
| 6610 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6611 | // .. | ||
| 6612 | EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U), | ||
| 6613 | // .. TRI_ENABLE = 1 | ||
| 6614 | // .. ==> 0XF800077C[0:0] = 0x00000001U | ||
| 6615 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 6616 | // .. L0_SEL = 0 | ||
| 6617 | // .. ==> 0XF800077C[1:1] = 0x00000000U | ||
| 6618 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6619 | // .. L1_SEL = 1 | ||
| 6620 | // .. ==> 0XF800077C[2:2] = 0x00000001U | ||
| 6621 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 6622 | // .. L2_SEL = 0 | ||
| 6623 | // .. ==> 0XF800077C[4:3] = 0x00000000U | ||
| 6624 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6625 | // .. L3_SEL = 0 | ||
| 6626 | // .. ==> 0XF800077C[7:5] = 0x00000000U | ||
| 6627 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6628 | // .. Speed = 1 | ||
| 6629 | // .. ==> 0XF800077C[8:8] = 0x00000001U | ||
| 6630 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6631 | // .. IO_Type = 1 | ||
| 6632 | // .. ==> 0XF800077C[11:9] = 0x00000001U | ||
| 6633 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 6634 | // .. PULLUP = 0 | ||
| 6635 | // .. ==> 0XF800077C[12:12] = 0x00000000U | ||
| 6636 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6637 | // .. DisableRcvr = 0 | ||
| 6638 | // .. ==> 0XF800077C[13:13] = 0x00000000U | ||
| 6639 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6640 | // .. | ||
| 6641 | EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U), | ||
| 6642 | // .. TRI_ENABLE = 0 | ||
| 6643 | // .. ==> 0XF8000780[0:0] = 0x00000000U | ||
| 6644 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6645 | // .. L0_SEL = 0 | ||
| 6646 | // .. ==> 0XF8000780[1:1] = 0x00000000U | ||
| 6647 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6648 | // .. L1_SEL = 1 | ||
| 6649 | // .. ==> 0XF8000780[2:2] = 0x00000001U | ||
| 6650 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 6651 | // .. L2_SEL = 0 | ||
| 6652 | // .. ==> 0XF8000780[4:3] = 0x00000000U | ||
| 6653 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6654 | // .. L3_SEL = 0 | ||
| 6655 | // .. ==> 0XF8000780[7:5] = 0x00000000U | ||
| 6656 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6657 | // .. Speed = 1 | ||
| 6658 | // .. ==> 0XF8000780[8:8] = 0x00000001U | ||
| 6659 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6660 | // .. IO_Type = 1 | ||
| 6661 | // .. ==> 0XF8000780[11:9] = 0x00000001U | ||
| 6662 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 6663 | // .. PULLUP = 0 | ||
| 6664 | // .. ==> 0XF8000780[12:12] = 0x00000000U | ||
| 6665 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6666 | // .. DisableRcvr = 0 | ||
| 6667 | // .. ==> 0XF8000780[13:13] = 0x00000000U | ||
| 6668 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6669 | // .. | ||
| 6670 | EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U), | ||
| 6671 | // .. TRI_ENABLE = 0 | ||
| 6672 | // .. ==> 0XF8000784[0:0] = 0x00000000U | ||
| 6673 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6674 | // .. L0_SEL = 0 | ||
| 6675 | // .. ==> 0XF8000784[1:1] = 0x00000000U | ||
| 6676 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6677 | // .. L1_SEL = 1 | ||
| 6678 | // .. ==> 0XF8000784[2:2] = 0x00000001U | ||
| 6679 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 6680 | // .. L2_SEL = 0 | ||
| 6681 | // .. ==> 0XF8000784[4:3] = 0x00000000U | ||
| 6682 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6683 | // .. L3_SEL = 0 | ||
| 6684 | // .. ==> 0XF8000784[7:5] = 0x00000000U | ||
| 6685 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6686 | // .. Speed = 1 | ||
| 6687 | // .. ==> 0XF8000784[8:8] = 0x00000001U | ||
| 6688 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6689 | // .. IO_Type = 1 | ||
| 6690 | // .. ==> 0XF8000784[11:9] = 0x00000001U | ||
| 6691 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 6692 | // .. PULLUP = 0 | ||
| 6693 | // .. ==> 0XF8000784[12:12] = 0x00000000U | ||
| 6694 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6695 | // .. DisableRcvr = 0 | ||
| 6696 | // .. ==> 0XF8000784[13:13] = 0x00000000U | ||
| 6697 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6698 | // .. | ||
| 6699 | EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U), | ||
| 6700 | // .. TRI_ENABLE = 0 | ||
| 6701 | // .. ==> 0XF8000788[0:0] = 0x00000000U | ||
| 6702 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6703 | // .. L0_SEL = 0 | ||
| 6704 | // .. ==> 0XF8000788[1:1] = 0x00000000U | ||
| 6705 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6706 | // .. L1_SEL = 1 | ||
| 6707 | // .. ==> 0XF8000788[2:2] = 0x00000001U | ||
| 6708 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 6709 | // .. L2_SEL = 0 | ||
| 6710 | // .. ==> 0XF8000788[4:3] = 0x00000000U | ||
| 6711 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6712 | // .. L3_SEL = 0 | ||
| 6713 | // .. ==> 0XF8000788[7:5] = 0x00000000U | ||
| 6714 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6715 | // .. Speed = 1 | ||
| 6716 | // .. ==> 0XF8000788[8:8] = 0x00000001U | ||
| 6717 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6718 | // .. IO_Type = 1 | ||
| 6719 | // .. ==> 0XF8000788[11:9] = 0x00000001U | ||
| 6720 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 6721 | // .. PULLUP = 0 | ||
| 6722 | // .. ==> 0XF8000788[12:12] = 0x00000000U | ||
| 6723 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6724 | // .. DisableRcvr = 0 | ||
| 6725 | // .. ==> 0XF8000788[13:13] = 0x00000000U | ||
| 6726 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6727 | // .. | ||
| 6728 | EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U), | ||
| 6729 | // .. TRI_ENABLE = 0 | ||
| 6730 | // .. ==> 0XF800078C[0:0] = 0x00000000U | ||
| 6731 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6732 | // .. L0_SEL = 0 | ||
| 6733 | // .. ==> 0XF800078C[1:1] = 0x00000000U | ||
| 6734 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6735 | // .. L1_SEL = 1 | ||
| 6736 | // .. ==> 0XF800078C[2:2] = 0x00000001U | ||
| 6737 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 6738 | // .. L2_SEL = 0 | ||
| 6739 | // .. ==> 0XF800078C[4:3] = 0x00000000U | ||
| 6740 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6741 | // .. L3_SEL = 0 | ||
| 6742 | // .. ==> 0XF800078C[7:5] = 0x00000000U | ||
| 6743 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6744 | // .. Speed = 1 | ||
| 6745 | // .. ==> 0XF800078C[8:8] = 0x00000001U | ||
| 6746 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6747 | // .. IO_Type = 1 | ||
| 6748 | // .. ==> 0XF800078C[11:9] = 0x00000001U | ||
| 6749 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 6750 | // .. PULLUP = 0 | ||
| 6751 | // .. ==> 0XF800078C[12:12] = 0x00000000U | ||
| 6752 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6753 | // .. DisableRcvr = 0 | ||
| 6754 | // .. ==> 0XF800078C[13:13] = 0x00000000U | ||
| 6755 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6756 | // .. | ||
| 6757 | EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U), | ||
| 6758 | // .. TRI_ENABLE = 1 | ||
| 6759 | // .. ==> 0XF8000790[0:0] = 0x00000001U | ||
| 6760 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 6761 | // .. L0_SEL = 0 | ||
| 6762 | // .. ==> 0XF8000790[1:1] = 0x00000000U | ||
| 6763 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6764 | // .. L1_SEL = 1 | ||
| 6765 | // .. ==> 0XF8000790[2:2] = 0x00000001U | ||
| 6766 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 6767 | // .. L2_SEL = 0 | ||
| 6768 | // .. ==> 0XF8000790[4:3] = 0x00000000U | ||
| 6769 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6770 | // .. L3_SEL = 0 | ||
| 6771 | // .. ==> 0XF8000790[7:5] = 0x00000000U | ||
| 6772 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6773 | // .. Speed = 1 | ||
| 6774 | // .. ==> 0XF8000790[8:8] = 0x00000001U | ||
| 6775 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6776 | // .. IO_Type = 1 | ||
| 6777 | // .. ==> 0XF8000790[11:9] = 0x00000001U | ||
| 6778 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 6779 | // .. PULLUP = 0 | ||
| 6780 | // .. ==> 0XF8000790[12:12] = 0x00000000U | ||
| 6781 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6782 | // .. DisableRcvr = 0 | ||
| 6783 | // .. ==> 0XF8000790[13:13] = 0x00000000U | ||
| 6784 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6785 | // .. | ||
| 6786 | EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U), | ||
| 6787 | // .. TRI_ENABLE = 0 | ||
| 6788 | // .. ==> 0XF8000794[0:0] = 0x00000000U | ||
| 6789 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6790 | // .. L0_SEL = 0 | ||
| 6791 | // .. ==> 0XF8000794[1:1] = 0x00000000U | ||
| 6792 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6793 | // .. L1_SEL = 1 | ||
| 6794 | // .. ==> 0XF8000794[2:2] = 0x00000001U | ||
| 6795 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 6796 | // .. L2_SEL = 0 | ||
| 6797 | // .. ==> 0XF8000794[4:3] = 0x00000000U | ||
| 6798 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6799 | // .. L3_SEL = 0 | ||
| 6800 | // .. ==> 0XF8000794[7:5] = 0x00000000U | ||
| 6801 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6802 | // .. Speed = 1 | ||
| 6803 | // .. ==> 0XF8000794[8:8] = 0x00000001U | ||
| 6804 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6805 | // .. IO_Type = 1 | ||
| 6806 | // .. ==> 0XF8000794[11:9] = 0x00000001U | ||
| 6807 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 6808 | // .. PULLUP = 0 | ||
| 6809 | // .. ==> 0XF8000794[12:12] = 0x00000000U | ||
| 6810 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6811 | // .. DisableRcvr = 0 | ||
| 6812 | // .. ==> 0XF8000794[13:13] = 0x00000000U | ||
| 6813 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6814 | // .. | ||
| 6815 | EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U), | ||
| 6816 | // .. TRI_ENABLE = 0 | ||
| 6817 | // .. ==> 0XF8000798[0:0] = 0x00000000U | ||
| 6818 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6819 | // .. L0_SEL = 0 | ||
| 6820 | // .. ==> 0XF8000798[1:1] = 0x00000000U | ||
| 6821 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6822 | // .. L1_SEL = 1 | ||
| 6823 | // .. ==> 0XF8000798[2:2] = 0x00000001U | ||
| 6824 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 6825 | // .. L2_SEL = 0 | ||
| 6826 | // .. ==> 0XF8000798[4:3] = 0x00000000U | ||
| 6827 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6828 | // .. L3_SEL = 0 | ||
| 6829 | // .. ==> 0XF8000798[7:5] = 0x00000000U | ||
| 6830 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6831 | // .. Speed = 1 | ||
| 6832 | // .. ==> 0XF8000798[8:8] = 0x00000001U | ||
| 6833 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6834 | // .. IO_Type = 1 | ||
| 6835 | // .. ==> 0XF8000798[11:9] = 0x00000001U | ||
| 6836 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 6837 | // .. PULLUP = 0 | ||
| 6838 | // .. ==> 0XF8000798[12:12] = 0x00000000U | ||
| 6839 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6840 | // .. DisableRcvr = 0 | ||
| 6841 | // .. ==> 0XF8000798[13:13] = 0x00000000U | ||
| 6842 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6843 | // .. | ||
| 6844 | EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U), | ||
| 6845 | // .. TRI_ENABLE = 0 | ||
| 6846 | // .. ==> 0XF800079C[0:0] = 0x00000000U | ||
| 6847 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6848 | // .. L0_SEL = 0 | ||
| 6849 | // .. ==> 0XF800079C[1:1] = 0x00000000U | ||
| 6850 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6851 | // .. L1_SEL = 1 | ||
| 6852 | // .. ==> 0XF800079C[2:2] = 0x00000001U | ||
| 6853 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 6854 | // .. L2_SEL = 0 | ||
| 6855 | // .. ==> 0XF800079C[4:3] = 0x00000000U | ||
| 6856 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6857 | // .. L3_SEL = 0 | ||
| 6858 | // .. ==> 0XF800079C[7:5] = 0x00000000U | ||
| 6859 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 6860 | // .. Speed = 1 | ||
| 6861 | // .. ==> 0XF800079C[8:8] = 0x00000001U | ||
| 6862 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6863 | // .. IO_Type = 1 | ||
| 6864 | // .. ==> 0XF800079C[11:9] = 0x00000001U | ||
| 6865 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 6866 | // .. PULLUP = 0 | ||
| 6867 | // .. ==> 0XF800079C[12:12] = 0x00000000U | ||
| 6868 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6869 | // .. DisableRcvr = 0 | ||
| 6870 | // .. ==> 0XF800079C[13:13] = 0x00000000U | ||
| 6871 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6872 | // .. | ||
| 6873 | EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U), | ||
| 6874 | // .. TRI_ENABLE = 0 | ||
| 6875 | // .. ==> 0XF80007A0[0:0] = 0x00000000U | ||
| 6876 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6877 | // .. L0_SEL = 0 | ||
| 6878 | // .. ==> 0XF80007A0[1:1] = 0x00000000U | ||
| 6879 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6880 | // .. L1_SEL = 0 | ||
| 6881 | // .. ==> 0XF80007A0[2:2] = 0x00000000U | ||
| 6882 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6883 | // .. L2_SEL = 0 | ||
| 6884 | // .. ==> 0XF80007A0[4:3] = 0x00000000U | ||
| 6885 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6886 | // .. L3_SEL = 4 | ||
| 6887 | // .. ==> 0XF80007A0[7:5] = 0x00000004U | ||
| 6888 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 6889 | // .. Speed = 1 | ||
| 6890 | // .. ==> 0XF80007A0[8:8] = 0x00000001U | ||
| 6891 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6892 | // .. IO_Type = 1 | ||
| 6893 | // .. ==> 0XF80007A0[11:9] = 0x00000001U | ||
| 6894 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 6895 | // .. PULLUP = 0 | ||
| 6896 | // .. ==> 0XF80007A0[12:12] = 0x00000000U | ||
| 6897 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6898 | // .. DisableRcvr = 0 | ||
| 6899 | // .. ==> 0XF80007A0[13:13] = 0x00000000U | ||
| 6900 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6901 | // .. | ||
| 6902 | EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U), | ||
| 6903 | // .. TRI_ENABLE = 0 | ||
| 6904 | // .. ==> 0XF80007A4[0:0] = 0x00000000U | ||
| 6905 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6906 | // .. L0_SEL = 0 | ||
| 6907 | // .. ==> 0XF80007A4[1:1] = 0x00000000U | ||
| 6908 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6909 | // .. L1_SEL = 0 | ||
| 6910 | // .. ==> 0XF80007A4[2:2] = 0x00000000U | ||
| 6911 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6912 | // .. L2_SEL = 0 | ||
| 6913 | // .. ==> 0XF80007A4[4:3] = 0x00000000U | ||
| 6914 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6915 | // .. L3_SEL = 4 | ||
| 6916 | // .. ==> 0XF80007A4[7:5] = 0x00000004U | ||
| 6917 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 6918 | // .. Speed = 1 | ||
| 6919 | // .. ==> 0XF80007A4[8:8] = 0x00000001U | ||
| 6920 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6921 | // .. IO_Type = 1 | ||
| 6922 | // .. ==> 0XF80007A4[11:9] = 0x00000001U | ||
| 6923 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 6924 | // .. PULLUP = 0 | ||
| 6925 | // .. ==> 0XF80007A4[12:12] = 0x00000000U | ||
| 6926 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6927 | // .. DisableRcvr = 0 | ||
| 6928 | // .. ==> 0XF80007A4[13:13] = 0x00000000U | ||
| 6929 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6930 | // .. | ||
| 6931 | EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U), | ||
| 6932 | // .. TRI_ENABLE = 0 | ||
| 6933 | // .. ==> 0XF80007A8[0:0] = 0x00000000U | ||
| 6934 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6935 | // .. L0_SEL = 0 | ||
| 6936 | // .. ==> 0XF80007A8[1:1] = 0x00000000U | ||
| 6937 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6938 | // .. L1_SEL = 0 | ||
| 6939 | // .. ==> 0XF80007A8[2:2] = 0x00000000U | ||
| 6940 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6941 | // .. L2_SEL = 0 | ||
| 6942 | // .. ==> 0XF80007A8[4:3] = 0x00000000U | ||
| 6943 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6944 | // .. L3_SEL = 4 | ||
| 6945 | // .. ==> 0XF80007A8[7:5] = 0x00000004U | ||
| 6946 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 6947 | // .. Speed = 1 | ||
| 6948 | // .. ==> 0XF80007A8[8:8] = 0x00000001U | ||
| 6949 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6950 | // .. IO_Type = 1 | ||
| 6951 | // .. ==> 0XF80007A8[11:9] = 0x00000001U | ||
| 6952 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 6953 | // .. PULLUP = 0 | ||
| 6954 | // .. ==> 0XF80007A8[12:12] = 0x00000000U | ||
| 6955 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6956 | // .. DisableRcvr = 0 | ||
| 6957 | // .. ==> 0XF80007A8[13:13] = 0x00000000U | ||
| 6958 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6959 | // .. | ||
| 6960 | EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U), | ||
| 6961 | // .. TRI_ENABLE = 0 | ||
| 6962 | // .. ==> 0XF80007AC[0:0] = 0x00000000U | ||
| 6963 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6964 | // .. L0_SEL = 0 | ||
| 6965 | // .. ==> 0XF80007AC[1:1] = 0x00000000U | ||
| 6966 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6967 | // .. L1_SEL = 0 | ||
| 6968 | // .. ==> 0XF80007AC[2:2] = 0x00000000U | ||
| 6969 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6970 | // .. L2_SEL = 0 | ||
| 6971 | // .. ==> 0XF80007AC[4:3] = 0x00000000U | ||
| 6972 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 6973 | // .. L3_SEL = 4 | ||
| 6974 | // .. ==> 0XF80007AC[7:5] = 0x00000004U | ||
| 6975 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 6976 | // .. Speed = 1 | ||
| 6977 | // .. ==> 0XF80007AC[8:8] = 0x00000001U | ||
| 6978 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 6979 | // .. IO_Type = 1 | ||
| 6980 | // .. ==> 0XF80007AC[11:9] = 0x00000001U | ||
| 6981 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 6982 | // .. PULLUP = 0 | ||
| 6983 | // .. ==> 0XF80007AC[12:12] = 0x00000000U | ||
| 6984 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 6985 | // .. DisableRcvr = 0 | ||
| 6986 | // .. ==> 0XF80007AC[13:13] = 0x00000000U | ||
| 6987 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 6988 | // .. | ||
| 6989 | EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U), | ||
| 6990 | // .. TRI_ENABLE = 0 | ||
| 6991 | // .. ==> 0XF80007B0[0:0] = 0x00000000U | ||
| 6992 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 6993 | // .. L0_SEL = 0 | ||
| 6994 | // .. ==> 0XF80007B0[1:1] = 0x00000000U | ||
| 6995 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 6996 | // .. L1_SEL = 0 | ||
| 6997 | // .. ==> 0XF80007B0[2:2] = 0x00000000U | ||
| 6998 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 6999 | // .. L2_SEL = 0 | ||
| 7000 | // .. ==> 0XF80007B0[4:3] = 0x00000000U | ||
| 7001 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 7002 | // .. L3_SEL = 4 | ||
| 7003 | // .. ==> 0XF80007B0[7:5] = 0x00000004U | ||
| 7004 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 7005 | // .. Speed = 1 | ||
| 7006 | // .. ==> 0XF80007B0[8:8] = 0x00000001U | ||
| 7007 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 7008 | // .. IO_Type = 1 | ||
| 7009 | // .. ==> 0XF80007B0[11:9] = 0x00000001U | ||
| 7010 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 7011 | // .. PULLUP = 0 | ||
| 7012 | // .. ==> 0XF80007B0[12:12] = 0x00000000U | ||
| 7013 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 7014 | // .. DisableRcvr = 0 | ||
| 7015 | // .. ==> 0XF80007B0[13:13] = 0x00000000U | ||
| 7016 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 7017 | // .. | ||
| 7018 | EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U), | ||
| 7019 | // .. TRI_ENABLE = 0 | ||
| 7020 | // .. ==> 0XF80007B4[0:0] = 0x00000000U | ||
| 7021 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 7022 | // .. L0_SEL = 0 | ||
| 7023 | // .. ==> 0XF80007B4[1:1] = 0x00000000U | ||
| 7024 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 7025 | // .. L1_SEL = 0 | ||
| 7026 | // .. ==> 0XF80007B4[2:2] = 0x00000000U | ||
| 7027 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 7028 | // .. L2_SEL = 0 | ||
| 7029 | // .. ==> 0XF80007B4[4:3] = 0x00000000U | ||
| 7030 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 7031 | // .. L3_SEL = 4 | ||
| 7032 | // .. ==> 0XF80007B4[7:5] = 0x00000004U | ||
| 7033 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 7034 | // .. Speed = 1 | ||
| 7035 | // .. ==> 0XF80007B4[8:8] = 0x00000001U | ||
| 7036 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 7037 | // .. IO_Type = 1 | ||
| 7038 | // .. ==> 0XF80007B4[11:9] = 0x00000001U | ||
| 7039 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 7040 | // .. PULLUP = 0 | ||
| 7041 | // .. ==> 0XF80007B4[12:12] = 0x00000000U | ||
| 7042 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 7043 | // .. DisableRcvr = 0 | ||
| 7044 | // .. ==> 0XF80007B4[13:13] = 0x00000000U | ||
| 7045 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 7046 | // .. | ||
| 7047 | EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U), | ||
| 7048 | // .. TRI_ENABLE = 1 | ||
| 7049 | // .. ==> 0XF80007BC[0:0] = 0x00000001U | ||
| 7050 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 7051 | // .. Speed = 0 | ||
| 7052 | // .. ==> 0XF80007BC[8:8] = 0x00000000U | ||
| 7053 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 7054 | // .. IO_Type = 1 | ||
| 7055 | // .. ==> 0XF80007BC[11:9] = 0x00000001U | ||
| 7056 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 7057 | // .. PULLUP = 0 | ||
| 7058 | // .. ==> 0XF80007BC[12:12] = 0x00000000U | ||
| 7059 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 7060 | // .. DisableRcvr = 0 | ||
| 7061 | // .. ==> 0XF80007BC[13:13] = 0x00000000U | ||
| 7062 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 7063 | // .. | ||
| 7064 | EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U), | ||
| 7065 | // .. TRI_ENABLE = 0 | ||
| 7066 | // .. ==> 0XF80007C0[0:0] = 0x00000000U | ||
| 7067 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 7068 | // .. L0_SEL = 0 | ||
| 7069 | // .. ==> 0XF80007C0[1:1] = 0x00000000U | ||
| 7070 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 7071 | // .. L1_SEL = 0 | ||
| 7072 | // .. ==> 0XF80007C0[2:2] = 0x00000000U | ||
| 7073 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 7074 | // .. L2_SEL = 0 | ||
| 7075 | // .. ==> 0XF80007C0[4:3] = 0x00000000U | ||
| 7076 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 7077 | // .. L3_SEL = 7 | ||
| 7078 | // .. ==> 0XF80007C0[7:5] = 0x00000007U | ||
| 7079 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | ||
| 7080 | // .. Speed = 0 | ||
| 7081 | // .. ==> 0XF80007C0[8:8] = 0x00000000U | ||
| 7082 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 7083 | // .. IO_Type = 1 | ||
| 7084 | // .. ==> 0XF80007C0[11:9] = 0x00000001U | ||
| 7085 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 7086 | // .. PULLUP = 0 | ||
| 7087 | // .. ==> 0XF80007C0[12:12] = 0x00000000U | ||
| 7088 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 7089 | // .. DisableRcvr = 0 | ||
| 7090 | // .. ==> 0XF80007C0[13:13] = 0x00000000U | ||
| 7091 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 7092 | // .. | ||
| 7093 | EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), | ||
| 7094 | // .. TRI_ENABLE = 1 | ||
| 7095 | // .. ==> 0XF80007C4[0:0] = 0x00000001U | ||
| 7096 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 7097 | // .. L0_SEL = 0 | ||
| 7098 | // .. ==> 0XF80007C4[1:1] = 0x00000000U | ||
| 7099 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 7100 | // .. L1_SEL = 0 | ||
| 7101 | // .. ==> 0XF80007C4[2:2] = 0x00000000U | ||
| 7102 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 7103 | // .. L2_SEL = 0 | ||
| 7104 | // .. ==> 0XF80007C4[4:3] = 0x00000000U | ||
| 7105 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 7106 | // .. L3_SEL = 7 | ||
| 7107 | // .. ==> 0XF80007C4[7:5] = 0x00000007U | ||
| 7108 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | ||
| 7109 | // .. Speed = 0 | ||
| 7110 | // .. ==> 0XF80007C4[8:8] = 0x00000000U | ||
| 7111 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 7112 | // .. IO_Type = 1 | ||
| 7113 | // .. ==> 0XF80007C4[11:9] = 0x00000001U | ||
| 7114 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 7115 | // .. PULLUP = 0 | ||
| 7116 | // .. ==> 0XF80007C4[12:12] = 0x00000000U | ||
| 7117 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 7118 | // .. DisableRcvr = 0 | ||
| 7119 | // .. ==> 0XF80007C4[13:13] = 0x00000000U | ||
| 7120 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 7121 | // .. | ||
| 7122 | EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), | ||
| 7123 | // .. TRI_ENABLE = 0 | ||
| 7124 | // .. ==> 0XF80007D0[0:0] = 0x00000000U | ||
| 7125 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 7126 | // .. L0_SEL = 0 | ||
| 7127 | // .. ==> 0XF80007D0[1:1] = 0x00000000U | ||
| 7128 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 7129 | // .. L1_SEL = 0 | ||
| 7130 | // .. ==> 0XF80007D0[2:2] = 0x00000000U | ||
| 7131 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 7132 | // .. L2_SEL = 0 | ||
| 7133 | // .. ==> 0XF80007D0[4:3] = 0x00000000U | ||
| 7134 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 7135 | // .. L3_SEL = 4 | ||
| 7136 | // .. ==> 0XF80007D0[7:5] = 0x00000004U | ||
| 7137 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 7138 | // .. Speed = 0 | ||
| 7139 | // .. ==> 0XF80007D0[8:8] = 0x00000000U | ||
| 7140 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 7141 | // .. IO_Type = 1 | ||
| 7142 | // .. ==> 0XF80007D0[11:9] = 0x00000001U | ||
| 7143 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 7144 | // .. PULLUP = 0 | ||
| 7145 | // .. ==> 0XF80007D0[12:12] = 0x00000000U | ||
| 7146 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 7147 | // .. DisableRcvr = 0 | ||
| 7148 | // .. ==> 0XF80007D0[13:13] = 0x00000000U | ||
| 7149 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 7150 | // .. | ||
| 7151 | EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), | ||
| 7152 | // .. TRI_ENABLE = 0 | ||
| 7153 | // .. ==> 0XF80007D4[0:0] = 0x00000000U | ||
| 7154 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 7155 | // .. L0_SEL = 0 | ||
| 7156 | // .. ==> 0XF80007D4[1:1] = 0x00000000U | ||
| 7157 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 7158 | // .. L1_SEL = 0 | ||
| 7159 | // .. ==> 0XF80007D4[2:2] = 0x00000000U | ||
| 7160 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 7161 | // .. L2_SEL = 0 | ||
| 7162 | // .. ==> 0XF80007D4[4:3] = 0x00000000U | ||
| 7163 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 7164 | // .. L3_SEL = 4 | ||
| 7165 | // .. ==> 0XF80007D4[7:5] = 0x00000004U | ||
| 7166 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 7167 | // .. Speed = 0 | ||
| 7168 | // .. ==> 0XF80007D4[8:8] = 0x00000000U | ||
| 7169 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 7170 | // .. IO_Type = 1 | ||
| 7171 | // .. ==> 0XF80007D4[11:9] = 0x00000001U | ||
| 7172 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 7173 | // .. PULLUP = 0 | ||
| 7174 | // .. ==> 0XF80007D4[12:12] = 0x00000000U | ||
| 7175 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 7176 | // .. DisableRcvr = 0 | ||
| 7177 | // .. ==> 0XF80007D4[13:13] = 0x00000000U | ||
| 7178 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 7179 | // .. | ||
| 7180 | EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), | ||
| 7181 | // .. SDIO0_WP_SEL = 55 | ||
| 7182 | // .. ==> 0XF8000830[5:0] = 0x00000037U | ||
| 7183 | // .. ==> MASK : 0x0000003FU VAL : 0x00000037U | ||
| 7184 | // .. SDIO0_CD_SEL = 47 | ||
| 7185 | // .. ==> 0XF8000830[21:16] = 0x0000002FU | ||
| 7186 | // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U | ||
| 7187 | // .. | ||
| 7188 | EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U), | ||
| 7189 | // .. FINISH: MIO PROGRAMMING | ||
| 7190 | // .. START: LOCK IT BACK | ||
| 7191 | // .. LOCK_KEY = 0X767B | ||
| 7192 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
| 7193 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
| 7194 | // .. | ||
| 7195 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
| 7196 | // .. FINISH: LOCK IT BACK | ||
| 7197 | // FINISH: top | ||
| 7198 | // | ||
| 7199 | EMIT_EXIT(), | ||
| 7200 | |||
| 7201 | // | ||
| 7202 | }; | ||
| 7203 | |||
| 7204 | unsigned long ps7_peripherals_init_data_2_0[] = { | ||
| 7205 | // START: top | ||
| 7206 | // .. START: SLCR SETTINGS | ||
| 7207 | // .. UNLOCK_KEY = 0XDF0D | ||
| 7208 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
| 7209 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
| 7210 | // .. | ||
| 7211 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
| 7212 | // .. FINISH: SLCR SETTINGS | ||
| 7213 | // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS | ||
| 7214 | // .. IBUF_DISABLE_MODE = 0x1 | ||
| 7215 | // .. ==> 0XF8000B48[7:7] = 0x00000001U | ||
| 7216 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
| 7217 | // .. TERM_DISABLE_MODE = 0x1 | ||
| 7218 | // .. ==> 0XF8000B48[8:8] = 0x00000001U | ||
| 7219 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 7220 | // .. | ||
| 7221 | EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), | ||
| 7222 | // .. IBUF_DISABLE_MODE = 0x1 | ||
| 7223 | // .. ==> 0XF8000B4C[7:7] = 0x00000001U | ||
| 7224 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
| 7225 | // .. TERM_DISABLE_MODE = 0x1 | ||
| 7226 | // .. ==> 0XF8000B4C[8:8] = 0x00000001U | ||
| 7227 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 7228 | // .. | ||
| 7229 | EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), | ||
| 7230 | // .. IBUF_DISABLE_MODE = 0x1 | ||
| 7231 | // .. ==> 0XF8000B50[7:7] = 0x00000001U | ||
| 7232 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
| 7233 | // .. TERM_DISABLE_MODE = 0x1 | ||
| 7234 | // .. ==> 0XF8000B50[8:8] = 0x00000001U | ||
| 7235 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 7236 | // .. | ||
| 7237 | EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), | ||
| 7238 | // .. IBUF_DISABLE_MODE = 0x1 | ||
| 7239 | // .. ==> 0XF8000B54[7:7] = 0x00000001U | ||
| 7240 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
| 7241 | // .. TERM_DISABLE_MODE = 0x1 | ||
| 7242 | // .. ==> 0XF8000B54[8:8] = 0x00000001U | ||
| 7243 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 7244 | // .. | ||
| 7245 | EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), | ||
| 7246 | // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS | ||
| 7247 | // .. START: LOCK IT BACK | ||
| 7248 | // .. LOCK_KEY = 0X767B | ||
| 7249 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
| 7250 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
| 7251 | // .. | ||
| 7252 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
| 7253 | // .. FINISH: LOCK IT BACK | ||
| 7254 | // .. START: SRAM/NOR SET OPMODE | ||
| 7255 | // .. FINISH: SRAM/NOR SET OPMODE | ||
| 7256 | // .. START: UART REGISTERS | ||
| 7257 | // .. BDIV = 0x6 | ||
| 7258 | // .. ==> 0XE0001034[7:0] = 0x00000006U | ||
| 7259 | // .. ==> MASK : 0x000000FFU VAL : 0x00000006U | ||
| 7260 | // .. | ||
| 7261 | EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), | ||
| 7262 | // .. CD = 0x3e | ||
| 7263 | // .. ==> 0XE0001018[15:0] = 0x0000003EU | ||
| 7264 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU | ||
| 7265 | // .. | ||
| 7266 | EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), | ||
| 7267 | // .. STPBRK = 0x0 | ||
| 7268 | // .. ==> 0XE0001000[8:8] = 0x00000000U | ||
| 7269 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 7270 | // .. STTBRK = 0x0 | ||
| 7271 | // .. ==> 0XE0001000[7:7] = 0x00000000U | ||
| 7272 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 7273 | // .. RSTTO = 0x0 | ||
| 7274 | // .. ==> 0XE0001000[6:6] = 0x00000000U | ||
| 7275 | // .. ==> MASK : 0x00000040U VAL : 0x00000000U | ||
| 7276 | // .. TXDIS = 0x0 | ||
| 7277 | // .. ==> 0XE0001000[5:5] = 0x00000000U | ||
| 7278 | // .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
| 7279 | // .. TXEN = 0x1 | ||
| 7280 | // .. ==> 0XE0001000[4:4] = 0x00000001U | ||
| 7281 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 7282 | // .. RXDIS = 0x0 | ||
| 7283 | // .. ==> 0XE0001000[3:3] = 0x00000000U | ||
| 7284 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 7285 | // .. RXEN = 0x1 | ||
| 7286 | // .. ==> 0XE0001000[2:2] = 0x00000001U | ||
| 7287 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 7288 | // .. TXRES = 0x1 | ||
| 7289 | // .. ==> 0XE0001000[1:1] = 0x00000001U | ||
| 7290 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 7291 | // .. RXRES = 0x1 | ||
| 7292 | // .. ==> 0XE0001000[0:0] = 0x00000001U | ||
| 7293 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 7294 | // .. | ||
| 7295 | EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), | ||
| 7296 | // .. IRMODE = 0x0 | ||
| 7297 | // .. ==> 0XE0001004[11:11] = 0x00000000U | ||
| 7298 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 7299 | // .. UCLKEN = 0x0 | ||
| 7300 | // .. ==> 0XE0001004[10:10] = 0x00000000U | ||
| 7301 | // .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 7302 | // .. CHMODE = 0x0 | ||
| 7303 | // .. ==> 0XE0001004[9:8] = 0x00000000U | ||
| 7304 | // .. ==> MASK : 0x00000300U VAL : 0x00000000U | ||
| 7305 | // .. NBSTOP = 0x0 | ||
| 7306 | // .. ==> 0XE0001004[7:6] = 0x00000000U | ||
| 7307 | // .. ==> MASK : 0x000000C0U VAL : 0x00000000U | ||
| 7308 | // .. PAR = 0x4 | ||
| 7309 | // .. ==> 0XE0001004[5:3] = 0x00000004U | ||
| 7310 | // .. ==> MASK : 0x00000038U VAL : 0x00000020U | ||
| 7311 | // .. CHRL = 0x0 | ||
| 7312 | // .. ==> 0XE0001004[2:1] = 0x00000000U | ||
| 7313 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
| 7314 | // .. CLKS = 0x0 | ||
| 7315 | // .. ==> 0XE0001004[0:0] = 0x00000000U | ||
| 7316 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 7317 | // .. | ||
| 7318 | EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), | ||
| 7319 | // .. FINISH: UART REGISTERS | ||
| 7320 | // .. START: TPIU WIDTH IN CASE OF EMIO | ||
| 7321 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
| 7322 | // .. .. a = 0XC5ACCE55 | ||
| 7323 | // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U | ||
| 7324 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
| 7325 | // .. .. | ||
| 7326 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
| 7327 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
| 7328 | // .. .. START: TRACE CURRENT PORT SIZE | ||
| 7329 | // .. .. a = 2 | ||
| 7330 | // .. .. ==> 0XF8803004[31:0] = 0x00000002U | ||
| 7331 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U | ||
| 7332 | // .. .. | ||
| 7333 | EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), | ||
| 7334 | // .. .. FINISH: TRACE CURRENT PORT SIZE | ||
| 7335 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
| 7336 | // .. .. a = 0X0 | ||
| 7337 | // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U | ||
| 7338 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
| 7339 | // .. .. | ||
| 7340 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), | ||
| 7341 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
| 7342 | // .. FINISH: TPIU WIDTH IN CASE OF EMIO | ||
| 7343 | // .. START: QSPI REGISTERS | ||
| 7344 | // .. Holdb_dr = 1 | ||
| 7345 | // .. ==> 0XE000D000[19:19] = 0x00000001U | ||
| 7346 | // .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
| 7347 | // .. | ||
| 7348 | EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), | ||
| 7349 | // .. FINISH: QSPI REGISTERS | ||
| 7350 | // .. START: PL POWER ON RESET REGISTERS | ||
| 7351 | // .. PCFG_POR_CNT_4K = 0 | ||
| 7352 | // .. ==> 0XF8007000[29:29] = 0x00000000U | ||
| 7353 | // .. ==> MASK : 0x20000000U VAL : 0x00000000U | ||
| 7354 | // .. | ||
| 7355 | EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), | ||
| 7356 | // .. FINISH: PL POWER ON RESET REGISTERS | ||
| 7357 | // .. START: SMC TIMING CALCULATION REGISTER UPDATE | ||
| 7358 | // .. .. START: NAND SET CYCLE | ||
| 7359 | // .. .. FINISH: NAND SET CYCLE | ||
| 7360 | // .. .. START: OPMODE | ||
| 7361 | // .. .. FINISH: OPMODE | ||
| 7362 | // .. .. START: DIRECT COMMAND | ||
| 7363 | // .. .. FINISH: DIRECT COMMAND | ||
| 7364 | // .. .. START: SRAM/NOR CS0 SET CYCLE | ||
| 7365 | // .. .. FINISH: SRAM/NOR CS0 SET CYCLE | ||
| 7366 | // .. .. START: DIRECT COMMAND | ||
| 7367 | // .. .. FINISH: DIRECT COMMAND | ||
| 7368 | // .. .. START: NOR CS0 BASE ADDRESS | ||
| 7369 | // .. .. FINISH: NOR CS0 BASE ADDRESS | ||
| 7370 | // .. .. START: SRAM/NOR CS1 SET CYCLE | ||
| 7371 | // .. .. FINISH: SRAM/NOR CS1 SET CYCLE | ||
| 7372 | // .. .. START: DIRECT COMMAND | ||
| 7373 | // .. .. FINISH: DIRECT COMMAND | ||
| 7374 | // .. .. START: NOR CS1 BASE ADDRESS | ||
| 7375 | // .. .. FINISH: NOR CS1 BASE ADDRESS | ||
| 7376 | // .. .. START: USB RESET | ||
| 7377 | // .. .. .. START: USB0 RESET | ||
| 7378 | // .. .. .. .. START: DIR MODE BANK 0 | ||
| 7379 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
| 7380 | // .. .. .. .. START: DIR MODE BANK 1 | ||
| 7381 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
| 7382 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7383 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7384 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7385 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7386 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7387 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7388 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7389 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7390 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
| 7391 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
| 7392 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
| 7393 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
| 7394 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 7395 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 7396 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 7397 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 7398 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 7399 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 7400 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 7401 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 7402 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 7403 | // .. .. .. .. | ||
| 7404 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 7405 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 7406 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7407 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7408 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7409 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7410 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7411 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7412 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7413 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7414 | // .. .. .. FINISH: USB0 RESET | ||
| 7415 | // .. .. .. START: USB1 RESET | ||
| 7416 | // .. .. .. .. START: DIR MODE BANK 0 | ||
| 7417 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
| 7418 | // .. .. .. .. START: DIR MODE BANK 1 | ||
| 7419 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
| 7420 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7421 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7422 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7423 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7424 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7425 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7426 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7427 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7428 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
| 7429 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
| 7430 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
| 7431 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
| 7432 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 7433 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 7434 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 7435 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 7436 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 7437 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 7438 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 7439 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 7440 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 7441 | // .. .. .. .. | ||
| 7442 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 7443 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 7444 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7445 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7446 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7447 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7448 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7449 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7450 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7451 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7452 | // .. .. .. FINISH: USB1 RESET | ||
| 7453 | // .. .. FINISH: USB RESET | ||
| 7454 | // .. .. START: ENET RESET | ||
| 7455 | // .. .. .. START: ENET0 RESET | ||
| 7456 | // .. .. .. .. START: DIR MODE BANK 0 | ||
| 7457 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
| 7458 | // .. .. .. .. START: DIR MODE BANK 1 | ||
| 7459 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
| 7460 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7461 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7462 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7463 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7464 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7465 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7466 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7467 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7468 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
| 7469 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
| 7470 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
| 7471 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
| 7472 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 7473 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 7474 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 7475 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 7476 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 7477 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 7478 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 7479 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 7480 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 7481 | // .. .. .. .. | ||
| 7482 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 7483 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 7484 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7485 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7486 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7487 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7488 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7489 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7490 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7491 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7492 | // .. .. .. FINISH: ENET0 RESET | ||
| 7493 | // .. .. .. START: ENET1 RESET | ||
| 7494 | // .. .. .. .. START: DIR MODE BANK 0 | ||
| 7495 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
| 7496 | // .. .. .. .. START: DIR MODE BANK 1 | ||
| 7497 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
| 7498 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7499 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7500 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7501 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7502 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7503 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7504 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7505 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7506 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
| 7507 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
| 7508 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
| 7509 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
| 7510 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 7511 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 7512 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 7513 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 7514 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 7515 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 7516 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 7517 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 7518 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 7519 | // .. .. .. .. | ||
| 7520 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 7521 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 7522 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7523 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7524 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7525 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7526 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7527 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7528 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7529 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7530 | // .. .. .. FINISH: ENET1 RESET | ||
| 7531 | // .. .. FINISH: ENET RESET | ||
| 7532 | // .. .. START: I2C RESET | ||
| 7533 | // .. .. .. START: I2C0 RESET | ||
| 7534 | // .. .. .. .. START: DIR MODE GPIO BANK0 | ||
| 7535 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | ||
| 7536 | // .. .. .. .. START: DIR MODE GPIO BANK1 | ||
| 7537 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | ||
| 7538 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7539 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7540 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7541 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7542 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7543 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7544 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7545 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7546 | // .. .. .. .. START: OUTPUT ENABLE | ||
| 7547 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
| 7548 | // .. .. .. .. START: OUTPUT ENABLE | ||
| 7549 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
| 7550 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 7551 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 7552 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 7553 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 7554 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 7555 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 7556 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 7557 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 7558 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 7559 | // .. .. .. .. | ||
| 7560 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 7561 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 7562 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7563 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7564 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7565 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7566 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7567 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7568 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7569 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7570 | // .. .. .. FINISH: I2C0 RESET | ||
| 7571 | // .. .. .. START: I2C1 RESET | ||
| 7572 | // .. .. .. .. START: DIR MODE GPIO BANK0 | ||
| 7573 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | ||
| 7574 | // .. .. .. .. START: DIR MODE GPIO BANK1 | ||
| 7575 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | ||
| 7576 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7577 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7578 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7579 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7580 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7581 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7582 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7583 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7584 | // .. .. .. .. START: OUTPUT ENABLE | ||
| 7585 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
| 7586 | // .. .. .. .. START: OUTPUT ENABLE | ||
| 7587 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
| 7588 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 7589 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 7590 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 7591 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 7592 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 7593 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 7594 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 7595 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 7596 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 7597 | // .. .. .. .. | ||
| 7598 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 7599 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 7600 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7601 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7602 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7603 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 7604 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7605 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 7606 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7607 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 7608 | // .. .. .. FINISH: I2C1 RESET | ||
| 7609 | // .. .. FINISH: I2C RESET | ||
| 7610 | // .. .. START: NOR CHIP SELECT | ||
| 7611 | // .. .. .. START: DIR MODE BANK 0 | ||
| 7612 | // .. .. .. FINISH: DIR MODE BANK 0 | ||
| 7613 | // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7614 | // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 7615 | // .. .. .. START: OUTPUT ENABLE BANK 0 | ||
| 7616 | // .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
| 7617 | // .. .. FINISH: NOR CHIP SELECT | ||
| 7618 | // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE | ||
| 7619 | // FINISH: top | ||
| 7620 | // | ||
| 7621 | EMIT_EXIT(), | ||
| 7622 | |||
| 7623 | // | ||
| 7624 | }; | ||
| 7625 | |||
| 7626 | unsigned long ps7_post_config_2_0[] = { | ||
| 7627 | // START: top | ||
| 7628 | // .. START: SLCR SETTINGS | ||
| 7629 | // .. UNLOCK_KEY = 0XDF0D | ||
| 7630 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
| 7631 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
| 7632 | // .. | ||
| 7633 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
| 7634 | // .. FINISH: SLCR SETTINGS | ||
| 7635 | // .. START: ENABLING LEVEL SHIFTER | ||
| 7636 | // .. USER_INP_ICT_EN_0 = 3 | ||
| 7637 | // .. ==> 0XF8000900[1:0] = 0x00000003U | ||
| 7638 | // .. ==> MASK : 0x00000003U VAL : 0x00000003U | ||
| 7639 | // .. USER_INP_ICT_EN_1 = 3 | ||
| 7640 | // .. ==> 0XF8000900[3:2] = 0x00000003U | ||
| 7641 | // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU | ||
| 7642 | // .. | ||
| 7643 | EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), | ||
| 7644 | // .. FINISH: ENABLING LEVEL SHIFTER | ||
| 7645 | // .. START: TPIU WIDTH IN CASE OF EMIO | ||
| 7646 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
| 7647 | // .. .. a = 0XC5ACCE55 | ||
| 7648 | // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U | ||
| 7649 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
| 7650 | // .. .. | ||
| 7651 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
| 7652 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
| 7653 | // .. .. START: TRACE CURRENT PORT SIZE | ||
| 7654 | // .. .. a = 2 | ||
| 7655 | // .. .. ==> 0XF8803004[31:0] = 0x00000002U | ||
| 7656 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U | ||
| 7657 | // .. .. | ||
| 7658 | EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), | ||
| 7659 | // .. .. FINISH: TRACE CURRENT PORT SIZE | ||
| 7660 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
| 7661 | // .. .. a = 0X0 | ||
| 7662 | // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U | ||
| 7663 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
| 7664 | // .. .. | ||
| 7665 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), | ||
| 7666 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
| 7667 | // .. FINISH: TPIU WIDTH IN CASE OF EMIO | ||
| 7668 | // .. START: FPGA RESETS TO 0 | ||
| 7669 | // .. reserved_3 = 0 | ||
| 7670 | // .. ==> 0XF8000240[31:25] = 0x00000000U | ||
| 7671 | // .. ==> MASK : 0xFE000000U VAL : 0x00000000U | ||
| 7672 | // .. FPGA_ACP_RST = 0 | ||
| 7673 | // .. ==> 0XF8000240[24:24] = 0x00000000U | ||
| 7674 | // .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
| 7675 | // .. FPGA_AXDS3_RST = 0 | ||
| 7676 | // .. ==> 0XF8000240[23:23] = 0x00000000U | ||
| 7677 | // .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
| 7678 | // .. FPGA_AXDS2_RST = 0 | ||
| 7679 | // .. ==> 0XF8000240[22:22] = 0x00000000U | ||
| 7680 | // .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
| 7681 | // .. FPGA_AXDS1_RST = 0 | ||
| 7682 | // .. ==> 0XF8000240[21:21] = 0x00000000U | ||
| 7683 | // .. ==> MASK : 0x00200000U VAL : 0x00000000U | ||
| 7684 | // .. FPGA_AXDS0_RST = 0 | ||
| 7685 | // .. ==> 0XF8000240[20:20] = 0x00000000U | ||
| 7686 | // .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
| 7687 | // .. reserved_2 = 0 | ||
| 7688 | // .. ==> 0XF8000240[19:18] = 0x00000000U | ||
| 7689 | // .. ==> MASK : 0x000C0000U VAL : 0x00000000U | ||
| 7690 | // .. FSSW1_FPGA_RST = 0 | ||
| 7691 | // .. ==> 0XF8000240[17:17] = 0x00000000U | ||
| 7692 | // .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 7693 | // .. FSSW0_FPGA_RST = 0 | ||
| 7694 | // .. ==> 0XF8000240[16:16] = 0x00000000U | ||
| 7695 | // .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 7696 | // .. reserved_1 = 0 | ||
| 7697 | // .. ==> 0XF8000240[15:14] = 0x00000000U | ||
| 7698 | // .. ==> MASK : 0x0000C000U VAL : 0x00000000U | ||
| 7699 | // .. FPGA_FMSW1_RST = 0 | ||
| 7700 | // .. ==> 0XF8000240[13:13] = 0x00000000U | ||
| 7701 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 7702 | // .. FPGA_FMSW0_RST = 0 | ||
| 7703 | // .. ==> 0XF8000240[12:12] = 0x00000000U | ||
| 7704 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 7705 | // .. FPGA_DMA3_RST = 0 | ||
| 7706 | // .. ==> 0XF8000240[11:11] = 0x00000000U | ||
| 7707 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 7708 | // .. FPGA_DMA2_RST = 0 | ||
| 7709 | // .. ==> 0XF8000240[10:10] = 0x00000000U | ||
| 7710 | // .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 7711 | // .. FPGA_DMA1_RST = 0 | ||
| 7712 | // .. ==> 0XF8000240[9:9] = 0x00000000U | ||
| 7713 | // .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
| 7714 | // .. FPGA_DMA0_RST = 0 | ||
| 7715 | // .. ==> 0XF8000240[8:8] = 0x00000000U | ||
| 7716 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 7717 | // .. reserved = 0 | ||
| 7718 | // .. ==> 0XF8000240[7:4] = 0x00000000U | ||
| 7719 | // .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
| 7720 | // .. FPGA3_OUT_RST = 0 | ||
| 7721 | // .. ==> 0XF8000240[3:3] = 0x00000000U | ||
| 7722 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 7723 | // .. FPGA2_OUT_RST = 0 | ||
| 7724 | // .. ==> 0XF8000240[2:2] = 0x00000000U | ||
| 7725 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 7726 | // .. FPGA1_OUT_RST = 0 | ||
| 7727 | // .. ==> 0XF8000240[1:1] = 0x00000000U | ||
| 7728 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 7729 | // .. FPGA0_OUT_RST = 0 | ||
| 7730 | // .. ==> 0XF8000240[0:0] = 0x00000000U | ||
| 7731 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 7732 | // .. | ||
| 7733 | EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), | ||
| 7734 | // .. FINISH: FPGA RESETS TO 0 | ||
| 7735 | // .. START: AFI REGISTERS | ||
| 7736 | // .. .. START: AFI0 REGISTERS | ||
| 7737 | // .. .. FINISH: AFI0 REGISTERS | ||
| 7738 | // .. .. START: AFI1 REGISTERS | ||
| 7739 | // .. .. FINISH: AFI1 REGISTERS | ||
| 7740 | // .. .. START: AFI2 REGISTERS | ||
| 7741 | // .. .. FINISH: AFI2 REGISTERS | ||
| 7742 | // .. .. START: AFI3 REGISTERS | ||
| 7743 | // .. .. FINISH: AFI3 REGISTERS | ||
| 7744 | // .. FINISH: AFI REGISTERS | ||
| 7745 | // .. START: LOCK IT BACK | ||
| 7746 | // .. LOCK_KEY = 0X767B | ||
| 7747 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
| 7748 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
| 7749 | // .. | ||
| 7750 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
| 7751 | // .. FINISH: LOCK IT BACK | ||
| 7752 | // FINISH: top | ||
| 7753 | // | ||
| 7754 | EMIT_EXIT(), | ||
| 7755 | |||
| 7756 | // | ||
| 7757 | }; | ||
| 7758 | |||
| 7759 | unsigned long ps7_debug_2_0[] = { | ||
| 7760 | // START: top | ||
| 7761 | // .. START: CROSS TRIGGER CONFIGURATIONS | ||
| 7762 | // .. .. START: UNLOCKING CTI REGISTERS | ||
| 7763 | // .. .. KEY = 0XC5ACCE55 | ||
| 7764 | // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U | ||
| 7765 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
| 7766 | // .. .. | ||
| 7767 | EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
| 7768 | // .. .. KEY = 0XC5ACCE55 | ||
| 7769 | // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U | ||
| 7770 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
| 7771 | // .. .. | ||
| 7772 | EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
| 7773 | // .. .. KEY = 0XC5ACCE55 | ||
| 7774 | // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U | ||
| 7775 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
| 7776 | // .. .. | ||
| 7777 | EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
| 7778 | // .. .. FINISH: UNLOCKING CTI REGISTERS | ||
| 7779 | // .. .. START: ENABLING CTI MODULES AND CHANNELS | ||
| 7780 | // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS | ||
| 7781 | // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS | ||
| 7782 | // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS | ||
| 7783 | // .. FINISH: CROSS TRIGGER CONFIGURATIONS | ||
| 7784 | // FINISH: top | ||
| 7785 | // | ||
| 7786 | EMIT_EXIT(), | ||
| 7787 | |||
| 7788 | // | ||
| 7789 | }; | ||
| 7790 | |||
| 7791 | unsigned long ps7_pll_init_data_1_0[] = { | ||
| 7792 | // START: top | ||
| 7793 | // .. START: SLCR SETTINGS | ||
| 7794 | // .. UNLOCK_KEY = 0XDF0D | ||
| 7795 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
| 7796 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
| 7797 | // .. | ||
| 7798 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
| 7799 | // .. FINISH: SLCR SETTINGS | ||
| 7800 | // .. START: PLL SLCR REGISTERS | ||
| 7801 | // .. .. START: ARM PLL INIT | ||
| 7802 | // .. .. PLL_RES = 0xc | ||
| 7803 | // .. .. ==> 0XF8000110[7:4] = 0x0000000CU | ||
| 7804 | // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U | ||
| 7805 | // .. .. PLL_CP = 0x2 | ||
| 7806 | // .. .. ==> 0XF8000110[11:8] = 0x00000002U | ||
| 7807 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
| 7808 | // .. .. LOCK_CNT = 0x177 | ||
| 7809 | // .. .. ==> 0XF8000110[21:12] = 0x00000177U | ||
| 7810 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U | ||
| 7811 | // .. .. | ||
| 7812 | EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U), | ||
| 7813 | // .. .. .. START: UPDATE FB_DIV | ||
| 7814 | // .. .. .. PLL_FDIV = 0x1a | ||
| 7815 | // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU | ||
| 7816 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U | ||
| 7817 | // .. .. .. | ||
| 7818 | EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U), | ||
| 7819 | // .. .. .. FINISH: UPDATE FB_DIV | ||
| 7820 | // .. .. .. START: BY PASS PLL | ||
| 7821 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
| 7822 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U | ||
| 7823 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 7824 | // .. .. .. | ||
| 7825 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), | ||
| 7826 | // .. .. .. FINISH: BY PASS PLL | ||
| 7827 | // .. .. .. START: ASSERT RESET | ||
| 7828 | // .. .. .. PLL_RESET = 1 | ||
| 7829 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U | ||
| 7830 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 7831 | // .. .. .. | ||
| 7832 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), | ||
| 7833 | // .. .. .. FINISH: ASSERT RESET | ||
| 7834 | // .. .. .. START: DEASSERT RESET | ||
| 7835 | // .. .. .. PLL_RESET = 0 | ||
| 7836 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U | ||
| 7837 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 7838 | // .. .. .. | ||
| 7839 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), | ||
| 7840 | // .. .. .. FINISH: DEASSERT RESET | ||
| 7841 | // .. .. .. START: CHECK PLL STATUS | ||
| 7842 | // .. .. .. ARM_PLL_LOCK = 1 | ||
| 7843 | // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U | ||
| 7844 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 7845 | // .. .. .. | ||
| 7846 | EMIT_MASKPOLL(0XF800010C, 0x00000001U), | ||
| 7847 | // .. .. .. FINISH: CHECK PLL STATUS | ||
| 7848 | // .. .. .. START: REMOVE PLL BY PASS | ||
| 7849 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
| 7850 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U | ||
| 7851 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 7852 | // .. .. .. | ||
| 7853 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), | ||
| 7854 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
| 7855 | // .. .. .. SRCSEL = 0x0 | ||
| 7856 | // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U | ||
| 7857 | // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 7858 | // .. .. .. DIVISOR = 0x2 | ||
| 7859 | // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U | ||
| 7860 | // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U | ||
| 7861 | // .. .. .. CPU_6OR4XCLKACT = 0x1 | ||
| 7862 | // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U | ||
| 7863 | // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U | ||
| 7864 | // .. .. .. CPU_3OR2XCLKACT = 0x1 | ||
| 7865 | // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U | ||
| 7866 | // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U | ||
| 7867 | // .. .. .. CPU_2XCLKACT = 0x1 | ||
| 7868 | // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U | ||
| 7869 | // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | ||
| 7870 | // .. .. .. CPU_1XCLKACT = 0x1 | ||
| 7871 | // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U | ||
| 7872 | // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | ||
| 7873 | // .. .. .. CPU_PERI_CLKACT = 0x1 | ||
| 7874 | // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U | ||
| 7875 | // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | ||
| 7876 | // .. .. .. | ||
| 7877 | EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), | ||
| 7878 | // .. .. FINISH: ARM PLL INIT | ||
| 7879 | // .. .. START: DDR PLL INIT | ||
| 7880 | // .. .. PLL_RES = 0xc | ||
| 7881 | // .. .. ==> 0XF8000114[7:4] = 0x0000000CU | ||
| 7882 | // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U | ||
| 7883 | // .. .. PLL_CP = 0x2 | ||
| 7884 | // .. .. ==> 0XF8000114[11:8] = 0x00000002U | ||
| 7885 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
| 7886 | // .. .. LOCK_CNT = 0x1db | ||
| 7887 | // .. .. ==> 0XF8000114[21:12] = 0x000001DBU | ||
| 7888 | // .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U | ||
| 7889 | // .. .. | ||
| 7890 | EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U), | ||
| 7891 | // .. .. .. START: UPDATE FB_DIV | ||
| 7892 | // .. .. .. PLL_FDIV = 0x15 | ||
| 7893 | // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U | ||
| 7894 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U | ||
| 7895 | // .. .. .. | ||
| 7896 | EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U), | ||
| 7897 | // .. .. .. FINISH: UPDATE FB_DIV | ||
| 7898 | // .. .. .. START: BY PASS PLL | ||
| 7899 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
| 7900 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U | ||
| 7901 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 7902 | // .. .. .. | ||
| 7903 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), | ||
| 7904 | // .. .. .. FINISH: BY PASS PLL | ||
| 7905 | // .. .. .. START: ASSERT RESET | ||
| 7906 | // .. .. .. PLL_RESET = 1 | ||
| 7907 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U | ||
| 7908 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 7909 | // .. .. .. | ||
| 7910 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), | ||
| 7911 | // .. .. .. FINISH: ASSERT RESET | ||
| 7912 | // .. .. .. START: DEASSERT RESET | ||
| 7913 | // .. .. .. PLL_RESET = 0 | ||
| 7914 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U | ||
| 7915 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 7916 | // .. .. .. | ||
| 7917 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), | ||
| 7918 | // .. .. .. FINISH: DEASSERT RESET | ||
| 7919 | // .. .. .. START: CHECK PLL STATUS | ||
| 7920 | // .. .. .. DDR_PLL_LOCK = 1 | ||
| 7921 | // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U | ||
| 7922 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 7923 | // .. .. .. | ||
| 7924 | EMIT_MASKPOLL(0XF800010C, 0x00000002U), | ||
| 7925 | // .. .. .. FINISH: CHECK PLL STATUS | ||
| 7926 | // .. .. .. START: REMOVE PLL BY PASS | ||
| 7927 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
| 7928 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U | ||
| 7929 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 7930 | // .. .. .. | ||
| 7931 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), | ||
| 7932 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
| 7933 | // .. .. .. DDR_3XCLKACT = 0x1 | ||
| 7934 | // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U | ||
| 7935 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 7936 | // .. .. .. DDR_2XCLKACT = 0x1 | ||
| 7937 | // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U | ||
| 7938 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 7939 | // .. .. .. DDR_3XCLK_DIVISOR = 0x2 | ||
| 7940 | // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U | ||
| 7941 | // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U | ||
| 7942 | // .. .. .. DDR_2XCLK_DIVISOR = 0x3 | ||
| 7943 | // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U | ||
| 7944 | // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U | ||
| 7945 | // .. .. .. | ||
| 7946 | EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), | ||
| 7947 | // .. .. FINISH: DDR PLL INIT | ||
| 7948 | // .. .. START: IO PLL INIT | ||
| 7949 | // .. .. PLL_RES = 0xc | ||
| 7950 | // .. .. ==> 0XF8000118[7:4] = 0x0000000CU | ||
| 7951 | // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U | ||
| 7952 | // .. .. PLL_CP = 0x2 | ||
| 7953 | // .. .. ==> 0XF8000118[11:8] = 0x00000002U | ||
| 7954 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
| 7955 | // .. .. LOCK_CNT = 0x1f4 | ||
| 7956 | // .. .. ==> 0XF8000118[21:12] = 0x000001F4U | ||
| 7957 | // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U | ||
| 7958 | // .. .. | ||
| 7959 | EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U), | ||
| 7960 | // .. .. .. START: UPDATE FB_DIV | ||
| 7961 | // .. .. .. PLL_FDIV = 0x14 | ||
| 7962 | // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U | ||
| 7963 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U | ||
| 7964 | // .. .. .. | ||
| 7965 | EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U), | ||
| 7966 | // .. .. .. FINISH: UPDATE FB_DIV | ||
| 7967 | // .. .. .. START: BY PASS PLL | ||
| 7968 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
| 7969 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U | ||
| 7970 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 7971 | // .. .. .. | ||
| 7972 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), | ||
| 7973 | // .. .. .. FINISH: BY PASS PLL | ||
| 7974 | // .. .. .. START: ASSERT RESET | ||
| 7975 | // .. .. .. PLL_RESET = 1 | ||
| 7976 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U | ||
| 7977 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 7978 | // .. .. .. | ||
| 7979 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), | ||
| 7980 | // .. .. .. FINISH: ASSERT RESET | ||
| 7981 | // .. .. .. START: DEASSERT RESET | ||
| 7982 | // .. .. .. PLL_RESET = 0 | ||
| 7983 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U | ||
| 7984 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 7985 | // .. .. .. | ||
| 7986 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), | ||
| 7987 | // .. .. .. FINISH: DEASSERT RESET | ||
| 7988 | // .. .. .. START: CHECK PLL STATUS | ||
| 7989 | // .. .. .. IO_PLL_LOCK = 1 | ||
| 7990 | // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U | ||
| 7991 | // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 7992 | // .. .. .. | ||
| 7993 | EMIT_MASKPOLL(0XF800010C, 0x00000004U), | ||
| 7994 | // .. .. .. FINISH: CHECK PLL STATUS | ||
| 7995 | // .. .. .. START: REMOVE PLL BY PASS | ||
| 7996 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
| 7997 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U | ||
| 7998 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 7999 | // .. .. .. | ||
| 8000 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), | ||
| 8001 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
| 8002 | // .. .. FINISH: IO PLL INIT | ||
| 8003 | // .. FINISH: PLL SLCR REGISTERS | ||
| 8004 | // .. START: LOCK IT BACK | ||
| 8005 | // .. LOCK_KEY = 0X767B | ||
| 8006 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
| 8007 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
| 8008 | // .. | ||
| 8009 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
| 8010 | // .. FINISH: LOCK IT BACK | ||
| 8011 | // FINISH: top | ||
| 8012 | // | ||
| 8013 | EMIT_EXIT(), | ||
| 8014 | |||
| 8015 | // | ||
| 8016 | }; | ||
| 8017 | |||
| 8018 | unsigned long ps7_clock_init_data_1_0[] = { | ||
| 8019 | // START: top | ||
| 8020 | // .. START: SLCR SETTINGS | ||
| 8021 | // .. UNLOCK_KEY = 0XDF0D | ||
| 8022 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
| 8023 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
| 8024 | // .. | ||
| 8025 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
| 8026 | // .. FINISH: SLCR SETTINGS | ||
| 8027 | // .. START: CLOCK CONTROL SLCR REGISTERS | ||
| 8028 | // .. CLKACT = 0x1 | ||
| 8029 | // .. ==> 0XF8000128[0:0] = 0x00000001U | ||
| 8030 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 8031 | // .. DIVISOR0 = 0x34 | ||
| 8032 | // .. ==> 0XF8000128[13:8] = 0x00000034U | ||
| 8033 | // .. ==> MASK : 0x00003F00U VAL : 0x00003400U | ||
| 8034 | // .. DIVISOR1 = 0x2 | ||
| 8035 | // .. ==> 0XF8000128[25:20] = 0x00000002U | ||
| 8036 | // .. ==> MASK : 0x03F00000U VAL : 0x00200000U | ||
| 8037 | // .. | ||
| 8038 | EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U), | ||
| 8039 | // .. CLKACT = 0x1 | ||
| 8040 | // .. ==> 0XF8000138[0:0] = 0x00000001U | ||
| 8041 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 8042 | // .. SRCSEL = 0x0 | ||
| 8043 | // .. ==> 0XF8000138[4:4] = 0x00000000U | ||
| 8044 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 8045 | // .. | ||
| 8046 | EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), | ||
| 8047 | // .. CLKACT = 0x1 | ||
| 8048 | // .. ==> 0XF8000140[0:0] = 0x00000001U | ||
| 8049 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 8050 | // .. SRCSEL = 0x0 | ||
| 8051 | // .. ==> 0XF8000140[6:4] = 0x00000000U | ||
| 8052 | // .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
| 8053 | // .. DIVISOR = 0x8 | ||
| 8054 | // .. ==> 0XF8000140[13:8] = 0x00000008U | ||
| 8055 | // .. ==> MASK : 0x00003F00U VAL : 0x00000800U | ||
| 8056 | // .. DIVISOR1 = 0x1 | ||
| 8057 | // .. ==> 0XF8000140[25:20] = 0x00000001U | ||
| 8058 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
| 8059 | // .. | ||
| 8060 | EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), | ||
| 8061 | // .. CLKACT = 0x1 | ||
| 8062 | // .. ==> 0XF800014C[0:0] = 0x00000001U | ||
| 8063 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 8064 | // .. SRCSEL = 0x0 | ||
| 8065 | // .. ==> 0XF800014C[5:4] = 0x00000000U | ||
| 8066 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 8067 | // .. DIVISOR = 0x5 | ||
| 8068 | // .. ==> 0XF800014C[13:8] = 0x00000005U | ||
| 8069 | // .. ==> MASK : 0x00003F00U VAL : 0x00000500U | ||
| 8070 | // .. | ||
| 8071 | EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), | ||
| 8072 | // .. CLKACT0 = 0x1 | ||
| 8073 | // .. ==> 0XF8000150[0:0] = 0x00000001U | ||
| 8074 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 8075 | // .. CLKACT1 = 0x0 | ||
| 8076 | // .. ==> 0XF8000150[1:1] = 0x00000000U | ||
| 8077 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 8078 | // .. SRCSEL = 0x0 | ||
| 8079 | // .. ==> 0XF8000150[5:4] = 0x00000000U | ||
| 8080 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 8081 | // .. DIVISOR = 0x14 | ||
| 8082 | // .. ==> 0XF8000150[13:8] = 0x00000014U | ||
| 8083 | // .. ==> MASK : 0x00003F00U VAL : 0x00001400U | ||
| 8084 | // .. | ||
| 8085 | EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), | ||
| 8086 | // .. CLKACT0 = 0x0 | ||
| 8087 | // .. ==> 0XF8000154[0:0] = 0x00000000U | ||
| 8088 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 8089 | // .. CLKACT1 = 0x1 | ||
| 8090 | // .. ==> 0XF8000154[1:1] = 0x00000001U | ||
| 8091 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 8092 | // .. SRCSEL = 0x0 | ||
| 8093 | // .. ==> 0XF8000154[5:4] = 0x00000000U | ||
| 8094 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 8095 | // .. DIVISOR = 0x14 | ||
| 8096 | // .. ==> 0XF8000154[13:8] = 0x00000014U | ||
| 8097 | // .. ==> MASK : 0x00003F00U VAL : 0x00001400U | ||
| 8098 | // .. | ||
| 8099 | EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), | ||
| 8100 | // .. .. START: TRACE CLOCK | ||
| 8101 | // .. .. FINISH: TRACE CLOCK | ||
| 8102 | // .. .. CLKACT = 0x1 | ||
| 8103 | // .. .. ==> 0XF8000168[0:0] = 0x00000001U | ||
| 8104 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 8105 | // .. .. SRCSEL = 0x0 | ||
| 8106 | // .. .. ==> 0XF8000168[5:4] = 0x00000000U | ||
| 8107 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 8108 | // .. .. DIVISOR = 0x5 | ||
| 8109 | // .. .. ==> 0XF8000168[13:8] = 0x00000005U | ||
| 8110 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U | ||
| 8111 | // .. .. | ||
| 8112 | EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), | ||
| 8113 | // .. .. SRCSEL = 0x0 | ||
| 8114 | // .. .. ==> 0XF8000170[5:4] = 0x00000000U | ||
| 8115 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 8116 | // .. .. DIVISOR0 = 0xa | ||
| 8117 | // .. .. ==> 0XF8000170[13:8] = 0x0000000AU | ||
| 8118 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | ||
| 8119 | // .. .. DIVISOR1 = 0x1 | ||
| 8120 | // .. .. ==> 0XF8000170[25:20] = 0x00000001U | ||
| 8121 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
| 8122 | // .. .. | ||
| 8123 | EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), | ||
| 8124 | // .. .. SRCSEL = 0x3 | ||
| 8125 | // .. .. ==> 0XF8000180[5:4] = 0x00000003U | ||
| 8126 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000030U | ||
| 8127 | // .. .. DIVISOR0 = 0x6 | ||
| 8128 | // .. .. ==> 0XF8000180[13:8] = 0x00000006U | ||
| 8129 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U | ||
| 8130 | // .. .. DIVISOR1 = 0x1 | ||
| 8131 | // .. .. ==> 0XF8000180[25:20] = 0x00000001U | ||
| 8132 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
| 8133 | // .. .. | ||
| 8134 | EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100630U), | ||
| 8135 | // .. .. SRCSEL = 0x2 | ||
| 8136 | // .. .. ==> 0XF8000190[5:4] = 0x00000002U | ||
| 8137 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000020U | ||
| 8138 | // .. .. DIVISOR0 = 0x35 | ||
| 8139 | // .. .. ==> 0XF8000190[13:8] = 0x00000035U | ||
| 8140 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U | ||
| 8141 | // .. .. DIVISOR1 = 0x2 | ||
| 8142 | // .. .. ==> 0XF8000190[25:20] = 0x00000002U | ||
| 8143 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U | ||
| 8144 | // .. .. | ||
| 8145 | EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00203520U), | ||
| 8146 | // .. .. SRCSEL = 0x0 | ||
| 8147 | // .. .. ==> 0XF80001A0[5:4] = 0x00000000U | ||
| 8148 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
| 8149 | // .. .. DIVISOR0 = 0xa | ||
| 8150 | // .. .. ==> 0XF80001A0[13:8] = 0x0000000AU | ||
| 8151 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | ||
| 8152 | // .. .. DIVISOR1 = 0x1 | ||
| 8153 | // .. .. ==> 0XF80001A0[25:20] = 0x00000001U | ||
| 8154 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
| 8155 | // .. .. | ||
| 8156 | EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100A00U), | ||
| 8157 | // .. .. CLK_621_TRUE = 0x1 | ||
| 8158 | // .. .. ==> 0XF80001C4[0:0] = 0x00000001U | ||
| 8159 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 8160 | // .. .. | ||
| 8161 | EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), | ||
| 8162 | // .. .. DMA_CPU_2XCLKACT = 0x1 | ||
| 8163 | // .. .. ==> 0XF800012C[0:0] = 0x00000001U | ||
| 8164 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 8165 | // .. .. USB0_CPU_1XCLKACT = 0x1 | ||
| 8166 | // .. .. ==> 0XF800012C[2:2] = 0x00000001U | ||
| 8167 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 8168 | // .. .. USB1_CPU_1XCLKACT = 0x1 | ||
| 8169 | // .. .. ==> 0XF800012C[3:3] = 0x00000001U | ||
| 8170 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U | ||
| 8171 | // .. .. GEM0_CPU_1XCLKACT = 0x1 | ||
| 8172 | // .. .. ==> 0XF800012C[6:6] = 0x00000001U | ||
| 8173 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U | ||
| 8174 | // .. .. GEM1_CPU_1XCLKACT = 0x0 | ||
| 8175 | // .. .. ==> 0XF800012C[7:7] = 0x00000000U | ||
| 8176 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 8177 | // .. .. SDI0_CPU_1XCLKACT = 0x1 | ||
| 8178 | // .. .. ==> 0XF800012C[10:10] = 0x00000001U | ||
| 8179 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U | ||
| 8180 | // .. .. SDI1_CPU_1XCLKACT = 0x0 | ||
| 8181 | // .. .. ==> 0XF800012C[11:11] = 0x00000000U | ||
| 8182 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 8183 | // .. .. SPI0_CPU_1XCLKACT = 0x0 | ||
| 8184 | // .. .. ==> 0XF800012C[14:14] = 0x00000000U | ||
| 8185 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
| 8186 | // .. .. SPI1_CPU_1XCLKACT = 0x0 | ||
| 8187 | // .. .. ==> 0XF800012C[15:15] = 0x00000000U | ||
| 8188 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
| 8189 | // .. .. CAN0_CPU_1XCLKACT = 0x0 | ||
| 8190 | // .. .. ==> 0XF800012C[16:16] = 0x00000000U | ||
| 8191 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 8192 | // .. .. CAN1_CPU_1XCLKACT = 0x0 | ||
| 8193 | // .. .. ==> 0XF800012C[17:17] = 0x00000000U | ||
| 8194 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 8195 | // .. .. I2C0_CPU_1XCLKACT = 0x1 | ||
| 8196 | // .. .. ==> 0XF800012C[18:18] = 0x00000001U | ||
| 8197 | // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U | ||
| 8198 | // .. .. I2C1_CPU_1XCLKACT = 0x1 | ||
| 8199 | // .. .. ==> 0XF800012C[19:19] = 0x00000001U | ||
| 8200 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
| 8201 | // .. .. UART0_CPU_1XCLKACT = 0x0 | ||
| 8202 | // .. .. ==> 0XF800012C[20:20] = 0x00000000U | ||
| 8203 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
| 8204 | // .. .. UART1_CPU_1XCLKACT = 0x1 | ||
| 8205 | // .. .. ==> 0XF800012C[21:21] = 0x00000001U | ||
| 8206 | // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U | ||
| 8207 | // .. .. GPIO_CPU_1XCLKACT = 0x1 | ||
| 8208 | // .. .. ==> 0XF800012C[22:22] = 0x00000001U | ||
| 8209 | // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U | ||
| 8210 | // .. .. LQSPI_CPU_1XCLKACT = 0x1 | ||
| 8211 | // .. .. ==> 0XF800012C[23:23] = 0x00000001U | ||
| 8212 | // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U | ||
| 8213 | // .. .. SMC_CPU_1XCLKACT = 0x1 | ||
| 8214 | // .. .. ==> 0XF800012C[24:24] = 0x00000001U | ||
| 8215 | // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U | ||
| 8216 | // .. .. | ||
| 8217 | EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), | ||
| 8218 | // .. FINISH: CLOCK CONTROL SLCR REGISTERS | ||
| 8219 | // .. START: THIS SHOULD BE BLANK | ||
| 8220 | // .. FINISH: THIS SHOULD BE BLANK | ||
| 8221 | // .. START: LOCK IT BACK | ||
| 8222 | // .. LOCK_KEY = 0X767B | ||
| 8223 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
| 8224 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
| 8225 | // .. | ||
| 8226 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
| 8227 | // .. FINISH: LOCK IT BACK | ||
| 8228 | // FINISH: top | ||
| 8229 | // | ||
| 8230 | EMIT_EXIT(), | ||
| 8231 | |||
| 8232 | // | ||
| 8233 | }; | ||
| 8234 | |||
| 8235 | unsigned long ps7_ddr_init_data_1_0[] = { | ||
| 8236 | // START: top | ||
| 8237 | // .. START: DDR INITIALIZATION | ||
| 8238 | // .. .. START: LOCK DDR | ||
| 8239 | // .. .. reg_ddrc_soft_rstb = 0 | ||
| 8240 | // .. .. ==> 0XF8006000[0:0] = 0x00000000U | ||
| 8241 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 8242 | // .. .. reg_ddrc_powerdown_en = 0x0 | ||
| 8243 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | ||
| 8244 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 8245 | // .. .. reg_ddrc_data_bus_width = 0x0 | ||
| 8246 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | ||
| 8247 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | ||
| 8248 | // .. .. reg_ddrc_burst8_refresh = 0x0 | ||
| 8249 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | ||
| 8250 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
| 8251 | // .. .. reg_ddrc_rdwr_idle_gap = 0x1 | ||
| 8252 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | ||
| 8253 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | ||
| 8254 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | ||
| 8255 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | ||
| 8256 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
| 8257 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | ||
| 8258 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | ||
| 8259 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
| 8260 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | ||
| 8261 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | ||
| 8262 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 8263 | // .. .. | ||
| 8264 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), | ||
| 8265 | // .. .. FINISH: LOCK DDR | ||
| 8266 | // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f | ||
| 8267 | // .. .. ==> 0XF8006004[11:0] = 0x0000007FU | ||
| 8268 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU | ||
| 8269 | // .. .. reg_ddrc_active_ranks = 0x1 | ||
| 8270 | // .. .. ==> 0XF8006004[13:12] = 0x00000001U | ||
| 8271 | // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U | ||
| 8272 | // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 | ||
| 8273 | // .. .. ==> 0XF8006004[18:14] = 0x00000000U | ||
| 8274 | // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U | ||
| 8275 | // .. .. reg_ddrc_wr_odt_block = 0x1 | ||
| 8276 | // .. .. ==> 0XF8006004[20:19] = 0x00000001U | ||
| 8277 | // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U | ||
| 8278 | // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 | ||
| 8279 | // .. .. ==> 0XF8006004[21:21] = 0x00000000U | ||
| 8280 | // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U | ||
| 8281 | // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 | ||
| 8282 | // .. .. ==> 0XF8006004[26:22] = 0x00000000U | ||
| 8283 | // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U | ||
| 8284 | // .. .. reg_ddrc_addrmap_open_bank = 0x0 | ||
| 8285 | // .. .. ==> 0XF8006004[27:27] = 0x00000000U | ||
| 8286 | // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U | ||
| 8287 | // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 | ||
| 8288 | // .. .. ==> 0XF8006004[28:28] = 0x00000000U | ||
| 8289 | // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U | ||
| 8290 | // .. .. | ||
| 8291 | EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x0008107FU), | ||
| 8292 | // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf | ||
| 8293 | // .. .. ==> 0XF8006008[10:0] = 0x0000000FU | ||
| 8294 | // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU | ||
| 8295 | // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf | ||
| 8296 | // .. .. ==> 0XF8006008[21:11] = 0x0000000FU | ||
| 8297 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U | ||
| 8298 | // .. .. reg_ddrc_hpr_xact_run_length = 0xf | ||
| 8299 | // .. .. ==> 0XF8006008[25:22] = 0x0000000FU | ||
| 8300 | // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U | ||
| 8301 | // .. .. | ||
| 8302 | EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), | ||
| 8303 | // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 | ||
| 8304 | // .. .. ==> 0XF800600C[10:0] = 0x00000001U | ||
| 8305 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | ||
| 8306 | // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 | ||
| 8307 | // .. .. ==> 0XF800600C[21:11] = 0x00000002U | ||
| 8308 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U | ||
| 8309 | // .. .. reg_ddrc_lpr_xact_run_length = 0x8 | ||
| 8310 | // .. .. ==> 0XF800600C[25:22] = 0x00000008U | ||
| 8311 | // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U | ||
| 8312 | // .. .. | ||
| 8313 | EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), | ||
| 8314 | // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 | ||
| 8315 | // .. .. ==> 0XF8006010[10:0] = 0x00000001U | ||
| 8316 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | ||
| 8317 | // .. .. reg_ddrc_w_xact_run_length = 0x8 | ||
| 8318 | // .. .. ==> 0XF8006010[14:11] = 0x00000008U | ||
| 8319 | // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U | ||
| 8320 | // .. .. reg_ddrc_w_max_starve_x32 = 0x2 | ||
| 8321 | // .. .. ==> 0XF8006010[25:15] = 0x00000002U | ||
| 8322 | // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U | ||
| 8323 | // .. .. | ||
| 8324 | EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), | ||
| 8325 | // .. .. reg_ddrc_t_rc = 0x1a | ||
| 8326 | // .. .. ==> 0XF8006014[5:0] = 0x0000001AU | ||
| 8327 | // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU | ||
| 8328 | // .. .. reg_ddrc_t_rfc_min = 0x54 | ||
| 8329 | // .. .. ==> 0XF8006014[13:6] = 0x00000054U | ||
| 8330 | // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U | ||
| 8331 | // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 | ||
| 8332 | // .. .. ==> 0XF8006014[20:14] = 0x00000010U | ||
| 8333 | // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U | ||
| 8334 | // .. .. | ||
| 8335 | EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU), | ||
| 8336 | // .. .. reg_ddrc_wr2pre = 0x12 | ||
| 8337 | // .. .. ==> 0XF8006018[4:0] = 0x00000012U | ||
| 8338 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U | ||
| 8339 | // .. .. reg_ddrc_powerdown_to_x32 = 0x6 | ||
| 8340 | // .. .. ==> 0XF8006018[9:5] = 0x00000006U | ||
| 8341 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U | ||
| 8342 | // .. .. reg_ddrc_t_faw = 0x15 | ||
| 8343 | // .. .. ==> 0XF8006018[15:10] = 0x00000015U | ||
| 8344 | // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U | ||
| 8345 | // .. .. reg_ddrc_t_ras_max = 0x23 | ||
| 8346 | // .. .. ==> 0XF8006018[21:16] = 0x00000023U | ||
| 8347 | // .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U | ||
| 8348 | // .. .. reg_ddrc_t_ras_min = 0x13 | ||
| 8349 | // .. .. ==> 0XF8006018[26:22] = 0x00000013U | ||
| 8350 | // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U | ||
| 8351 | // .. .. reg_ddrc_t_cke = 0x4 | ||
| 8352 | // .. .. ==> 0XF8006018[31:28] = 0x00000004U | ||
| 8353 | // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U | ||
| 8354 | // .. .. | ||
| 8355 | EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U), | ||
| 8356 | // .. .. reg_ddrc_write_latency = 0x5 | ||
| 8357 | // .. .. ==> 0XF800601C[4:0] = 0x00000005U | ||
| 8358 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U | ||
| 8359 | // .. .. reg_ddrc_rd2wr = 0x7 | ||
| 8360 | // .. .. ==> 0XF800601C[9:5] = 0x00000007U | ||
| 8361 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U | ||
| 8362 | // .. .. reg_ddrc_wr2rd = 0xe | ||
| 8363 | // .. .. ==> 0XF800601C[14:10] = 0x0000000EU | ||
| 8364 | // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U | ||
| 8365 | // .. .. reg_ddrc_t_xp = 0x4 | ||
| 8366 | // .. .. ==> 0XF800601C[19:15] = 0x00000004U | ||
| 8367 | // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U | ||
| 8368 | // .. .. reg_ddrc_pad_pd = 0x0 | ||
| 8369 | // .. .. ==> 0XF800601C[22:20] = 0x00000000U | ||
| 8370 | // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U | ||
| 8371 | // .. .. reg_ddrc_rd2pre = 0x4 | ||
| 8372 | // .. .. ==> 0XF800601C[27:23] = 0x00000004U | ||
| 8373 | // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U | ||
| 8374 | // .. .. reg_ddrc_t_rcd = 0x7 | ||
| 8375 | // .. .. ==> 0XF800601C[31:28] = 0x00000007U | ||
| 8376 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | ||
| 8377 | // .. .. | ||
| 8378 | EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), | ||
| 8379 | // .. .. reg_ddrc_t_ccd = 0x4 | ||
| 8380 | // .. .. ==> 0XF8006020[4:2] = 0x00000004U | ||
| 8381 | // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U | ||
| 8382 | // .. .. reg_ddrc_t_rrd = 0x6 | ||
| 8383 | // .. .. ==> 0XF8006020[7:5] = 0x00000006U | ||
| 8384 | // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U | ||
| 8385 | // .. .. reg_ddrc_refresh_margin = 0x2 | ||
| 8386 | // .. .. ==> 0XF8006020[11:8] = 0x00000002U | ||
| 8387 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
| 8388 | // .. .. reg_ddrc_t_rp = 0x7 | ||
| 8389 | // .. .. ==> 0XF8006020[15:12] = 0x00000007U | ||
| 8390 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U | ||
| 8391 | // .. .. reg_ddrc_refresh_to_x32 = 0x8 | ||
| 8392 | // .. .. ==> 0XF8006020[20:16] = 0x00000008U | ||
| 8393 | // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U | ||
| 8394 | // .. .. reg_ddrc_sdram = 0x1 | ||
| 8395 | // .. .. ==> 0XF8006020[21:21] = 0x00000001U | ||
| 8396 | // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U | ||
| 8397 | // .. .. reg_ddrc_mobile = 0x0 | ||
| 8398 | // .. .. ==> 0XF8006020[22:22] = 0x00000000U | ||
| 8399 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
| 8400 | // .. .. reg_ddrc_clock_stop_en = 0x0 | ||
| 8401 | // .. .. ==> 0XF8006020[23:23] = 0x00000000U | ||
| 8402 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
| 8403 | // .. .. reg_ddrc_read_latency = 0x7 | ||
| 8404 | // .. .. ==> 0XF8006020[28:24] = 0x00000007U | ||
| 8405 | // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U | ||
| 8406 | // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 | ||
| 8407 | // .. .. ==> 0XF8006020[29:29] = 0x00000001U | ||
| 8408 | // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U | ||
| 8409 | // .. .. reg_ddrc_dis_pad_pd = 0x0 | ||
| 8410 | // .. .. ==> 0XF8006020[30:30] = 0x00000000U | ||
| 8411 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | ||
| 8412 | // .. .. reg_ddrc_loopback = 0x0 | ||
| 8413 | // .. .. ==> 0XF8006020[31:31] = 0x00000000U | ||
| 8414 | // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U | ||
| 8415 | // .. .. | ||
| 8416 | EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), | ||
| 8417 | // .. .. reg_ddrc_en_2t_timing_mode = 0x0 | ||
| 8418 | // .. .. ==> 0XF8006024[0:0] = 0x00000000U | ||
| 8419 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 8420 | // .. .. reg_ddrc_prefer_write = 0x0 | ||
| 8421 | // .. .. ==> 0XF8006024[1:1] = 0x00000000U | ||
| 8422 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 8423 | // .. .. reg_ddrc_max_rank_rd = 0xf | ||
| 8424 | // .. .. ==> 0XF8006024[5:2] = 0x0000000FU | ||
| 8425 | // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU | ||
| 8426 | // .. .. reg_ddrc_mr_wr = 0x0 | ||
| 8427 | // .. .. ==> 0XF8006024[6:6] = 0x00000000U | ||
| 8428 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U | ||
| 8429 | // .. .. reg_ddrc_mr_addr = 0x0 | ||
| 8430 | // .. .. ==> 0XF8006024[8:7] = 0x00000000U | ||
| 8431 | // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U | ||
| 8432 | // .. .. reg_ddrc_mr_data = 0x0 | ||
| 8433 | // .. .. ==> 0XF8006024[24:9] = 0x00000000U | ||
| 8434 | // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U | ||
| 8435 | // .. .. ddrc_reg_mr_wr_busy = 0x0 | ||
| 8436 | // .. .. ==> 0XF8006024[25:25] = 0x00000000U | ||
| 8437 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
| 8438 | // .. .. reg_ddrc_mr_type = 0x0 | ||
| 8439 | // .. .. ==> 0XF8006024[26:26] = 0x00000000U | ||
| 8440 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | ||
| 8441 | // .. .. reg_ddrc_mr_rdata_valid = 0x0 | ||
| 8442 | // .. .. ==> 0XF8006024[27:27] = 0x00000000U | ||
| 8443 | // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U | ||
| 8444 | // .. .. | ||
| 8445 | EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), | ||
| 8446 | // .. .. reg_ddrc_final_wait_x32 = 0x7 | ||
| 8447 | // .. .. ==> 0XF8006028[6:0] = 0x00000007U | ||
| 8448 | // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U | ||
| 8449 | // .. .. reg_ddrc_pre_ocd_x32 = 0x0 | ||
| 8450 | // .. .. ==> 0XF8006028[10:7] = 0x00000000U | ||
| 8451 | // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U | ||
| 8452 | // .. .. reg_ddrc_t_mrd = 0x4 | ||
| 8453 | // .. .. ==> 0XF8006028[13:11] = 0x00000004U | ||
| 8454 | // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U | ||
| 8455 | // .. .. | ||
| 8456 | EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), | ||
| 8457 | // .. .. reg_ddrc_emr2 = 0x8 | ||
| 8458 | // .. .. ==> 0XF800602C[15:0] = 0x00000008U | ||
| 8459 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U | ||
| 8460 | // .. .. reg_ddrc_emr3 = 0x0 | ||
| 8461 | // .. .. ==> 0XF800602C[31:16] = 0x00000000U | ||
| 8462 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U | ||
| 8463 | // .. .. | ||
| 8464 | EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), | ||
| 8465 | // .. .. reg_ddrc_mr = 0x930 | ||
| 8466 | // .. .. ==> 0XF8006030[15:0] = 0x00000930U | ||
| 8467 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U | ||
| 8468 | // .. .. reg_ddrc_emr = 0x4 | ||
| 8469 | // .. .. ==> 0XF8006030[31:16] = 0x00000004U | ||
| 8470 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U | ||
| 8471 | // .. .. | ||
| 8472 | EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), | ||
| 8473 | // .. .. reg_ddrc_burst_rdwr = 0x4 | ||
| 8474 | // .. .. ==> 0XF8006034[3:0] = 0x00000004U | ||
| 8475 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U | ||
| 8476 | // .. .. reg_ddrc_pre_cke_x1024 = 0x101 | ||
| 8477 | // .. .. ==> 0XF8006034[13:4] = 0x00000101U | ||
| 8478 | // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U | ||
| 8479 | // .. .. reg_ddrc_post_cke_x1024 = 0x1 | ||
| 8480 | // .. .. ==> 0XF8006034[25:16] = 0x00000001U | ||
| 8481 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U | ||
| 8482 | // .. .. reg_ddrc_burstchop = 0x0 | ||
| 8483 | // .. .. ==> 0XF8006034[28:28] = 0x00000000U | ||
| 8484 | // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U | ||
| 8485 | // .. .. | ||
| 8486 | EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011014U), | ||
| 8487 | // .. .. reg_ddrc_force_low_pri_n = 0x0 | ||
| 8488 | // .. .. ==> 0XF8006038[0:0] = 0x00000000U | ||
| 8489 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 8490 | // .. .. reg_ddrc_dis_dq = 0x0 | ||
| 8491 | // .. .. ==> 0XF8006038[1:1] = 0x00000000U | ||
| 8492 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 8493 | // .. .. reg_phy_debug_mode = 0x0 | ||
| 8494 | // .. .. ==> 0XF8006038[6:6] = 0x00000000U | ||
| 8495 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U | ||
| 8496 | // .. .. reg_phy_wr_level_start = 0x0 | ||
| 8497 | // .. .. ==> 0XF8006038[7:7] = 0x00000000U | ||
| 8498 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 8499 | // .. .. reg_phy_rd_level_start = 0x0 | ||
| 8500 | // .. .. ==> 0XF8006038[8:8] = 0x00000000U | ||
| 8501 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 8502 | // .. .. reg_phy_dq0_wait_t = 0x0 | ||
| 8503 | // .. .. ==> 0XF8006038[12:9] = 0x00000000U | ||
| 8504 | // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U | ||
| 8505 | // .. .. | ||
| 8506 | EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), | ||
| 8507 | // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 | ||
| 8508 | // .. .. ==> 0XF800603C[3:0] = 0x00000007U | ||
| 8509 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U | ||
| 8510 | // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 | ||
| 8511 | // .. .. ==> 0XF800603C[7:4] = 0x00000007U | ||
| 8512 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U | ||
| 8513 | // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 | ||
| 8514 | // .. .. ==> 0XF800603C[11:8] = 0x00000007U | ||
| 8515 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U | ||
| 8516 | // .. .. reg_ddrc_addrmap_col_b5 = 0x0 | ||
| 8517 | // .. .. ==> 0XF800603C[15:12] = 0x00000000U | ||
| 8518 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | ||
| 8519 | // .. .. reg_ddrc_addrmap_col_b6 = 0x0 | ||
| 8520 | // .. .. ==> 0XF800603C[19:16] = 0x00000000U | ||
| 8521 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | ||
| 8522 | // .. .. | ||
| 8523 | EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), | ||
| 8524 | // .. .. reg_ddrc_addrmap_col_b2 = 0x0 | ||
| 8525 | // .. .. ==> 0XF8006040[3:0] = 0x00000000U | ||
| 8526 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
| 8527 | // .. .. reg_ddrc_addrmap_col_b3 = 0x0 | ||
| 8528 | // .. .. ==> 0XF8006040[7:4] = 0x00000000U | ||
| 8529 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
| 8530 | // .. .. reg_ddrc_addrmap_col_b4 = 0x0 | ||
| 8531 | // .. .. ==> 0XF8006040[11:8] = 0x00000000U | ||
| 8532 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | ||
| 8533 | // .. .. reg_ddrc_addrmap_col_b7 = 0x0 | ||
| 8534 | // .. .. ==> 0XF8006040[15:12] = 0x00000000U | ||
| 8535 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | ||
| 8536 | // .. .. reg_ddrc_addrmap_col_b8 = 0x0 | ||
| 8537 | // .. .. ==> 0XF8006040[19:16] = 0x00000000U | ||
| 8538 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | ||
| 8539 | // .. .. reg_ddrc_addrmap_col_b9 = 0xf | ||
| 8540 | // .. .. ==> 0XF8006040[23:20] = 0x0000000FU | ||
| 8541 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U | ||
| 8542 | // .. .. reg_ddrc_addrmap_col_b10 = 0xf | ||
| 8543 | // .. .. ==> 0XF8006040[27:24] = 0x0000000FU | ||
| 8544 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | ||
| 8545 | // .. .. reg_ddrc_addrmap_col_b11 = 0xf | ||
| 8546 | // .. .. ==> 0XF8006040[31:28] = 0x0000000FU | ||
| 8547 | // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U | ||
| 8548 | // .. .. | ||
| 8549 | EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), | ||
| 8550 | // .. .. reg_ddrc_addrmap_row_b0 = 0x6 | ||
| 8551 | // .. .. ==> 0XF8006044[3:0] = 0x00000006U | ||
| 8552 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U | ||
| 8553 | // .. .. reg_ddrc_addrmap_row_b1 = 0x6 | ||
| 8554 | // .. .. ==> 0XF8006044[7:4] = 0x00000006U | ||
| 8555 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U | ||
| 8556 | // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 | ||
| 8557 | // .. .. ==> 0XF8006044[11:8] = 0x00000006U | ||
| 8558 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U | ||
| 8559 | // .. .. reg_ddrc_addrmap_row_b12 = 0x6 | ||
| 8560 | // .. .. ==> 0XF8006044[15:12] = 0x00000006U | ||
| 8561 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U | ||
| 8562 | // .. .. reg_ddrc_addrmap_row_b13 = 0x6 | ||
| 8563 | // .. .. ==> 0XF8006044[19:16] = 0x00000006U | ||
| 8564 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U | ||
| 8565 | // .. .. reg_ddrc_addrmap_row_b14 = 0xf | ||
| 8566 | // .. .. ==> 0XF8006044[23:20] = 0x0000000FU | ||
| 8567 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U | ||
| 8568 | // .. .. reg_ddrc_addrmap_row_b15 = 0xf | ||
| 8569 | // .. .. ==> 0XF8006044[27:24] = 0x0000000FU | ||
| 8570 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | ||
| 8571 | // .. .. | ||
| 8572 | EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U), | ||
| 8573 | // .. .. reg_ddrc_rank0_rd_odt = 0x0 | ||
| 8574 | // .. .. ==> 0XF8006048[2:0] = 0x00000000U | ||
| 8575 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | ||
| 8576 | // .. .. reg_ddrc_rank0_wr_odt = 0x1 | ||
| 8577 | // .. .. ==> 0XF8006048[5:3] = 0x00000001U | ||
| 8578 | // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U | ||
| 8579 | // .. .. reg_ddrc_rank1_rd_odt = 0x1 | ||
| 8580 | // .. .. ==> 0XF8006048[8:6] = 0x00000001U | ||
| 8581 | // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U | ||
| 8582 | // .. .. reg_ddrc_rank1_wr_odt = 0x1 | ||
| 8583 | // .. .. ==> 0XF8006048[11:9] = 0x00000001U | ||
| 8584 | // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 8585 | // .. .. reg_phy_rd_local_odt = 0x0 | ||
| 8586 | // .. .. ==> 0XF8006048[13:12] = 0x00000000U | ||
| 8587 | // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U | ||
| 8588 | // .. .. reg_phy_wr_local_odt = 0x3 | ||
| 8589 | // .. .. ==> 0XF8006048[15:14] = 0x00000003U | ||
| 8590 | // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U | ||
| 8591 | // .. .. reg_phy_idle_local_odt = 0x3 | ||
| 8592 | // .. .. ==> 0XF8006048[17:16] = 0x00000003U | ||
| 8593 | // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U | ||
| 8594 | // .. .. reg_ddrc_rank2_rd_odt = 0x0 | ||
| 8595 | // .. .. ==> 0XF8006048[20:18] = 0x00000000U | ||
| 8596 | // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U | ||
| 8597 | // .. .. reg_ddrc_rank2_wr_odt = 0x0 | ||
| 8598 | // .. .. ==> 0XF8006048[23:21] = 0x00000000U | ||
| 8599 | // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U | ||
| 8600 | // .. .. reg_ddrc_rank3_rd_odt = 0x0 | ||
| 8601 | // .. .. ==> 0XF8006048[26:24] = 0x00000000U | ||
| 8602 | // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
| 8603 | // .. .. reg_ddrc_rank3_wr_odt = 0x0 | ||
| 8604 | // .. .. ==> 0XF8006048[29:27] = 0x00000000U | ||
| 8605 | // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U | ||
| 8606 | // .. .. | ||
| 8607 | EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), | ||
| 8608 | // .. .. reg_phy_rd_cmd_to_data = 0x0 | ||
| 8609 | // .. .. ==> 0XF8006050[3:0] = 0x00000000U | ||
| 8610 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
| 8611 | // .. .. reg_phy_wr_cmd_to_data = 0x0 | ||
| 8612 | // .. .. ==> 0XF8006050[7:4] = 0x00000000U | ||
| 8613 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
| 8614 | // .. .. reg_phy_rdc_we_to_re_delay = 0x8 | ||
| 8615 | // .. .. ==> 0XF8006050[11:8] = 0x00000008U | ||
| 8616 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U | ||
| 8617 | // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 | ||
| 8618 | // .. .. ==> 0XF8006050[15:15] = 0x00000000U | ||
| 8619 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
| 8620 | // .. .. reg_phy_use_fixed_re = 0x1 | ||
| 8621 | // .. .. ==> 0XF8006050[16:16] = 0x00000001U | ||
| 8622 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | ||
| 8623 | // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 | ||
| 8624 | // .. .. ==> 0XF8006050[17:17] = 0x00000000U | ||
| 8625 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 8626 | // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 | ||
| 8627 | // .. .. ==> 0XF8006050[18:18] = 0x00000000U | ||
| 8628 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 8629 | // .. .. reg_phy_clk_stall_level = 0x0 | ||
| 8630 | // .. .. ==> 0XF8006050[19:19] = 0x00000000U | ||
| 8631 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
| 8632 | // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 | ||
| 8633 | // .. .. ==> 0XF8006050[27:24] = 0x00000007U | ||
| 8634 | // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U | ||
| 8635 | // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 | ||
| 8636 | // .. .. ==> 0XF8006050[31:28] = 0x00000007U | ||
| 8637 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | ||
| 8638 | // .. .. | ||
| 8639 | EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), | ||
| 8640 | // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 | ||
| 8641 | // .. .. ==> 0XF8006058[7:0] = 0x00000001U | ||
| 8642 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U | ||
| 8643 | // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 | ||
| 8644 | // .. .. ==> 0XF8006058[15:8] = 0x00000001U | ||
| 8645 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U | ||
| 8646 | // .. .. reg_ddrc_dis_dll_calib = 0x0 | ||
| 8647 | // .. .. ==> 0XF8006058[16:16] = 0x00000000U | ||
| 8648 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 8649 | // .. .. | ||
| 8650 | EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), | ||
| 8651 | // .. .. reg_ddrc_rd_odt_delay = 0x3 | ||
| 8652 | // .. .. ==> 0XF800605C[3:0] = 0x00000003U | ||
| 8653 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U | ||
| 8654 | // .. .. reg_ddrc_wr_odt_delay = 0x0 | ||
| 8655 | // .. .. ==> 0XF800605C[7:4] = 0x00000000U | ||
| 8656 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
| 8657 | // .. .. reg_ddrc_rd_odt_hold = 0x0 | ||
| 8658 | // .. .. ==> 0XF800605C[11:8] = 0x00000000U | ||
| 8659 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | ||
| 8660 | // .. .. reg_ddrc_wr_odt_hold = 0x5 | ||
| 8661 | // .. .. ==> 0XF800605C[15:12] = 0x00000005U | ||
| 8662 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U | ||
| 8663 | // .. .. | ||
| 8664 | EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), | ||
| 8665 | // .. .. reg_ddrc_pageclose = 0x0 | ||
| 8666 | // .. .. ==> 0XF8006060[0:0] = 0x00000000U | ||
| 8667 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 8668 | // .. .. reg_ddrc_lpr_num_entries = 0x1f | ||
| 8669 | // .. .. ==> 0XF8006060[6:1] = 0x0000001FU | ||
| 8670 | // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU | ||
| 8671 | // .. .. reg_ddrc_auto_pre_en = 0x0 | ||
| 8672 | // .. .. ==> 0XF8006060[7:7] = 0x00000000U | ||
| 8673 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 8674 | // .. .. reg_ddrc_refresh_update_level = 0x0 | ||
| 8675 | // .. .. ==> 0XF8006060[8:8] = 0x00000000U | ||
| 8676 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 8677 | // .. .. reg_ddrc_dis_wc = 0x0 | ||
| 8678 | // .. .. ==> 0XF8006060[9:9] = 0x00000000U | ||
| 8679 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
| 8680 | // .. .. reg_ddrc_dis_collision_page_opt = 0x0 | ||
| 8681 | // .. .. ==> 0XF8006060[10:10] = 0x00000000U | ||
| 8682 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 8683 | // .. .. reg_ddrc_selfref_en = 0x0 | ||
| 8684 | // .. .. ==> 0XF8006060[12:12] = 0x00000000U | ||
| 8685 | // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 8686 | // .. .. | ||
| 8687 | EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), | ||
| 8688 | // .. .. reg_ddrc_go2critical_hysteresis = 0x0 | ||
| 8689 | // .. .. ==> 0XF8006064[12:5] = 0x00000000U | ||
| 8690 | // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U | ||
| 8691 | // .. .. reg_arb_go2critical_en = 0x1 | ||
| 8692 | // .. .. ==> 0XF8006064[17:17] = 0x00000001U | ||
| 8693 | // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U | ||
| 8694 | // .. .. | ||
| 8695 | EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), | ||
| 8696 | // .. .. reg_ddrc_wrlvl_ww = 0x41 | ||
| 8697 | // .. .. ==> 0XF8006068[7:0] = 0x00000041U | ||
| 8698 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U | ||
| 8699 | // .. .. reg_ddrc_rdlvl_rr = 0x41 | ||
| 8700 | // .. .. ==> 0XF8006068[15:8] = 0x00000041U | ||
| 8701 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U | ||
| 8702 | // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 | ||
| 8703 | // .. .. ==> 0XF8006068[25:16] = 0x00000028U | ||
| 8704 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U | ||
| 8705 | // .. .. | ||
| 8706 | EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), | ||
| 8707 | // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 | ||
| 8708 | // .. .. ==> 0XF800606C[7:0] = 0x00000010U | ||
| 8709 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U | ||
| 8710 | // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 | ||
| 8711 | // .. .. ==> 0XF800606C[15:8] = 0x00000016U | ||
| 8712 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U | ||
| 8713 | // .. .. | ||
| 8714 | EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), | ||
| 8715 | // .. .. refresh_timer0_start_value_x32 = 0x0 | ||
| 8716 | // .. .. ==> 0XF80060A0[11:0] = 0x00000000U | ||
| 8717 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U | ||
| 8718 | // .. .. refresh_timer1_start_value_x32 = 0x8 | ||
| 8719 | // .. .. ==> 0XF80060A0[23:12] = 0x00000008U | ||
| 8720 | // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U | ||
| 8721 | // .. .. | ||
| 8722 | EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), | ||
| 8723 | // .. .. reg_ddrc_dis_auto_zq = 0x0 | ||
| 8724 | // .. .. ==> 0XF80060A4[0:0] = 0x00000000U | ||
| 8725 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 8726 | // .. .. reg_ddrc_ddr3 = 0x1 | ||
| 8727 | // .. .. ==> 0XF80060A4[1:1] = 0x00000001U | ||
| 8728 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 8729 | // .. .. reg_ddrc_t_mod = 0x200 | ||
| 8730 | // .. .. ==> 0XF80060A4[11:2] = 0x00000200U | ||
| 8731 | // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U | ||
| 8732 | // .. .. reg_ddrc_t_zq_long_nop = 0x200 | ||
| 8733 | // .. .. ==> 0XF80060A4[21:12] = 0x00000200U | ||
| 8734 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U | ||
| 8735 | // .. .. reg_ddrc_t_zq_short_nop = 0x40 | ||
| 8736 | // .. .. ==> 0XF80060A4[31:22] = 0x00000040U | ||
| 8737 | // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U | ||
| 8738 | // .. .. | ||
| 8739 | EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), | ||
| 8740 | // .. .. t_zq_short_interval_x1024 = 0xc845 | ||
| 8741 | // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U | ||
| 8742 | // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U | ||
| 8743 | // .. .. dram_rstn_x1024 = 0x67 | ||
| 8744 | // .. .. ==> 0XF80060A8[27:20] = 0x00000067U | ||
| 8745 | // .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U | ||
| 8746 | // .. .. | ||
| 8747 | EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U), | ||
| 8748 | // .. .. deeppowerdown_en = 0x0 | ||
| 8749 | // .. .. ==> 0XF80060AC[0:0] = 0x00000000U | ||
| 8750 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 8751 | // .. .. deeppowerdown_to_x1024 = 0xff | ||
| 8752 | // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU | ||
| 8753 | // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU | ||
| 8754 | // .. .. | ||
| 8755 | EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), | ||
| 8756 | // .. .. dfi_wrlvl_max_x1024 = 0xfff | ||
| 8757 | // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU | ||
| 8758 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU | ||
| 8759 | // .. .. dfi_rdlvl_max_x1024 = 0xfff | ||
| 8760 | // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU | ||
| 8761 | // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U | ||
| 8762 | // .. .. ddrc_reg_twrlvl_max_error = 0x0 | ||
| 8763 | // .. .. ==> 0XF80060B0[24:24] = 0x00000000U | ||
| 8764 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
| 8765 | // .. .. ddrc_reg_trdlvl_max_error = 0x0 | ||
| 8766 | // .. .. ==> 0XF80060B0[25:25] = 0x00000000U | ||
| 8767 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
| 8768 | // .. .. reg_ddrc_dfi_wr_level_en = 0x1 | ||
| 8769 | // .. .. ==> 0XF80060B0[26:26] = 0x00000001U | ||
| 8770 | // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | ||
| 8771 | // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 | ||
| 8772 | // .. .. ==> 0XF80060B0[27:27] = 0x00000001U | ||
| 8773 | // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | ||
| 8774 | // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 | ||
| 8775 | // .. .. ==> 0XF80060B0[28:28] = 0x00000001U | ||
| 8776 | // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | ||
| 8777 | // .. .. | ||
| 8778 | EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), | ||
| 8779 | // .. .. reg_ddrc_2t_delay = 0x0 | ||
| 8780 | // .. .. ==> 0XF80060B4[8:0] = 0x00000000U | ||
| 8781 | // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U | ||
| 8782 | // .. .. reg_ddrc_skip_ocd = 0x1 | ||
| 8783 | // .. .. ==> 0XF80060B4[9:9] = 0x00000001U | ||
| 8784 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U | ||
| 8785 | // .. .. reg_ddrc_dis_pre_bypass = 0x0 | ||
| 8786 | // .. .. ==> 0XF80060B4[10:10] = 0x00000000U | ||
| 8787 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 8788 | // .. .. | ||
| 8789 | EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), | ||
| 8790 | // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 | ||
| 8791 | // .. .. ==> 0XF80060B8[4:0] = 0x00000006U | ||
| 8792 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U | ||
| 8793 | // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 | ||
| 8794 | // .. .. ==> 0XF80060B8[14:5] = 0x00000003U | ||
| 8795 | // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U | ||
| 8796 | // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 | ||
| 8797 | // .. .. ==> 0XF80060B8[24:15] = 0x00000040U | ||
| 8798 | // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U | ||
| 8799 | // .. .. | ||
| 8800 | EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), | ||
| 8801 | // .. .. START: RESET ECC ERROR | ||
| 8802 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 | ||
| 8803 | // .. .. ==> 0XF80060C4[0:0] = 0x00000001U | ||
| 8804 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 8805 | // .. .. Clear_Correctable_DRAM_ECC_error = 1 | ||
| 8806 | // .. .. ==> 0XF80060C4[1:1] = 0x00000001U | ||
| 8807 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 8808 | // .. .. | ||
| 8809 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), | ||
| 8810 | // .. .. FINISH: RESET ECC ERROR | ||
| 8811 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 | ||
| 8812 | // .. .. ==> 0XF80060C4[0:0] = 0x00000000U | ||
| 8813 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 8814 | // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 | ||
| 8815 | // .. .. ==> 0XF80060C4[1:1] = 0x00000000U | ||
| 8816 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 8817 | // .. .. | ||
| 8818 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), | ||
| 8819 | // .. .. CORR_ECC_LOG_VALID = 0x0 | ||
| 8820 | // .. .. ==> 0XF80060C8[0:0] = 0x00000000U | ||
| 8821 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 8822 | // .. .. ECC_CORRECTED_BIT_NUM = 0x0 | ||
| 8823 | // .. .. ==> 0XF80060C8[7:1] = 0x00000000U | ||
| 8824 | // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U | ||
| 8825 | // .. .. | ||
| 8826 | EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), | ||
| 8827 | // .. .. UNCORR_ECC_LOG_VALID = 0x0 | ||
| 8828 | // .. .. ==> 0XF80060DC[0:0] = 0x00000000U | ||
| 8829 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 8830 | // .. .. | ||
| 8831 | EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), | ||
| 8832 | // .. .. STAT_NUM_CORR_ERR = 0x0 | ||
| 8833 | // .. .. ==> 0XF80060F0[15:8] = 0x00000000U | ||
| 8834 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U | ||
| 8835 | // .. .. STAT_NUM_UNCORR_ERR = 0x0 | ||
| 8836 | // .. .. ==> 0XF80060F0[7:0] = 0x00000000U | ||
| 8837 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U | ||
| 8838 | // .. .. | ||
| 8839 | EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), | ||
| 8840 | // .. .. reg_ddrc_ecc_mode = 0x0 | ||
| 8841 | // .. .. ==> 0XF80060F4[2:0] = 0x00000000U | ||
| 8842 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | ||
| 8843 | // .. .. reg_ddrc_dis_scrub = 0x1 | ||
| 8844 | // .. .. ==> 0XF80060F4[3:3] = 0x00000001U | ||
| 8845 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U | ||
| 8846 | // .. .. | ||
| 8847 | EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), | ||
| 8848 | // .. .. reg_phy_dif_on = 0x0 | ||
| 8849 | // .. .. ==> 0XF8006114[3:0] = 0x00000000U | ||
| 8850 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
| 8851 | // .. .. reg_phy_dif_off = 0x0 | ||
| 8852 | // .. .. ==> 0XF8006114[7:4] = 0x00000000U | ||
| 8853 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
| 8854 | // .. .. | ||
| 8855 | EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), | ||
| 8856 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
| 8857 | // .. .. ==> 0XF8006118[0:0] = 0x00000001U | ||
| 8858 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 8859 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
| 8860 | // .. .. ==> 0XF8006118[1:1] = 0x00000000U | ||
| 8861 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 8862 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
| 8863 | // .. .. ==> 0XF8006118[2:2] = 0x00000000U | ||
| 8864 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 8865 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
| 8866 | // .. .. ==> 0XF8006118[3:3] = 0x00000000U | ||
| 8867 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 8868 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
| 8869 | // .. .. ==> 0XF8006118[4:4] = 0x00000000U | ||
| 8870 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 8871 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
| 8872 | // .. .. ==> 0XF8006118[5:5] = 0x00000000U | ||
| 8873 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
| 8874 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
| 8875 | // .. .. ==> 0XF8006118[14:6] = 0x00000000U | ||
| 8876 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
| 8877 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
| 8878 | // .. .. ==> 0XF8006118[23:15] = 0x00000000U | ||
| 8879 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
| 8880 | // .. .. reg_phy_dq_offset = 0x40 | ||
| 8881 | // .. .. ==> 0XF8006118[30:24] = 0x00000040U | ||
| 8882 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
| 8883 | // .. .. | ||
| 8884 | EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), | ||
| 8885 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
| 8886 | // .. .. ==> 0XF800611C[0:0] = 0x00000001U | ||
| 8887 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 8888 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
| 8889 | // .. .. ==> 0XF800611C[1:1] = 0x00000000U | ||
| 8890 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 8891 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
| 8892 | // .. .. ==> 0XF800611C[2:2] = 0x00000000U | ||
| 8893 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 8894 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
| 8895 | // .. .. ==> 0XF800611C[3:3] = 0x00000000U | ||
| 8896 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 8897 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
| 8898 | // .. .. ==> 0XF800611C[4:4] = 0x00000000U | ||
| 8899 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 8900 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
| 8901 | // .. .. ==> 0XF800611C[5:5] = 0x00000000U | ||
| 8902 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
| 8903 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
| 8904 | // .. .. ==> 0XF800611C[14:6] = 0x00000000U | ||
| 8905 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
| 8906 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
| 8907 | // .. .. ==> 0XF800611C[23:15] = 0x00000000U | ||
| 8908 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
| 8909 | // .. .. reg_phy_dq_offset = 0x40 | ||
| 8910 | // .. .. ==> 0XF800611C[30:24] = 0x00000040U | ||
| 8911 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
| 8912 | // .. .. | ||
| 8913 | EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), | ||
| 8914 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
| 8915 | // .. .. ==> 0XF8006120[0:0] = 0x00000001U | ||
| 8916 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 8917 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
| 8918 | // .. .. ==> 0XF8006120[1:1] = 0x00000000U | ||
| 8919 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 8920 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
| 8921 | // .. .. ==> 0XF8006120[2:2] = 0x00000000U | ||
| 8922 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 8923 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
| 8924 | // .. .. ==> 0XF8006120[3:3] = 0x00000000U | ||
| 8925 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 8926 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
| 8927 | // .. .. ==> 0XF8006120[4:4] = 0x00000000U | ||
| 8928 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 8929 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
| 8930 | // .. .. ==> 0XF8006120[5:5] = 0x00000000U | ||
| 8931 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
| 8932 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
| 8933 | // .. .. ==> 0XF8006120[14:6] = 0x00000000U | ||
| 8934 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
| 8935 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
| 8936 | // .. .. ==> 0XF8006120[23:15] = 0x00000000U | ||
| 8937 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
| 8938 | // .. .. reg_phy_dq_offset = 0x40 | ||
| 8939 | // .. .. ==> 0XF8006120[30:24] = 0x00000040U | ||
| 8940 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
| 8941 | // .. .. | ||
| 8942 | EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), | ||
| 8943 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
| 8944 | // .. .. ==> 0XF8006124[0:0] = 0x00000001U | ||
| 8945 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 8946 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
| 8947 | // .. .. ==> 0XF8006124[1:1] = 0x00000000U | ||
| 8948 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 8949 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
| 8950 | // .. .. ==> 0XF8006124[2:2] = 0x00000000U | ||
| 8951 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 8952 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
| 8953 | // .. .. ==> 0XF8006124[3:3] = 0x00000000U | ||
| 8954 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 8955 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
| 8956 | // .. .. ==> 0XF8006124[4:4] = 0x00000000U | ||
| 8957 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 8958 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
| 8959 | // .. .. ==> 0XF8006124[5:5] = 0x00000000U | ||
| 8960 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
| 8961 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
| 8962 | // .. .. ==> 0XF8006124[14:6] = 0x00000000U | ||
| 8963 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
| 8964 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
| 8965 | // .. .. ==> 0XF8006124[23:15] = 0x00000000U | ||
| 8966 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
| 8967 | // .. .. reg_phy_dq_offset = 0x40 | ||
| 8968 | // .. .. ==> 0XF8006124[30:24] = 0x00000040U | ||
| 8969 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
| 8970 | // .. .. | ||
| 8971 | EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), | ||
| 8972 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
| 8973 | // .. .. ==> 0XF800612C[9:0] = 0x00000000U | ||
| 8974 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
| 8975 | // .. .. reg_phy_gatelvl_init_ratio = 0x8f | ||
| 8976 | // .. .. ==> 0XF800612C[19:10] = 0x0000008FU | ||
| 8977 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U | ||
| 8978 | // .. .. | ||
| 8979 | EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U), | ||
| 8980 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
| 8981 | // .. .. ==> 0XF8006130[9:0] = 0x00000000U | ||
| 8982 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
| 8983 | // .. .. reg_phy_gatelvl_init_ratio = 0x8a | ||
| 8984 | // .. .. ==> 0XF8006130[19:10] = 0x0000008AU | ||
| 8985 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U | ||
| 8986 | // .. .. | ||
| 8987 | EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U), | ||
| 8988 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
| 8989 | // .. .. ==> 0XF8006134[9:0] = 0x00000000U | ||
| 8990 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
| 8991 | // .. .. reg_phy_gatelvl_init_ratio = 0x8b | ||
| 8992 | // .. .. ==> 0XF8006134[19:10] = 0x0000008BU | ||
| 8993 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U | ||
| 8994 | // .. .. | ||
| 8995 | EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U), | ||
| 8996 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
| 8997 | // .. .. ==> 0XF8006138[9:0] = 0x00000000U | ||
| 8998 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
| 8999 | // .. .. reg_phy_gatelvl_init_ratio = 0x92 | ||
| 9000 | // .. .. ==> 0XF8006138[19:10] = 0x00000092U | ||
| 9001 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U | ||
| 9002 | // .. .. | ||
| 9003 | EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U), | ||
| 9004 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
| 9005 | // .. .. ==> 0XF8006140[9:0] = 0x00000035U | ||
| 9006 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
| 9007 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
| 9008 | // .. .. ==> 0XF8006140[10:10] = 0x00000000U | ||
| 9009 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 9010 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
| 9011 | // .. .. ==> 0XF8006140[19:11] = 0x00000000U | ||
| 9012 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 9013 | // .. .. | ||
| 9014 | EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), | ||
| 9015 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
| 9016 | // .. .. ==> 0XF8006144[9:0] = 0x00000035U | ||
| 9017 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
| 9018 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
| 9019 | // .. .. ==> 0XF8006144[10:10] = 0x00000000U | ||
| 9020 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 9021 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
| 9022 | // .. .. ==> 0XF8006144[19:11] = 0x00000000U | ||
| 9023 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 9024 | // .. .. | ||
| 9025 | EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), | ||
| 9026 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
| 9027 | // .. .. ==> 0XF8006148[9:0] = 0x00000035U | ||
| 9028 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
| 9029 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
| 9030 | // .. .. ==> 0XF8006148[10:10] = 0x00000000U | ||
| 9031 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 9032 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
| 9033 | // .. .. ==> 0XF8006148[19:11] = 0x00000000U | ||
| 9034 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 9035 | // .. .. | ||
| 9036 | EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), | ||
| 9037 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
| 9038 | // .. .. ==> 0XF800614C[9:0] = 0x00000035U | ||
| 9039 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
| 9040 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
| 9041 | // .. .. ==> 0XF800614C[10:10] = 0x00000000U | ||
| 9042 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 9043 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
| 9044 | // .. .. ==> 0XF800614C[19:11] = 0x00000000U | ||
| 9045 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 9046 | // .. .. | ||
| 9047 | EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), | ||
| 9048 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 | ||
| 9049 | // .. .. ==> 0XF8006154[9:0] = 0x00000077U | ||
| 9050 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U | ||
| 9051 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
| 9052 | // .. .. ==> 0XF8006154[10:10] = 0x00000000U | ||
| 9053 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 9054 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
| 9055 | // .. .. ==> 0XF8006154[19:11] = 0x00000000U | ||
| 9056 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 9057 | // .. .. | ||
| 9058 | EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U), | ||
| 9059 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c | ||
| 9060 | // .. .. ==> 0XF8006158[9:0] = 0x0000007CU | ||
| 9061 | // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU | ||
| 9062 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
| 9063 | // .. .. ==> 0XF8006158[10:10] = 0x00000000U | ||
| 9064 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 9065 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
| 9066 | // .. .. ==> 0XF8006158[19:11] = 0x00000000U | ||
| 9067 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 9068 | // .. .. | ||
| 9069 | EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), | ||
| 9070 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c | ||
| 9071 | // .. .. ==> 0XF800615C[9:0] = 0x0000007CU | ||
| 9072 | // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU | ||
| 9073 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
| 9074 | // .. .. ==> 0XF800615C[10:10] = 0x00000000U | ||
| 9075 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 9076 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
| 9077 | // .. .. ==> 0XF800615C[19:11] = 0x00000000U | ||
| 9078 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 9079 | // .. .. | ||
| 9080 | EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU), | ||
| 9081 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x75 | ||
| 9082 | // .. .. ==> 0XF8006160[9:0] = 0x00000075U | ||
| 9083 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U | ||
| 9084 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
| 9085 | // .. .. ==> 0XF8006160[10:10] = 0x00000000U | ||
| 9086 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 9087 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
| 9088 | // .. .. ==> 0XF8006160[19:11] = 0x00000000U | ||
| 9089 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 9090 | // .. .. | ||
| 9091 | EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U), | ||
| 9092 | // .. .. reg_phy_fifo_we_slave_ratio = 0xe4 | ||
| 9093 | // .. .. ==> 0XF8006168[10:0] = 0x000000E4U | ||
| 9094 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U | ||
| 9095 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
| 9096 | // .. .. ==> 0XF8006168[11:11] = 0x00000000U | ||
| 9097 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 9098 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
| 9099 | // .. .. ==> 0XF8006168[20:12] = 0x00000000U | ||
| 9100 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
| 9101 | // .. .. | ||
| 9102 | EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U), | ||
| 9103 | // .. .. reg_phy_fifo_we_slave_ratio = 0xdf | ||
| 9104 | // .. .. ==> 0XF800616C[10:0] = 0x000000DFU | ||
| 9105 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU | ||
| 9106 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
| 9107 | // .. .. ==> 0XF800616C[11:11] = 0x00000000U | ||
| 9108 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 9109 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
| 9110 | // .. .. ==> 0XF800616C[20:12] = 0x00000000U | ||
| 9111 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
| 9112 | // .. .. | ||
| 9113 | EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU), | ||
| 9114 | // .. .. reg_phy_fifo_we_slave_ratio = 0xe0 | ||
| 9115 | // .. .. ==> 0XF8006170[10:0] = 0x000000E0U | ||
| 9116 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U | ||
| 9117 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
| 9118 | // .. .. ==> 0XF8006170[11:11] = 0x00000000U | ||
| 9119 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 9120 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
| 9121 | // .. .. ==> 0XF8006170[20:12] = 0x00000000U | ||
| 9122 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
| 9123 | // .. .. | ||
| 9124 | EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U), | ||
| 9125 | // .. .. reg_phy_fifo_we_slave_ratio = 0xe7 | ||
| 9126 | // .. .. ==> 0XF8006174[10:0] = 0x000000E7U | ||
| 9127 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U | ||
| 9128 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
| 9129 | // .. .. ==> 0XF8006174[11:11] = 0x00000000U | ||
| 9130 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 9131 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
| 9132 | // .. .. ==> 0XF8006174[20:12] = 0x00000000U | ||
| 9133 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
| 9134 | // .. .. | ||
| 9135 | EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U), | ||
| 9136 | // .. .. reg_phy_wr_data_slave_ratio = 0xb7 | ||
| 9137 | // .. .. ==> 0XF800617C[9:0] = 0x000000B7U | ||
| 9138 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U | ||
| 9139 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
| 9140 | // .. .. ==> 0XF800617C[10:10] = 0x00000000U | ||
| 9141 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 9142 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
| 9143 | // .. .. ==> 0XF800617C[19:11] = 0x00000000U | ||
| 9144 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 9145 | // .. .. | ||
| 9146 | EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U), | ||
| 9147 | // .. .. reg_phy_wr_data_slave_ratio = 0xbc | ||
| 9148 | // .. .. ==> 0XF8006180[9:0] = 0x000000BCU | ||
| 9149 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU | ||
| 9150 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
| 9151 | // .. .. ==> 0XF8006180[10:10] = 0x00000000U | ||
| 9152 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 9153 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
| 9154 | // .. .. ==> 0XF8006180[19:11] = 0x00000000U | ||
| 9155 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 9156 | // .. .. | ||
| 9157 | EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), | ||
| 9158 | // .. .. reg_phy_wr_data_slave_ratio = 0xbc | ||
| 9159 | // .. .. ==> 0XF8006184[9:0] = 0x000000BCU | ||
| 9160 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU | ||
| 9161 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
| 9162 | // .. .. ==> 0XF8006184[10:10] = 0x00000000U | ||
| 9163 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 9164 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
| 9165 | // .. .. ==> 0XF8006184[19:11] = 0x00000000U | ||
| 9166 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 9167 | // .. .. | ||
| 9168 | EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU), | ||
| 9169 | // .. .. reg_phy_wr_data_slave_ratio = 0xb5 | ||
| 9170 | // .. .. ==> 0XF8006188[9:0] = 0x000000B5U | ||
| 9171 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U | ||
| 9172 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
| 9173 | // .. .. ==> 0XF8006188[10:10] = 0x00000000U | ||
| 9174 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 9175 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
| 9176 | // .. .. ==> 0XF8006188[19:11] = 0x00000000U | ||
| 9177 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
| 9178 | // .. .. | ||
| 9179 | EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U), | ||
| 9180 | // .. .. reg_phy_loopback = 0x0 | ||
| 9181 | // .. .. ==> 0XF8006190[0:0] = 0x00000000U | ||
| 9182 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 9183 | // .. .. reg_phy_bl2 = 0x0 | ||
| 9184 | // .. .. ==> 0XF8006190[1:1] = 0x00000000U | ||
| 9185 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 9186 | // .. .. reg_phy_at_spd_atpg = 0x0 | ||
| 9187 | // .. .. ==> 0XF8006190[2:2] = 0x00000000U | ||
| 9188 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 9189 | // .. .. reg_phy_bist_enable = 0x0 | ||
| 9190 | // .. .. ==> 0XF8006190[3:3] = 0x00000000U | ||
| 9191 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 9192 | // .. .. reg_phy_bist_force_err = 0x0 | ||
| 9193 | // .. .. ==> 0XF8006190[4:4] = 0x00000000U | ||
| 9194 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 9195 | // .. .. reg_phy_bist_mode = 0x0 | ||
| 9196 | // .. .. ==> 0XF8006190[6:5] = 0x00000000U | ||
| 9197 | // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
| 9198 | // .. .. reg_phy_invert_clkout = 0x1 | ||
| 9199 | // .. .. ==> 0XF8006190[7:7] = 0x00000001U | ||
| 9200 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
| 9201 | // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 | ||
| 9202 | // .. .. ==> 0XF8006190[8:8] = 0x00000000U | ||
| 9203 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 9204 | // .. .. reg_phy_sel_logic = 0x0 | ||
| 9205 | // .. .. ==> 0XF8006190[9:9] = 0x00000000U | ||
| 9206 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
| 9207 | // .. .. reg_phy_ctrl_slave_ratio = 0x100 | ||
| 9208 | // .. .. ==> 0XF8006190[19:10] = 0x00000100U | ||
| 9209 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U | ||
| 9210 | // .. .. reg_phy_ctrl_slave_force = 0x0 | ||
| 9211 | // .. .. ==> 0XF8006190[20:20] = 0x00000000U | ||
| 9212 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
| 9213 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | ||
| 9214 | // .. .. ==> 0XF8006190[27:21] = 0x00000000U | ||
| 9215 | // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U | ||
| 9216 | // .. .. reg_phy_use_rank0_delays = 0x1 | ||
| 9217 | // .. .. ==> 0XF8006190[28:28] = 0x00000001U | ||
| 9218 | // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | ||
| 9219 | // .. .. reg_phy_lpddr = 0x0 | ||
| 9220 | // .. .. ==> 0XF8006190[29:29] = 0x00000000U | ||
| 9221 | // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U | ||
| 9222 | // .. .. reg_phy_cmd_latency = 0x0 | ||
| 9223 | // .. .. ==> 0XF8006190[30:30] = 0x00000000U | ||
| 9224 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | ||
| 9225 | // .. .. reg_phy_int_lpbk = 0x0 | ||
| 9226 | // .. .. ==> 0XF8006190[31:31] = 0x00000000U | ||
| 9227 | // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U | ||
| 9228 | // .. .. | ||
| 9229 | EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), | ||
| 9230 | // .. .. reg_phy_wr_rl_delay = 0x2 | ||
| 9231 | // .. .. ==> 0XF8006194[4:0] = 0x00000002U | ||
| 9232 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U | ||
| 9233 | // .. .. reg_phy_rd_rl_delay = 0x4 | ||
| 9234 | // .. .. ==> 0XF8006194[9:5] = 0x00000004U | ||
| 9235 | // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U | ||
| 9236 | // .. .. reg_phy_dll_lock_diff = 0xf | ||
| 9237 | // .. .. ==> 0XF8006194[13:10] = 0x0000000FU | ||
| 9238 | // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U | ||
| 9239 | // .. .. reg_phy_use_wr_level = 0x1 | ||
| 9240 | // .. .. ==> 0XF8006194[14:14] = 0x00000001U | ||
| 9241 | // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U | ||
| 9242 | // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 | ||
| 9243 | // .. .. ==> 0XF8006194[15:15] = 0x00000001U | ||
| 9244 | // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U | ||
| 9245 | // .. .. reg_phy_use_rd_data_eye_level = 0x1 | ||
| 9246 | // .. .. ==> 0XF8006194[16:16] = 0x00000001U | ||
| 9247 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | ||
| 9248 | // .. .. reg_phy_dis_calib_rst = 0x0 | ||
| 9249 | // .. .. ==> 0XF8006194[17:17] = 0x00000000U | ||
| 9250 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 9251 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | ||
| 9252 | // .. .. ==> 0XF8006194[19:18] = 0x00000000U | ||
| 9253 | // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U | ||
| 9254 | // .. .. | ||
| 9255 | EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), | ||
| 9256 | // .. .. reg_arb_page_addr_mask = 0x0 | ||
| 9257 | // .. .. ==> 0XF8006204[31:0] = 0x00000000U | ||
| 9258 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
| 9259 | // .. .. | ||
| 9260 | EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), | ||
| 9261 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
| 9262 | // .. .. ==> 0XF8006208[9:0] = 0x000003FFU | ||
| 9263 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 9264 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
| 9265 | // .. .. ==> 0XF8006208[16:16] = 0x00000000U | ||
| 9266 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 9267 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
| 9268 | // .. .. ==> 0XF8006208[17:17] = 0x00000000U | ||
| 9269 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 9270 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
| 9271 | // .. .. ==> 0XF8006208[18:18] = 0x00000000U | ||
| 9272 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 9273 | // .. .. reg_arb_dis_rmw_portn = 0x1 | ||
| 9274 | // .. .. ==> 0XF8006208[19:19] = 0x00000001U | ||
| 9275 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
| 9276 | // .. .. | ||
| 9277 | EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), | ||
| 9278 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
| 9279 | // .. .. ==> 0XF800620C[9:0] = 0x000003FFU | ||
| 9280 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 9281 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
| 9282 | // .. .. ==> 0XF800620C[16:16] = 0x00000000U | ||
| 9283 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 9284 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
| 9285 | // .. .. ==> 0XF800620C[17:17] = 0x00000000U | ||
| 9286 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 9287 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
| 9288 | // .. .. ==> 0XF800620C[18:18] = 0x00000000U | ||
| 9289 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 9290 | // .. .. reg_arb_dis_rmw_portn = 0x1 | ||
| 9291 | // .. .. ==> 0XF800620C[19:19] = 0x00000001U | ||
| 9292 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
| 9293 | // .. .. | ||
| 9294 | EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), | ||
| 9295 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
| 9296 | // .. .. ==> 0XF8006210[9:0] = 0x000003FFU | ||
| 9297 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 9298 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
| 9299 | // .. .. ==> 0XF8006210[16:16] = 0x00000000U | ||
| 9300 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 9301 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
| 9302 | // .. .. ==> 0XF8006210[17:17] = 0x00000000U | ||
| 9303 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 9304 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
| 9305 | // .. .. ==> 0XF8006210[18:18] = 0x00000000U | ||
| 9306 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 9307 | // .. .. reg_arb_dis_rmw_portn = 0x1 | ||
| 9308 | // .. .. ==> 0XF8006210[19:19] = 0x00000001U | ||
| 9309 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
| 9310 | // .. .. | ||
| 9311 | EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), | ||
| 9312 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
| 9313 | // .. .. ==> 0XF8006214[9:0] = 0x000003FFU | ||
| 9314 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 9315 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
| 9316 | // .. .. ==> 0XF8006214[16:16] = 0x00000000U | ||
| 9317 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 9318 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
| 9319 | // .. .. ==> 0XF8006214[17:17] = 0x00000000U | ||
| 9320 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 9321 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
| 9322 | // .. .. ==> 0XF8006214[18:18] = 0x00000000U | ||
| 9323 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 9324 | // .. .. reg_arb_dis_rmw_portn = 0x1 | ||
| 9325 | // .. .. ==> 0XF8006214[19:19] = 0x00000001U | ||
| 9326 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
| 9327 | // .. .. | ||
| 9328 | EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), | ||
| 9329 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
| 9330 | // .. .. ==> 0XF8006218[9:0] = 0x000003FFU | ||
| 9331 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 9332 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
| 9333 | // .. .. ==> 0XF8006218[16:16] = 0x00000000U | ||
| 9334 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 9335 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
| 9336 | // .. .. ==> 0XF8006218[17:17] = 0x00000000U | ||
| 9337 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 9338 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
| 9339 | // .. .. ==> 0XF8006218[18:18] = 0x00000000U | ||
| 9340 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 9341 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
| 9342 | // .. .. ==> 0XF8006218[19:19] = 0x00000000U | ||
| 9343 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
| 9344 | // .. .. | ||
| 9345 | EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), | ||
| 9346 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
| 9347 | // .. .. ==> 0XF800621C[9:0] = 0x000003FFU | ||
| 9348 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 9349 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
| 9350 | // .. .. ==> 0XF800621C[16:16] = 0x00000000U | ||
| 9351 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 9352 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
| 9353 | // .. .. ==> 0XF800621C[17:17] = 0x00000000U | ||
| 9354 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 9355 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
| 9356 | // .. .. ==> 0XF800621C[18:18] = 0x00000000U | ||
| 9357 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 9358 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
| 9359 | // .. .. ==> 0XF800621C[19:19] = 0x00000000U | ||
| 9360 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
| 9361 | // .. .. | ||
| 9362 | EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), | ||
| 9363 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
| 9364 | // .. .. ==> 0XF8006220[9:0] = 0x000003FFU | ||
| 9365 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 9366 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
| 9367 | // .. .. ==> 0XF8006220[16:16] = 0x00000000U | ||
| 9368 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 9369 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
| 9370 | // .. .. ==> 0XF8006220[17:17] = 0x00000000U | ||
| 9371 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 9372 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
| 9373 | // .. .. ==> 0XF8006220[18:18] = 0x00000000U | ||
| 9374 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 9375 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
| 9376 | // .. .. ==> 0XF8006220[19:19] = 0x00000000U | ||
| 9377 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
| 9378 | // .. .. | ||
| 9379 | EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), | ||
| 9380 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
| 9381 | // .. .. ==> 0XF8006224[9:0] = 0x000003FFU | ||
| 9382 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
| 9383 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
| 9384 | // .. .. ==> 0XF8006224[16:16] = 0x00000000U | ||
| 9385 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 9386 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
| 9387 | // .. .. ==> 0XF8006224[17:17] = 0x00000000U | ||
| 9388 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 9389 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
| 9390 | // .. .. ==> 0XF8006224[18:18] = 0x00000000U | ||
| 9391 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
| 9392 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
| 9393 | // .. .. ==> 0XF8006224[19:19] = 0x00000000U | ||
| 9394 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
| 9395 | // .. .. | ||
| 9396 | EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), | ||
| 9397 | // .. .. reg_ddrc_lpddr2 = 0x0 | ||
| 9398 | // .. .. ==> 0XF80062A8[0:0] = 0x00000000U | ||
| 9399 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 9400 | // .. .. reg_ddrc_per_bank_refresh = 0x0 | ||
| 9401 | // .. .. ==> 0XF80062A8[1:1] = 0x00000000U | ||
| 9402 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 9403 | // .. .. reg_ddrc_derate_enable = 0x0 | ||
| 9404 | // .. .. ==> 0XF80062A8[2:2] = 0x00000000U | ||
| 9405 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 9406 | // .. .. reg_ddrc_mr4_margin = 0x0 | ||
| 9407 | // .. .. ==> 0XF80062A8[11:4] = 0x00000000U | ||
| 9408 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U | ||
| 9409 | // .. .. | ||
| 9410 | EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), | ||
| 9411 | // .. .. reg_ddrc_mr4_read_interval = 0x0 | ||
| 9412 | // .. .. ==> 0XF80062AC[31:0] = 0x00000000U | ||
| 9413 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
| 9414 | // .. .. | ||
| 9415 | EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), | ||
| 9416 | // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 | ||
| 9417 | // .. .. ==> 0XF80062B0[3:0] = 0x00000005U | ||
| 9418 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U | ||
| 9419 | // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 | ||
| 9420 | // .. .. ==> 0XF80062B0[11:4] = 0x00000012U | ||
| 9421 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U | ||
| 9422 | // .. .. reg_ddrc_t_mrw = 0x5 | ||
| 9423 | // .. .. ==> 0XF80062B0[21:12] = 0x00000005U | ||
| 9424 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U | ||
| 9425 | // .. .. | ||
| 9426 | EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), | ||
| 9427 | // .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 | ||
| 9428 | // .. .. ==> 0XF80062B4[7:0] = 0x000000A6U | ||
| 9429 | // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U | ||
| 9430 | // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 | ||
| 9431 | // .. .. ==> 0XF80062B4[17:8] = 0x00000012U | ||
| 9432 | // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U | ||
| 9433 | // .. .. | ||
| 9434 | EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U), | ||
| 9435 | // .. .. START: POLL ON DCI STATUS | ||
| 9436 | // .. .. DONE = 1 | ||
| 9437 | // .. .. ==> 0XF8000B74[13:13] = 0x00000001U | ||
| 9438 | // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 9439 | // .. .. | ||
| 9440 | EMIT_MASKPOLL(0XF8000B74, 0x00002000U), | ||
| 9441 | // .. .. FINISH: POLL ON DCI STATUS | ||
| 9442 | // .. .. START: UNLOCK DDR | ||
| 9443 | // .. .. reg_ddrc_soft_rstb = 0x1 | ||
| 9444 | // .. .. ==> 0XF8006000[0:0] = 0x00000001U | ||
| 9445 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 9446 | // .. .. reg_ddrc_powerdown_en = 0x0 | ||
| 9447 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | ||
| 9448 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 9449 | // .. .. reg_ddrc_data_bus_width = 0x0 | ||
| 9450 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | ||
| 9451 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | ||
| 9452 | // .. .. reg_ddrc_burst8_refresh = 0x0 | ||
| 9453 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | ||
| 9454 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
| 9455 | // .. .. reg_ddrc_rdwr_idle_gap = 1 | ||
| 9456 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | ||
| 9457 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | ||
| 9458 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | ||
| 9459 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | ||
| 9460 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
| 9461 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | ||
| 9462 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | ||
| 9463 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
| 9464 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | ||
| 9465 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | ||
| 9466 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 9467 | // .. .. | ||
| 9468 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), | ||
| 9469 | // .. .. FINISH: UNLOCK DDR | ||
| 9470 | // .. .. START: CHECK DDR STATUS | ||
| 9471 | // .. .. ddrc_reg_operating_mode = 1 | ||
| 9472 | // .. .. ==> 0XF8006054[2:0] = 0x00000001U | ||
| 9473 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U | ||
| 9474 | // .. .. | ||
| 9475 | EMIT_MASKPOLL(0XF8006054, 0x00000007U), | ||
| 9476 | // .. .. FINISH: CHECK DDR STATUS | ||
| 9477 | // .. FINISH: DDR INITIALIZATION | ||
| 9478 | // FINISH: top | ||
| 9479 | // | ||
| 9480 | EMIT_EXIT(), | ||
| 9481 | |||
| 9482 | // | ||
| 9483 | }; | ||
| 9484 | |||
| 9485 | unsigned long ps7_mio_init_data_1_0[] = { | ||
| 9486 | // START: top | ||
| 9487 | // .. START: SLCR SETTINGS | ||
| 9488 | // .. UNLOCK_KEY = 0XDF0D | ||
| 9489 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
| 9490 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
| 9491 | // .. | ||
| 9492 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
| 9493 | // .. FINISH: SLCR SETTINGS | ||
| 9494 | // .. START: OCM REMAPPING | ||
| 9495 | // .. VREF_EN = 0x1 | ||
| 9496 | // .. ==> 0XF8000B00[0:0] = 0x00000001U | ||
| 9497 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 9498 | // .. VREF_PULLUP_EN = 0x0 | ||
| 9499 | // .. ==> 0XF8000B00[1:1] = 0x00000000U | ||
| 9500 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 9501 | // .. CLK_PULLUP_EN = 0x0 | ||
| 9502 | // .. ==> 0XF8000B00[8:8] = 0x00000000U | ||
| 9503 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 9504 | // .. SRSTN_PULLUP_EN = 0x0 | ||
| 9505 | // .. ==> 0XF8000B00[9:9] = 0x00000000U | ||
| 9506 | // .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
| 9507 | // .. | ||
| 9508 | EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), | ||
| 9509 | // .. FINISH: OCM REMAPPING | ||
| 9510 | // .. START: DDRIOB SETTINGS | ||
| 9511 | // .. INP_POWER = 0x0 | ||
| 9512 | // .. ==> 0XF8000B40[0:0] = 0x00000000U | ||
| 9513 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 9514 | // .. INP_TYPE = 0x0 | ||
| 9515 | // .. ==> 0XF8000B40[2:1] = 0x00000000U | ||
| 9516 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
| 9517 | // .. DCI_UPDATE = 0x0 | ||
| 9518 | // .. ==> 0XF8000B40[3:3] = 0x00000000U | ||
| 9519 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 9520 | // .. TERM_EN = 0x0 | ||
| 9521 | // .. ==> 0XF8000B40[4:4] = 0x00000000U | ||
| 9522 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 9523 | // .. DCR_TYPE = 0x0 | ||
| 9524 | // .. ==> 0XF8000B40[6:5] = 0x00000000U | ||
| 9525 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
| 9526 | // .. IBUF_DISABLE_MODE = 0x0 | ||
| 9527 | // .. ==> 0XF8000B40[7:7] = 0x00000000U | ||
| 9528 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 9529 | // .. TERM_DISABLE_MODE = 0x0 | ||
| 9530 | // .. ==> 0XF8000B40[8:8] = 0x00000000U | ||
| 9531 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 9532 | // .. OUTPUT_EN = 0x3 | ||
| 9533 | // .. ==> 0XF8000B40[10:9] = 0x00000003U | ||
| 9534 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 9535 | // .. PULLUP_EN = 0x0 | ||
| 9536 | // .. ==> 0XF8000B40[11:11] = 0x00000000U | ||
| 9537 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 9538 | // .. | ||
| 9539 | EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), | ||
| 9540 | // .. INP_POWER = 0x0 | ||
| 9541 | // .. ==> 0XF8000B44[0:0] = 0x00000000U | ||
| 9542 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 9543 | // .. INP_TYPE = 0x0 | ||
| 9544 | // .. ==> 0XF8000B44[2:1] = 0x00000000U | ||
| 9545 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
| 9546 | // .. DCI_UPDATE = 0x0 | ||
| 9547 | // .. ==> 0XF8000B44[3:3] = 0x00000000U | ||
| 9548 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 9549 | // .. TERM_EN = 0x0 | ||
| 9550 | // .. ==> 0XF8000B44[4:4] = 0x00000000U | ||
| 9551 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 9552 | // .. DCR_TYPE = 0x0 | ||
| 9553 | // .. ==> 0XF8000B44[6:5] = 0x00000000U | ||
| 9554 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
| 9555 | // .. IBUF_DISABLE_MODE = 0x0 | ||
| 9556 | // .. ==> 0XF8000B44[7:7] = 0x00000000U | ||
| 9557 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 9558 | // .. TERM_DISABLE_MODE = 0x0 | ||
| 9559 | // .. ==> 0XF8000B44[8:8] = 0x00000000U | ||
| 9560 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 9561 | // .. OUTPUT_EN = 0x3 | ||
| 9562 | // .. ==> 0XF8000B44[10:9] = 0x00000003U | ||
| 9563 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 9564 | // .. PULLUP_EN = 0x0 | ||
| 9565 | // .. ==> 0XF8000B44[11:11] = 0x00000000U | ||
| 9566 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 9567 | // .. | ||
| 9568 | EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), | ||
| 9569 | // .. INP_POWER = 0x0 | ||
| 9570 | // .. ==> 0XF8000B48[0:0] = 0x00000000U | ||
| 9571 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 9572 | // .. INP_TYPE = 0x1 | ||
| 9573 | // .. ==> 0XF8000B48[2:1] = 0x00000001U | ||
| 9574 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | ||
| 9575 | // .. DCI_UPDATE = 0x0 | ||
| 9576 | // .. ==> 0XF8000B48[3:3] = 0x00000000U | ||
| 9577 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 9578 | // .. TERM_EN = 0x1 | ||
| 9579 | // .. ==> 0XF8000B48[4:4] = 0x00000001U | ||
| 9580 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 9581 | // .. DCR_TYPE = 0x3 | ||
| 9582 | // .. ==> 0XF8000B48[6:5] = 0x00000003U | ||
| 9583 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
| 9584 | // .. IBUF_DISABLE_MODE = 0 | ||
| 9585 | // .. ==> 0XF8000B48[7:7] = 0x00000000U | ||
| 9586 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 9587 | // .. TERM_DISABLE_MODE = 0 | ||
| 9588 | // .. ==> 0XF8000B48[8:8] = 0x00000000U | ||
| 9589 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 9590 | // .. OUTPUT_EN = 0x3 | ||
| 9591 | // .. ==> 0XF8000B48[10:9] = 0x00000003U | ||
| 9592 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 9593 | // .. PULLUP_EN = 0x0 | ||
| 9594 | // .. ==> 0XF8000B48[11:11] = 0x00000000U | ||
| 9595 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 9596 | // .. | ||
| 9597 | EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), | ||
| 9598 | // .. INP_POWER = 0x0 | ||
| 9599 | // .. ==> 0XF8000B4C[0:0] = 0x00000000U | ||
| 9600 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 9601 | // .. INP_TYPE = 0x1 | ||
| 9602 | // .. ==> 0XF8000B4C[2:1] = 0x00000001U | ||
| 9603 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | ||
| 9604 | // .. DCI_UPDATE = 0x0 | ||
| 9605 | // .. ==> 0XF8000B4C[3:3] = 0x00000000U | ||
| 9606 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 9607 | // .. TERM_EN = 0x1 | ||
| 9608 | // .. ==> 0XF8000B4C[4:4] = 0x00000001U | ||
| 9609 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 9610 | // .. DCR_TYPE = 0x3 | ||
| 9611 | // .. ==> 0XF8000B4C[6:5] = 0x00000003U | ||
| 9612 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
| 9613 | // .. IBUF_DISABLE_MODE = 0 | ||
| 9614 | // .. ==> 0XF8000B4C[7:7] = 0x00000000U | ||
| 9615 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 9616 | // .. TERM_DISABLE_MODE = 0 | ||
| 9617 | // .. ==> 0XF8000B4C[8:8] = 0x00000000U | ||
| 9618 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 9619 | // .. OUTPUT_EN = 0x3 | ||
| 9620 | // .. ==> 0XF8000B4C[10:9] = 0x00000003U | ||
| 9621 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 9622 | // .. PULLUP_EN = 0x0 | ||
| 9623 | // .. ==> 0XF8000B4C[11:11] = 0x00000000U | ||
| 9624 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 9625 | // .. | ||
| 9626 | EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), | ||
| 9627 | // .. INP_POWER = 0x0 | ||
| 9628 | // .. ==> 0XF8000B50[0:0] = 0x00000000U | ||
| 9629 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 9630 | // .. INP_TYPE = 0x2 | ||
| 9631 | // .. ==> 0XF8000B50[2:1] = 0x00000002U | ||
| 9632 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | ||
| 9633 | // .. DCI_UPDATE = 0x0 | ||
| 9634 | // .. ==> 0XF8000B50[3:3] = 0x00000000U | ||
| 9635 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 9636 | // .. TERM_EN = 0x1 | ||
| 9637 | // .. ==> 0XF8000B50[4:4] = 0x00000001U | ||
| 9638 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 9639 | // .. DCR_TYPE = 0x3 | ||
| 9640 | // .. ==> 0XF8000B50[6:5] = 0x00000003U | ||
| 9641 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
| 9642 | // .. IBUF_DISABLE_MODE = 0 | ||
| 9643 | // .. ==> 0XF8000B50[7:7] = 0x00000000U | ||
| 9644 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 9645 | // .. TERM_DISABLE_MODE = 0 | ||
| 9646 | // .. ==> 0XF8000B50[8:8] = 0x00000000U | ||
| 9647 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 9648 | // .. OUTPUT_EN = 0x3 | ||
| 9649 | // .. ==> 0XF8000B50[10:9] = 0x00000003U | ||
| 9650 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 9651 | // .. PULLUP_EN = 0x0 | ||
| 9652 | // .. ==> 0XF8000B50[11:11] = 0x00000000U | ||
| 9653 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 9654 | // .. | ||
| 9655 | EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), | ||
| 9656 | // .. INP_POWER = 0x0 | ||
| 9657 | // .. ==> 0XF8000B54[0:0] = 0x00000000U | ||
| 9658 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 9659 | // .. INP_TYPE = 0x2 | ||
| 9660 | // .. ==> 0XF8000B54[2:1] = 0x00000002U | ||
| 9661 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | ||
| 9662 | // .. DCI_UPDATE = 0x0 | ||
| 9663 | // .. ==> 0XF8000B54[3:3] = 0x00000000U | ||
| 9664 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 9665 | // .. TERM_EN = 0x1 | ||
| 9666 | // .. ==> 0XF8000B54[4:4] = 0x00000001U | ||
| 9667 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 9668 | // .. DCR_TYPE = 0x3 | ||
| 9669 | // .. ==> 0XF8000B54[6:5] = 0x00000003U | ||
| 9670 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
| 9671 | // .. IBUF_DISABLE_MODE = 0 | ||
| 9672 | // .. ==> 0XF8000B54[7:7] = 0x00000000U | ||
| 9673 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 9674 | // .. TERM_DISABLE_MODE = 0 | ||
| 9675 | // .. ==> 0XF8000B54[8:8] = 0x00000000U | ||
| 9676 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 9677 | // .. OUTPUT_EN = 0x3 | ||
| 9678 | // .. ==> 0XF8000B54[10:9] = 0x00000003U | ||
| 9679 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 9680 | // .. PULLUP_EN = 0x0 | ||
| 9681 | // .. ==> 0XF8000B54[11:11] = 0x00000000U | ||
| 9682 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 9683 | // .. | ||
| 9684 | EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), | ||
| 9685 | // .. INP_POWER = 0x0 | ||
| 9686 | // .. ==> 0XF8000B58[0:0] = 0x00000000U | ||
| 9687 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 9688 | // .. INP_TYPE = 0x0 | ||
| 9689 | // .. ==> 0XF8000B58[2:1] = 0x00000000U | ||
| 9690 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
| 9691 | // .. DCI_UPDATE = 0x0 | ||
| 9692 | // .. ==> 0XF8000B58[3:3] = 0x00000000U | ||
| 9693 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 9694 | // .. TERM_EN = 0x0 | ||
| 9695 | // .. ==> 0XF8000B58[4:4] = 0x00000000U | ||
| 9696 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 9697 | // .. DCR_TYPE = 0x0 | ||
| 9698 | // .. ==> 0XF8000B58[6:5] = 0x00000000U | ||
| 9699 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
| 9700 | // .. IBUF_DISABLE_MODE = 0x0 | ||
| 9701 | // .. ==> 0XF8000B58[7:7] = 0x00000000U | ||
| 9702 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 9703 | // .. TERM_DISABLE_MODE = 0x0 | ||
| 9704 | // .. ==> 0XF8000B58[8:8] = 0x00000000U | ||
| 9705 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 9706 | // .. OUTPUT_EN = 0x3 | ||
| 9707 | // .. ==> 0XF8000B58[10:9] = 0x00000003U | ||
| 9708 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
| 9709 | // .. PULLUP_EN = 0x0 | ||
| 9710 | // .. ==> 0XF8000B58[11:11] = 0x00000000U | ||
| 9711 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 9712 | // .. | ||
| 9713 | EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), | ||
| 9714 | // .. DRIVE_P = 0x1c | ||
| 9715 | // .. ==> 0XF8000B5C[6:0] = 0x0000001CU | ||
| 9716 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
| 9717 | // .. DRIVE_N = 0xc | ||
| 9718 | // .. ==> 0XF8000B5C[13:7] = 0x0000000CU | ||
| 9719 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
| 9720 | // .. SLEW_P = 0x3 | ||
| 9721 | // .. ==> 0XF8000B5C[18:14] = 0x00000003U | ||
| 9722 | // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U | ||
| 9723 | // .. SLEW_N = 0x3 | ||
| 9724 | // .. ==> 0XF8000B5C[23:19] = 0x00000003U | ||
| 9725 | // .. ==> MASK : 0x00F80000U VAL : 0x00180000U | ||
| 9726 | // .. GTL = 0x0 | ||
| 9727 | // .. ==> 0XF8000B5C[26:24] = 0x00000000U | ||
| 9728 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
| 9729 | // .. RTERM = 0x0 | ||
| 9730 | // .. ==> 0XF8000B5C[31:27] = 0x00000000U | ||
| 9731 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
| 9732 | // .. | ||
| 9733 | EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), | ||
| 9734 | // .. DRIVE_P = 0x1c | ||
| 9735 | // .. ==> 0XF8000B60[6:0] = 0x0000001CU | ||
| 9736 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
| 9737 | // .. DRIVE_N = 0xc | ||
| 9738 | // .. ==> 0XF8000B60[13:7] = 0x0000000CU | ||
| 9739 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
| 9740 | // .. SLEW_P = 0x6 | ||
| 9741 | // .. ==> 0XF8000B60[18:14] = 0x00000006U | ||
| 9742 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
| 9743 | // .. SLEW_N = 0x1f | ||
| 9744 | // .. ==> 0XF8000B60[23:19] = 0x0000001FU | ||
| 9745 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
| 9746 | // .. GTL = 0x0 | ||
| 9747 | // .. ==> 0XF8000B60[26:24] = 0x00000000U | ||
| 9748 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
| 9749 | // .. RTERM = 0x0 | ||
| 9750 | // .. ==> 0XF8000B60[31:27] = 0x00000000U | ||
| 9751 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
| 9752 | // .. | ||
| 9753 | EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), | ||
| 9754 | // .. DRIVE_P = 0x1c | ||
| 9755 | // .. ==> 0XF8000B64[6:0] = 0x0000001CU | ||
| 9756 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
| 9757 | // .. DRIVE_N = 0xc | ||
| 9758 | // .. ==> 0XF8000B64[13:7] = 0x0000000CU | ||
| 9759 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
| 9760 | // .. SLEW_P = 0x6 | ||
| 9761 | // .. ==> 0XF8000B64[18:14] = 0x00000006U | ||
| 9762 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
| 9763 | // .. SLEW_N = 0x1f | ||
| 9764 | // .. ==> 0XF8000B64[23:19] = 0x0000001FU | ||
| 9765 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
| 9766 | // .. GTL = 0x0 | ||
| 9767 | // .. ==> 0XF8000B64[26:24] = 0x00000000U | ||
| 9768 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
| 9769 | // .. RTERM = 0x0 | ||
| 9770 | // .. ==> 0XF8000B64[31:27] = 0x00000000U | ||
| 9771 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
| 9772 | // .. | ||
| 9773 | EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), | ||
| 9774 | // .. DRIVE_P = 0x1c | ||
| 9775 | // .. ==> 0XF8000B68[6:0] = 0x0000001CU | ||
| 9776 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
| 9777 | // .. DRIVE_N = 0xc | ||
| 9778 | // .. ==> 0XF8000B68[13:7] = 0x0000000CU | ||
| 9779 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
| 9780 | // .. SLEW_P = 0x6 | ||
| 9781 | // .. ==> 0XF8000B68[18:14] = 0x00000006U | ||
| 9782 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
| 9783 | // .. SLEW_N = 0x1f | ||
| 9784 | // .. ==> 0XF8000B68[23:19] = 0x0000001FU | ||
| 9785 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
| 9786 | // .. GTL = 0x0 | ||
| 9787 | // .. ==> 0XF8000B68[26:24] = 0x00000000U | ||
| 9788 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
| 9789 | // .. RTERM = 0x0 | ||
| 9790 | // .. ==> 0XF8000B68[31:27] = 0x00000000U | ||
| 9791 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
| 9792 | // .. | ||
| 9793 | EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), | ||
| 9794 | // .. VREF_INT_EN = 0x0 | ||
| 9795 | // .. ==> 0XF8000B6C[0:0] = 0x00000000U | ||
| 9796 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 9797 | // .. VREF_SEL = 0x0 | ||
| 9798 | // .. ==> 0XF8000B6C[4:1] = 0x00000000U | ||
| 9799 | // .. ==> MASK : 0x0000001EU VAL : 0x00000000U | ||
| 9800 | // .. VREF_EXT_EN = 0x3 | ||
| 9801 | // .. ==> 0XF8000B6C[6:5] = 0x00000003U | ||
| 9802 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
| 9803 | // .. VREF_PULLUP_EN = 0x0 | ||
| 9804 | // .. ==> 0XF8000B6C[8:7] = 0x00000000U | ||
| 9805 | // .. ==> MASK : 0x00000180U VAL : 0x00000000U | ||
| 9806 | // .. REFIO_EN = 0x1 | ||
| 9807 | // .. ==> 0XF8000B6C[9:9] = 0x00000001U | ||
| 9808 | // .. ==> MASK : 0x00000200U VAL : 0x00000200U | ||
| 9809 | // .. REFIO_PULLUP_EN = 0x0 | ||
| 9810 | // .. ==> 0XF8000B6C[12:12] = 0x00000000U | ||
| 9811 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 9812 | // .. DRST_B_PULLUP_EN = 0x0 | ||
| 9813 | // .. ==> 0XF8000B6C[13:13] = 0x00000000U | ||
| 9814 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 9815 | // .. CKE_PULLUP_EN = 0x0 | ||
| 9816 | // .. ==> 0XF8000B6C[14:14] = 0x00000000U | ||
| 9817 | // .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
| 9818 | // .. | ||
| 9819 | EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U), | ||
| 9820 | // .. .. START: ASSERT RESET | ||
| 9821 | // .. .. RESET = 1 | ||
| 9822 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | ||
| 9823 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 9824 | // .. .. VRN_OUT = 0x1 | ||
| 9825 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | ||
| 9826 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | ||
| 9827 | // .. .. | ||
| 9828 | EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), | ||
| 9829 | // .. .. FINISH: ASSERT RESET | ||
| 9830 | // .. .. START: DEASSERT RESET | ||
| 9831 | // .. .. RESET = 0 | ||
| 9832 | // .. .. ==> 0XF8000B70[0:0] = 0x00000000U | ||
| 9833 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 9834 | // .. .. VRN_OUT = 0x1 | ||
| 9835 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | ||
| 9836 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | ||
| 9837 | // .. .. | ||
| 9838 | EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), | ||
| 9839 | // .. .. FINISH: DEASSERT RESET | ||
| 9840 | // .. .. RESET = 0x1 | ||
| 9841 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | ||
| 9842 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 9843 | // .. .. ENABLE = 0x1 | ||
| 9844 | // .. .. ==> 0XF8000B70[1:1] = 0x00000001U | ||
| 9845 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 9846 | // .. .. VRP_TRI = 0x0 | ||
| 9847 | // .. .. ==> 0XF8000B70[2:2] = 0x00000000U | ||
| 9848 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 9849 | // .. .. VRN_TRI = 0x0 | ||
| 9850 | // .. .. ==> 0XF8000B70[3:3] = 0x00000000U | ||
| 9851 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 9852 | // .. .. VRP_OUT = 0x0 | ||
| 9853 | // .. .. ==> 0XF8000B70[4:4] = 0x00000000U | ||
| 9854 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
| 9855 | // .. .. VRN_OUT = 0x1 | ||
| 9856 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | ||
| 9857 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | ||
| 9858 | // .. .. NREF_OPT1 = 0x0 | ||
| 9859 | // .. .. ==> 0XF8000B70[7:6] = 0x00000000U | ||
| 9860 | // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U | ||
| 9861 | // .. .. NREF_OPT2 = 0x0 | ||
| 9862 | // .. .. ==> 0XF8000B70[10:8] = 0x00000000U | ||
| 9863 | // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U | ||
| 9864 | // .. .. NREF_OPT4 = 0x1 | ||
| 9865 | // .. .. ==> 0XF8000B70[13:11] = 0x00000001U | ||
| 9866 | // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U | ||
| 9867 | // .. .. PREF_OPT1 = 0x0 | ||
| 9868 | // .. .. ==> 0XF8000B70[16:14] = 0x00000000U | ||
| 9869 | // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U | ||
| 9870 | // .. .. PREF_OPT2 = 0x0 | ||
| 9871 | // .. .. ==> 0XF8000B70[19:17] = 0x00000000U | ||
| 9872 | // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U | ||
| 9873 | // .. .. UPDATE_CONTROL = 0x0 | ||
| 9874 | // .. .. ==> 0XF8000B70[20:20] = 0x00000000U | ||
| 9875 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
| 9876 | // .. .. INIT_COMPLETE = 0x0 | ||
| 9877 | // .. .. ==> 0XF8000B70[21:21] = 0x00000000U | ||
| 9878 | // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U | ||
| 9879 | // .. .. TST_CLK = 0x0 | ||
| 9880 | // .. .. ==> 0XF8000B70[22:22] = 0x00000000U | ||
| 9881 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
| 9882 | // .. .. TST_HLN = 0x0 | ||
| 9883 | // .. .. ==> 0XF8000B70[23:23] = 0x00000000U | ||
| 9884 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
| 9885 | // .. .. TST_HLP = 0x0 | ||
| 9886 | // .. .. ==> 0XF8000B70[24:24] = 0x00000000U | ||
| 9887 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
| 9888 | // .. .. TST_RST = 0x0 | ||
| 9889 | // .. .. ==> 0XF8000B70[25:25] = 0x00000000U | ||
| 9890 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
| 9891 | // .. .. INT_DCI_EN = 0x0 | ||
| 9892 | // .. .. ==> 0XF8000B70[26:26] = 0x00000000U | ||
| 9893 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | ||
| 9894 | // .. .. | ||
| 9895 | EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), | ||
| 9896 | // .. FINISH: DDRIOB SETTINGS | ||
| 9897 | // .. START: MIO PROGRAMMING | ||
| 9898 | // .. TRI_ENABLE = 0 | ||
| 9899 | // .. ==> 0XF8000704[0:0] = 0x00000000U | ||
| 9900 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 9901 | // .. L0_SEL = 1 | ||
| 9902 | // .. ==> 0XF8000704[1:1] = 0x00000001U | ||
| 9903 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 9904 | // .. L1_SEL = 0 | ||
| 9905 | // .. ==> 0XF8000704[2:2] = 0x00000000U | ||
| 9906 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 9907 | // .. L2_SEL = 0 | ||
| 9908 | // .. ==> 0XF8000704[4:3] = 0x00000000U | ||
| 9909 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 9910 | // .. L3_SEL = 0 | ||
| 9911 | // .. ==> 0XF8000704[7:5] = 0x00000000U | ||
| 9912 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 9913 | // .. Speed = 1 | ||
| 9914 | // .. ==> 0XF8000704[8:8] = 0x00000001U | ||
| 9915 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 9916 | // .. IO_Type = 3 | ||
| 9917 | // .. ==> 0XF8000704[11:9] = 0x00000003U | ||
| 9918 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 9919 | // .. PULLUP = 0 | ||
| 9920 | // .. ==> 0XF8000704[12:12] = 0x00000000U | ||
| 9921 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 9922 | // .. DisableRcvr = 0 | ||
| 9923 | // .. ==> 0XF8000704[13:13] = 0x00000000U | ||
| 9924 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 9925 | // .. | ||
| 9926 | EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U), | ||
| 9927 | // .. TRI_ENABLE = 0 | ||
| 9928 | // .. ==> 0XF8000708[0:0] = 0x00000000U | ||
| 9929 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 9930 | // .. L0_SEL = 1 | ||
| 9931 | // .. ==> 0XF8000708[1:1] = 0x00000001U | ||
| 9932 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 9933 | // .. L1_SEL = 0 | ||
| 9934 | // .. ==> 0XF8000708[2:2] = 0x00000000U | ||
| 9935 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 9936 | // .. L2_SEL = 0 | ||
| 9937 | // .. ==> 0XF8000708[4:3] = 0x00000000U | ||
| 9938 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 9939 | // .. L3_SEL = 0 | ||
| 9940 | // .. ==> 0XF8000708[7:5] = 0x00000000U | ||
| 9941 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 9942 | // .. Speed = 1 | ||
| 9943 | // .. ==> 0XF8000708[8:8] = 0x00000001U | ||
| 9944 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 9945 | // .. IO_Type = 3 | ||
| 9946 | // .. ==> 0XF8000708[11:9] = 0x00000003U | ||
| 9947 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 9948 | // .. PULLUP = 0 | ||
| 9949 | // .. ==> 0XF8000708[12:12] = 0x00000000U | ||
| 9950 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 9951 | // .. DisableRcvr = 0 | ||
| 9952 | // .. ==> 0XF8000708[13:13] = 0x00000000U | ||
| 9953 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 9954 | // .. | ||
| 9955 | EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U), | ||
| 9956 | // .. TRI_ENABLE = 0 | ||
| 9957 | // .. ==> 0XF800070C[0:0] = 0x00000000U | ||
| 9958 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 9959 | // .. L0_SEL = 1 | ||
| 9960 | // .. ==> 0XF800070C[1:1] = 0x00000001U | ||
| 9961 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 9962 | // .. L1_SEL = 0 | ||
| 9963 | // .. ==> 0XF800070C[2:2] = 0x00000000U | ||
| 9964 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 9965 | // .. L2_SEL = 0 | ||
| 9966 | // .. ==> 0XF800070C[4:3] = 0x00000000U | ||
| 9967 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 9968 | // .. L3_SEL = 0 | ||
| 9969 | // .. ==> 0XF800070C[7:5] = 0x00000000U | ||
| 9970 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 9971 | // .. Speed = 1 | ||
| 9972 | // .. ==> 0XF800070C[8:8] = 0x00000001U | ||
| 9973 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 9974 | // .. IO_Type = 3 | ||
| 9975 | // .. ==> 0XF800070C[11:9] = 0x00000003U | ||
| 9976 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 9977 | // .. PULLUP = 0 | ||
| 9978 | // .. ==> 0XF800070C[12:12] = 0x00000000U | ||
| 9979 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 9980 | // .. DisableRcvr = 0 | ||
| 9981 | // .. ==> 0XF800070C[13:13] = 0x00000000U | ||
| 9982 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 9983 | // .. | ||
| 9984 | EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U), | ||
| 9985 | // .. TRI_ENABLE = 0 | ||
| 9986 | // .. ==> 0XF8000710[0:0] = 0x00000000U | ||
| 9987 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 9988 | // .. L0_SEL = 1 | ||
| 9989 | // .. ==> 0XF8000710[1:1] = 0x00000001U | ||
| 9990 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 9991 | // .. L1_SEL = 0 | ||
| 9992 | // .. ==> 0XF8000710[2:2] = 0x00000000U | ||
| 9993 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 9994 | // .. L2_SEL = 0 | ||
| 9995 | // .. ==> 0XF8000710[4:3] = 0x00000000U | ||
| 9996 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 9997 | // .. L3_SEL = 0 | ||
| 9998 | // .. ==> 0XF8000710[7:5] = 0x00000000U | ||
| 9999 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10000 | // .. Speed = 1 | ||
| 10001 | // .. ==> 0XF8000710[8:8] = 0x00000001U | ||
| 10002 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10003 | // .. IO_Type = 3 | ||
| 10004 | // .. ==> 0XF8000710[11:9] = 0x00000003U | ||
| 10005 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 10006 | // .. PULLUP = 0 | ||
| 10007 | // .. ==> 0XF8000710[12:12] = 0x00000000U | ||
| 10008 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10009 | // .. DisableRcvr = 0 | ||
| 10010 | // .. ==> 0XF8000710[13:13] = 0x00000000U | ||
| 10011 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10012 | // .. | ||
| 10013 | EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U), | ||
| 10014 | // .. TRI_ENABLE = 0 | ||
| 10015 | // .. ==> 0XF8000714[0:0] = 0x00000000U | ||
| 10016 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10017 | // .. L0_SEL = 1 | ||
| 10018 | // .. ==> 0XF8000714[1:1] = 0x00000001U | ||
| 10019 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 10020 | // .. L1_SEL = 0 | ||
| 10021 | // .. ==> 0XF8000714[2:2] = 0x00000000U | ||
| 10022 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10023 | // .. L2_SEL = 0 | ||
| 10024 | // .. ==> 0XF8000714[4:3] = 0x00000000U | ||
| 10025 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10026 | // .. L3_SEL = 0 | ||
| 10027 | // .. ==> 0XF8000714[7:5] = 0x00000000U | ||
| 10028 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10029 | // .. Speed = 1 | ||
| 10030 | // .. ==> 0XF8000714[8:8] = 0x00000001U | ||
| 10031 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10032 | // .. IO_Type = 3 | ||
| 10033 | // .. ==> 0XF8000714[11:9] = 0x00000003U | ||
| 10034 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 10035 | // .. PULLUP = 0 | ||
| 10036 | // .. ==> 0XF8000714[12:12] = 0x00000000U | ||
| 10037 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10038 | // .. DisableRcvr = 0 | ||
| 10039 | // .. ==> 0XF8000714[13:13] = 0x00000000U | ||
| 10040 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10041 | // .. | ||
| 10042 | EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U), | ||
| 10043 | // .. TRI_ENABLE = 0 | ||
| 10044 | // .. ==> 0XF8000718[0:0] = 0x00000000U | ||
| 10045 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10046 | // .. L0_SEL = 1 | ||
| 10047 | // .. ==> 0XF8000718[1:1] = 0x00000001U | ||
| 10048 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 10049 | // .. L1_SEL = 0 | ||
| 10050 | // .. ==> 0XF8000718[2:2] = 0x00000000U | ||
| 10051 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10052 | // .. L2_SEL = 0 | ||
| 10053 | // .. ==> 0XF8000718[4:3] = 0x00000000U | ||
| 10054 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10055 | // .. L3_SEL = 0 | ||
| 10056 | // .. ==> 0XF8000718[7:5] = 0x00000000U | ||
| 10057 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10058 | // .. Speed = 1 | ||
| 10059 | // .. ==> 0XF8000718[8:8] = 0x00000001U | ||
| 10060 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10061 | // .. IO_Type = 3 | ||
| 10062 | // .. ==> 0XF8000718[11:9] = 0x00000003U | ||
| 10063 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
| 10064 | // .. PULLUP = 0 | ||
| 10065 | // .. ==> 0XF8000718[12:12] = 0x00000000U | ||
| 10066 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10067 | // .. DisableRcvr = 0 | ||
| 10068 | // .. ==> 0XF8000718[13:13] = 0x00000000U | ||
| 10069 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10070 | // .. | ||
| 10071 | EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U), | ||
| 10072 | // .. TRI_ENABLE = 0 | ||
| 10073 | // .. ==> 0XF8000740[0:0] = 0x00000000U | ||
| 10074 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10075 | // .. L0_SEL = 1 | ||
| 10076 | // .. ==> 0XF8000740[1:1] = 0x00000001U | ||
| 10077 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 10078 | // .. L1_SEL = 0 | ||
| 10079 | // .. ==> 0XF8000740[2:2] = 0x00000000U | ||
| 10080 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10081 | // .. L2_SEL = 0 | ||
| 10082 | // .. ==> 0XF8000740[4:3] = 0x00000000U | ||
| 10083 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10084 | // .. L3_SEL = 0 | ||
| 10085 | // .. ==> 0XF8000740[7:5] = 0x00000000U | ||
| 10086 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10087 | // .. Speed = 1 | ||
| 10088 | // .. ==> 0XF8000740[8:8] = 0x00000001U | ||
| 10089 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10090 | // .. IO_Type = 4 | ||
| 10091 | // .. ==> 0XF8000740[11:9] = 0x00000004U | ||
| 10092 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 10093 | // .. PULLUP = 0 | ||
| 10094 | // .. ==> 0XF8000740[12:12] = 0x00000000U | ||
| 10095 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10096 | // .. DisableRcvr = 1 | ||
| 10097 | // .. ==> 0XF8000740[13:13] = 0x00000001U | ||
| 10098 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 10099 | // .. | ||
| 10100 | EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U), | ||
| 10101 | // .. TRI_ENABLE = 0 | ||
| 10102 | // .. ==> 0XF8000744[0:0] = 0x00000000U | ||
| 10103 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10104 | // .. L0_SEL = 1 | ||
| 10105 | // .. ==> 0XF8000744[1:1] = 0x00000001U | ||
| 10106 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 10107 | // .. L1_SEL = 0 | ||
| 10108 | // .. ==> 0XF8000744[2:2] = 0x00000000U | ||
| 10109 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10110 | // .. L2_SEL = 0 | ||
| 10111 | // .. ==> 0XF8000744[4:3] = 0x00000000U | ||
| 10112 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10113 | // .. L3_SEL = 0 | ||
| 10114 | // .. ==> 0XF8000744[7:5] = 0x00000000U | ||
| 10115 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10116 | // .. Speed = 1 | ||
| 10117 | // .. ==> 0XF8000744[8:8] = 0x00000001U | ||
| 10118 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10119 | // .. IO_Type = 4 | ||
| 10120 | // .. ==> 0XF8000744[11:9] = 0x00000004U | ||
| 10121 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 10122 | // .. PULLUP = 0 | ||
| 10123 | // .. ==> 0XF8000744[12:12] = 0x00000000U | ||
| 10124 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10125 | // .. DisableRcvr = 1 | ||
| 10126 | // .. ==> 0XF8000744[13:13] = 0x00000001U | ||
| 10127 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 10128 | // .. | ||
| 10129 | EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U), | ||
| 10130 | // .. TRI_ENABLE = 0 | ||
| 10131 | // .. ==> 0XF8000748[0:0] = 0x00000000U | ||
| 10132 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10133 | // .. L0_SEL = 1 | ||
| 10134 | // .. ==> 0XF8000748[1:1] = 0x00000001U | ||
| 10135 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 10136 | // .. L1_SEL = 0 | ||
| 10137 | // .. ==> 0XF8000748[2:2] = 0x00000000U | ||
| 10138 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10139 | // .. L2_SEL = 0 | ||
| 10140 | // .. ==> 0XF8000748[4:3] = 0x00000000U | ||
| 10141 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10142 | // .. L3_SEL = 0 | ||
| 10143 | // .. ==> 0XF8000748[7:5] = 0x00000000U | ||
| 10144 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10145 | // .. Speed = 1 | ||
| 10146 | // .. ==> 0XF8000748[8:8] = 0x00000001U | ||
| 10147 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10148 | // .. IO_Type = 4 | ||
| 10149 | // .. ==> 0XF8000748[11:9] = 0x00000004U | ||
| 10150 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 10151 | // .. PULLUP = 0 | ||
| 10152 | // .. ==> 0XF8000748[12:12] = 0x00000000U | ||
| 10153 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10154 | // .. DisableRcvr = 1 | ||
| 10155 | // .. ==> 0XF8000748[13:13] = 0x00000001U | ||
| 10156 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 10157 | // .. | ||
| 10158 | EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U), | ||
| 10159 | // .. TRI_ENABLE = 0 | ||
| 10160 | // .. ==> 0XF800074C[0:0] = 0x00000000U | ||
| 10161 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10162 | // .. L0_SEL = 1 | ||
| 10163 | // .. ==> 0XF800074C[1:1] = 0x00000001U | ||
| 10164 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 10165 | // .. L1_SEL = 0 | ||
| 10166 | // .. ==> 0XF800074C[2:2] = 0x00000000U | ||
| 10167 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10168 | // .. L2_SEL = 0 | ||
| 10169 | // .. ==> 0XF800074C[4:3] = 0x00000000U | ||
| 10170 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10171 | // .. L3_SEL = 0 | ||
| 10172 | // .. ==> 0XF800074C[7:5] = 0x00000000U | ||
| 10173 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10174 | // .. Speed = 1 | ||
| 10175 | // .. ==> 0XF800074C[8:8] = 0x00000001U | ||
| 10176 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10177 | // .. IO_Type = 4 | ||
| 10178 | // .. ==> 0XF800074C[11:9] = 0x00000004U | ||
| 10179 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 10180 | // .. PULLUP = 0 | ||
| 10181 | // .. ==> 0XF800074C[12:12] = 0x00000000U | ||
| 10182 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10183 | // .. DisableRcvr = 1 | ||
| 10184 | // .. ==> 0XF800074C[13:13] = 0x00000001U | ||
| 10185 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 10186 | // .. | ||
| 10187 | EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U), | ||
| 10188 | // .. TRI_ENABLE = 0 | ||
| 10189 | // .. ==> 0XF8000750[0:0] = 0x00000000U | ||
| 10190 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10191 | // .. L0_SEL = 1 | ||
| 10192 | // .. ==> 0XF8000750[1:1] = 0x00000001U | ||
| 10193 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 10194 | // .. L1_SEL = 0 | ||
| 10195 | // .. ==> 0XF8000750[2:2] = 0x00000000U | ||
| 10196 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10197 | // .. L2_SEL = 0 | ||
| 10198 | // .. ==> 0XF8000750[4:3] = 0x00000000U | ||
| 10199 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10200 | // .. L3_SEL = 0 | ||
| 10201 | // .. ==> 0XF8000750[7:5] = 0x00000000U | ||
| 10202 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10203 | // .. Speed = 1 | ||
| 10204 | // .. ==> 0XF8000750[8:8] = 0x00000001U | ||
| 10205 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10206 | // .. IO_Type = 4 | ||
| 10207 | // .. ==> 0XF8000750[11:9] = 0x00000004U | ||
| 10208 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 10209 | // .. PULLUP = 0 | ||
| 10210 | // .. ==> 0XF8000750[12:12] = 0x00000000U | ||
| 10211 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10212 | // .. DisableRcvr = 1 | ||
| 10213 | // .. ==> 0XF8000750[13:13] = 0x00000001U | ||
| 10214 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 10215 | // .. | ||
| 10216 | EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U), | ||
| 10217 | // .. TRI_ENABLE = 0 | ||
| 10218 | // .. ==> 0XF8000754[0:0] = 0x00000000U | ||
| 10219 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10220 | // .. L0_SEL = 1 | ||
| 10221 | // .. ==> 0XF8000754[1:1] = 0x00000001U | ||
| 10222 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 10223 | // .. L1_SEL = 0 | ||
| 10224 | // .. ==> 0XF8000754[2:2] = 0x00000000U | ||
| 10225 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10226 | // .. L2_SEL = 0 | ||
| 10227 | // .. ==> 0XF8000754[4:3] = 0x00000000U | ||
| 10228 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10229 | // .. L3_SEL = 0 | ||
| 10230 | // .. ==> 0XF8000754[7:5] = 0x00000000U | ||
| 10231 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10232 | // .. Speed = 1 | ||
| 10233 | // .. ==> 0XF8000754[8:8] = 0x00000001U | ||
| 10234 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10235 | // .. IO_Type = 4 | ||
| 10236 | // .. ==> 0XF8000754[11:9] = 0x00000004U | ||
| 10237 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 10238 | // .. PULLUP = 0 | ||
| 10239 | // .. ==> 0XF8000754[12:12] = 0x00000000U | ||
| 10240 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10241 | // .. DisableRcvr = 1 | ||
| 10242 | // .. ==> 0XF8000754[13:13] = 0x00000001U | ||
| 10243 | // .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
| 10244 | // .. | ||
| 10245 | EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U), | ||
| 10246 | // .. TRI_ENABLE = 1 | ||
| 10247 | // .. ==> 0XF8000758[0:0] = 0x00000001U | ||
| 10248 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 10249 | // .. L0_SEL = 1 | ||
| 10250 | // .. ==> 0XF8000758[1:1] = 0x00000001U | ||
| 10251 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 10252 | // .. L1_SEL = 0 | ||
| 10253 | // .. ==> 0XF8000758[2:2] = 0x00000000U | ||
| 10254 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10255 | // .. L2_SEL = 0 | ||
| 10256 | // .. ==> 0XF8000758[4:3] = 0x00000000U | ||
| 10257 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10258 | // .. L3_SEL = 0 | ||
| 10259 | // .. ==> 0XF8000758[7:5] = 0x00000000U | ||
| 10260 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10261 | // .. Speed = 1 | ||
| 10262 | // .. ==> 0XF8000758[8:8] = 0x00000001U | ||
| 10263 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10264 | // .. IO_Type = 4 | ||
| 10265 | // .. ==> 0XF8000758[11:9] = 0x00000004U | ||
| 10266 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 10267 | // .. PULLUP = 0 | ||
| 10268 | // .. ==> 0XF8000758[12:12] = 0x00000000U | ||
| 10269 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10270 | // .. DisableRcvr = 0 | ||
| 10271 | // .. ==> 0XF8000758[13:13] = 0x00000000U | ||
| 10272 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10273 | // .. | ||
| 10274 | EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U), | ||
| 10275 | // .. TRI_ENABLE = 1 | ||
| 10276 | // .. ==> 0XF800075C[0:0] = 0x00000001U | ||
| 10277 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 10278 | // .. L0_SEL = 1 | ||
| 10279 | // .. ==> 0XF800075C[1:1] = 0x00000001U | ||
| 10280 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 10281 | // .. L1_SEL = 0 | ||
| 10282 | // .. ==> 0XF800075C[2:2] = 0x00000000U | ||
| 10283 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10284 | // .. L2_SEL = 0 | ||
| 10285 | // .. ==> 0XF800075C[4:3] = 0x00000000U | ||
| 10286 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10287 | // .. L3_SEL = 0 | ||
| 10288 | // .. ==> 0XF800075C[7:5] = 0x00000000U | ||
| 10289 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10290 | // .. Speed = 1 | ||
| 10291 | // .. ==> 0XF800075C[8:8] = 0x00000001U | ||
| 10292 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10293 | // .. IO_Type = 4 | ||
| 10294 | // .. ==> 0XF800075C[11:9] = 0x00000004U | ||
| 10295 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 10296 | // .. PULLUP = 0 | ||
| 10297 | // .. ==> 0XF800075C[12:12] = 0x00000000U | ||
| 10298 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10299 | // .. DisableRcvr = 0 | ||
| 10300 | // .. ==> 0XF800075C[13:13] = 0x00000000U | ||
| 10301 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10302 | // .. | ||
| 10303 | EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U), | ||
| 10304 | // .. TRI_ENABLE = 1 | ||
| 10305 | // .. ==> 0XF8000760[0:0] = 0x00000001U | ||
| 10306 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 10307 | // .. L0_SEL = 1 | ||
| 10308 | // .. ==> 0XF8000760[1:1] = 0x00000001U | ||
| 10309 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 10310 | // .. L1_SEL = 0 | ||
| 10311 | // .. ==> 0XF8000760[2:2] = 0x00000000U | ||
| 10312 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10313 | // .. L2_SEL = 0 | ||
| 10314 | // .. ==> 0XF8000760[4:3] = 0x00000000U | ||
| 10315 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10316 | // .. L3_SEL = 0 | ||
| 10317 | // .. ==> 0XF8000760[7:5] = 0x00000000U | ||
| 10318 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10319 | // .. Speed = 1 | ||
| 10320 | // .. ==> 0XF8000760[8:8] = 0x00000001U | ||
| 10321 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10322 | // .. IO_Type = 4 | ||
| 10323 | // .. ==> 0XF8000760[11:9] = 0x00000004U | ||
| 10324 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 10325 | // .. PULLUP = 0 | ||
| 10326 | // .. ==> 0XF8000760[12:12] = 0x00000000U | ||
| 10327 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10328 | // .. DisableRcvr = 0 | ||
| 10329 | // .. ==> 0XF8000760[13:13] = 0x00000000U | ||
| 10330 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10331 | // .. | ||
| 10332 | EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U), | ||
| 10333 | // .. TRI_ENABLE = 1 | ||
| 10334 | // .. ==> 0XF8000764[0:0] = 0x00000001U | ||
| 10335 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 10336 | // .. L0_SEL = 1 | ||
| 10337 | // .. ==> 0XF8000764[1:1] = 0x00000001U | ||
| 10338 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 10339 | // .. L1_SEL = 0 | ||
| 10340 | // .. ==> 0XF8000764[2:2] = 0x00000000U | ||
| 10341 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10342 | // .. L2_SEL = 0 | ||
| 10343 | // .. ==> 0XF8000764[4:3] = 0x00000000U | ||
| 10344 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10345 | // .. L3_SEL = 0 | ||
| 10346 | // .. ==> 0XF8000764[7:5] = 0x00000000U | ||
| 10347 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10348 | // .. Speed = 1 | ||
| 10349 | // .. ==> 0XF8000764[8:8] = 0x00000001U | ||
| 10350 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10351 | // .. IO_Type = 4 | ||
| 10352 | // .. ==> 0XF8000764[11:9] = 0x00000004U | ||
| 10353 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 10354 | // .. PULLUP = 0 | ||
| 10355 | // .. ==> 0XF8000764[12:12] = 0x00000000U | ||
| 10356 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10357 | // .. DisableRcvr = 0 | ||
| 10358 | // .. ==> 0XF8000764[13:13] = 0x00000000U | ||
| 10359 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10360 | // .. | ||
| 10361 | EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U), | ||
| 10362 | // .. TRI_ENABLE = 1 | ||
| 10363 | // .. ==> 0XF8000768[0:0] = 0x00000001U | ||
| 10364 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 10365 | // .. L0_SEL = 1 | ||
| 10366 | // .. ==> 0XF8000768[1:1] = 0x00000001U | ||
| 10367 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 10368 | // .. L1_SEL = 0 | ||
| 10369 | // .. ==> 0XF8000768[2:2] = 0x00000000U | ||
| 10370 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10371 | // .. L2_SEL = 0 | ||
| 10372 | // .. ==> 0XF8000768[4:3] = 0x00000000U | ||
| 10373 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10374 | // .. L3_SEL = 0 | ||
| 10375 | // .. ==> 0XF8000768[7:5] = 0x00000000U | ||
| 10376 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10377 | // .. Speed = 1 | ||
| 10378 | // .. ==> 0XF8000768[8:8] = 0x00000001U | ||
| 10379 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10380 | // .. IO_Type = 4 | ||
| 10381 | // .. ==> 0XF8000768[11:9] = 0x00000004U | ||
| 10382 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 10383 | // .. PULLUP = 0 | ||
| 10384 | // .. ==> 0XF8000768[12:12] = 0x00000000U | ||
| 10385 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10386 | // .. DisableRcvr = 0 | ||
| 10387 | // .. ==> 0XF8000768[13:13] = 0x00000000U | ||
| 10388 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10389 | // .. | ||
| 10390 | EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U), | ||
| 10391 | // .. TRI_ENABLE = 1 | ||
| 10392 | // .. ==> 0XF800076C[0:0] = 0x00000001U | ||
| 10393 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 10394 | // .. L0_SEL = 1 | ||
| 10395 | // .. ==> 0XF800076C[1:1] = 0x00000001U | ||
| 10396 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 10397 | // .. L1_SEL = 0 | ||
| 10398 | // .. ==> 0XF800076C[2:2] = 0x00000000U | ||
| 10399 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10400 | // .. L2_SEL = 0 | ||
| 10401 | // .. ==> 0XF800076C[4:3] = 0x00000000U | ||
| 10402 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10403 | // .. L3_SEL = 0 | ||
| 10404 | // .. ==> 0XF800076C[7:5] = 0x00000000U | ||
| 10405 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10406 | // .. Speed = 1 | ||
| 10407 | // .. ==> 0XF800076C[8:8] = 0x00000001U | ||
| 10408 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10409 | // .. IO_Type = 4 | ||
| 10410 | // .. ==> 0XF800076C[11:9] = 0x00000004U | ||
| 10411 | // .. ==> MASK : 0x00000E00U VAL : 0x00000800U | ||
| 10412 | // .. PULLUP = 0 | ||
| 10413 | // .. ==> 0XF800076C[12:12] = 0x00000000U | ||
| 10414 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10415 | // .. DisableRcvr = 0 | ||
| 10416 | // .. ==> 0XF800076C[13:13] = 0x00000000U | ||
| 10417 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10418 | // .. | ||
| 10419 | EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U), | ||
| 10420 | // .. TRI_ENABLE = 0 | ||
| 10421 | // .. ==> 0XF8000770[0:0] = 0x00000000U | ||
| 10422 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10423 | // .. L0_SEL = 0 | ||
| 10424 | // .. ==> 0XF8000770[1:1] = 0x00000000U | ||
| 10425 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10426 | // .. L1_SEL = 1 | ||
| 10427 | // .. ==> 0XF8000770[2:2] = 0x00000001U | ||
| 10428 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 10429 | // .. L2_SEL = 0 | ||
| 10430 | // .. ==> 0XF8000770[4:3] = 0x00000000U | ||
| 10431 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10432 | // .. L3_SEL = 0 | ||
| 10433 | // .. ==> 0XF8000770[7:5] = 0x00000000U | ||
| 10434 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10435 | // .. Speed = 1 | ||
| 10436 | // .. ==> 0XF8000770[8:8] = 0x00000001U | ||
| 10437 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10438 | // .. IO_Type = 1 | ||
| 10439 | // .. ==> 0XF8000770[11:9] = 0x00000001U | ||
| 10440 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10441 | // .. PULLUP = 0 | ||
| 10442 | // .. ==> 0XF8000770[12:12] = 0x00000000U | ||
| 10443 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10444 | // .. DisableRcvr = 0 | ||
| 10445 | // .. ==> 0XF8000770[13:13] = 0x00000000U | ||
| 10446 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10447 | // .. | ||
| 10448 | EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U), | ||
| 10449 | // .. TRI_ENABLE = 1 | ||
| 10450 | // .. ==> 0XF8000774[0:0] = 0x00000001U | ||
| 10451 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 10452 | // .. L0_SEL = 0 | ||
| 10453 | // .. ==> 0XF8000774[1:1] = 0x00000000U | ||
| 10454 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10455 | // .. L1_SEL = 1 | ||
| 10456 | // .. ==> 0XF8000774[2:2] = 0x00000001U | ||
| 10457 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 10458 | // .. L2_SEL = 0 | ||
| 10459 | // .. ==> 0XF8000774[4:3] = 0x00000000U | ||
| 10460 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10461 | // .. L3_SEL = 0 | ||
| 10462 | // .. ==> 0XF8000774[7:5] = 0x00000000U | ||
| 10463 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10464 | // .. Speed = 1 | ||
| 10465 | // .. ==> 0XF8000774[8:8] = 0x00000001U | ||
| 10466 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10467 | // .. IO_Type = 1 | ||
| 10468 | // .. ==> 0XF8000774[11:9] = 0x00000001U | ||
| 10469 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10470 | // .. PULLUP = 0 | ||
| 10471 | // .. ==> 0XF8000774[12:12] = 0x00000000U | ||
| 10472 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10473 | // .. DisableRcvr = 0 | ||
| 10474 | // .. ==> 0XF8000774[13:13] = 0x00000000U | ||
| 10475 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10476 | // .. | ||
| 10477 | EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U), | ||
| 10478 | // .. TRI_ENABLE = 0 | ||
| 10479 | // .. ==> 0XF8000778[0:0] = 0x00000000U | ||
| 10480 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10481 | // .. L0_SEL = 0 | ||
| 10482 | // .. ==> 0XF8000778[1:1] = 0x00000000U | ||
| 10483 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10484 | // .. L1_SEL = 1 | ||
| 10485 | // .. ==> 0XF8000778[2:2] = 0x00000001U | ||
| 10486 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 10487 | // .. L2_SEL = 0 | ||
| 10488 | // .. ==> 0XF8000778[4:3] = 0x00000000U | ||
| 10489 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10490 | // .. L3_SEL = 0 | ||
| 10491 | // .. ==> 0XF8000778[7:5] = 0x00000000U | ||
| 10492 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10493 | // .. Speed = 1 | ||
| 10494 | // .. ==> 0XF8000778[8:8] = 0x00000001U | ||
| 10495 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10496 | // .. IO_Type = 1 | ||
| 10497 | // .. ==> 0XF8000778[11:9] = 0x00000001U | ||
| 10498 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10499 | // .. PULLUP = 0 | ||
| 10500 | // .. ==> 0XF8000778[12:12] = 0x00000000U | ||
| 10501 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10502 | // .. DisableRcvr = 0 | ||
| 10503 | // .. ==> 0XF8000778[13:13] = 0x00000000U | ||
| 10504 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10505 | // .. | ||
| 10506 | EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U), | ||
| 10507 | // .. TRI_ENABLE = 1 | ||
| 10508 | // .. ==> 0XF800077C[0:0] = 0x00000001U | ||
| 10509 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 10510 | // .. L0_SEL = 0 | ||
| 10511 | // .. ==> 0XF800077C[1:1] = 0x00000000U | ||
| 10512 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10513 | // .. L1_SEL = 1 | ||
| 10514 | // .. ==> 0XF800077C[2:2] = 0x00000001U | ||
| 10515 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 10516 | // .. L2_SEL = 0 | ||
| 10517 | // .. ==> 0XF800077C[4:3] = 0x00000000U | ||
| 10518 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10519 | // .. L3_SEL = 0 | ||
| 10520 | // .. ==> 0XF800077C[7:5] = 0x00000000U | ||
| 10521 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10522 | // .. Speed = 1 | ||
| 10523 | // .. ==> 0XF800077C[8:8] = 0x00000001U | ||
| 10524 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10525 | // .. IO_Type = 1 | ||
| 10526 | // .. ==> 0XF800077C[11:9] = 0x00000001U | ||
| 10527 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10528 | // .. PULLUP = 0 | ||
| 10529 | // .. ==> 0XF800077C[12:12] = 0x00000000U | ||
| 10530 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10531 | // .. DisableRcvr = 0 | ||
| 10532 | // .. ==> 0XF800077C[13:13] = 0x00000000U | ||
| 10533 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10534 | // .. | ||
| 10535 | EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U), | ||
| 10536 | // .. TRI_ENABLE = 0 | ||
| 10537 | // .. ==> 0XF8000780[0:0] = 0x00000000U | ||
| 10538 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10539 | // .. L0_SEL = 0 | ||
| 10540 | // .. ==> 0XF8000780[1:1] = 0x00000000U | ||
| 10541 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10542 | // .. L1_SEL = 1 | ||
| 10543 | // .. ==> 0XF8000780[2:2] = 0x00000001U | ||
| 10544 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 10545 | // .. L2_SEL = 0 | ||
| 10546 | // .. ==> 0XF8000780[4:3] = 0x00000000U | ||
| 10547 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10548 | // .. L3_SEL = 0 | ||
| 10549 | // .. ==> 0XF8000780[7:5] = 0x00000000U | ||
| 10550 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10551 | // .. Speed = 1 | ||
| 10552 | // .. ==> 0XF8000780[8:8] = 0x00000001U | ||
| 10553 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10554 | // .. IO_Type = 1 | ||
| 10555 | // .. ==> 0XF8000780[11:9] = 0x00000001U | ||
| 10556 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10557 | // .. PULLUP = 0 | ||
| 10558 | // .. ==> 0XF8000780[12:12] = 0x00000000U | ||
| 10559 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10560 | // .. DisableRcvr = 0 | ||
| 10561 | // .. ==> 0XF8000780[13:13] = 0x00000000U | ||
| 10562 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10563 | // .. | ||
| 10564 | EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U), | ||
| 10565 | // .. TRI_ENABLE = 0 | ||
| 10566 | // .. ==> 0XF8000784[0:0] = 0x00000000U | ||
| 10567 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10568 | // .. L0_SEL = 0 | ||
| 10569 | // .. ==> 0XF8000784[1:1] = 0x00000000U | ||
| 10570 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10571 | // .. L1_SEL = 1 | ||
| 10572 | // .. ==> 0XF8000784[2:2] = 0x00000001U | ||
| 10573 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 10574 | // .. L2_SEL = 0 | ||
| 10575 | // .. ==> 0XF8000784[4:3] = 0x00000000U | ||
| 10576 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10577 | // .. L3_SEL = 0 | ||
| 10578 | // .. ==> 0XF8000784[7:5] = 0x00000000U | ||
| 10579 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10580 | // .. Speed = 1 | ||
| 10581 | // .. ==> 0XF8000784[8:8] = 0x00000001U | ||
| 10582 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10583 | // .. IO_Type = 1 | ||
| 10584 | // .. ==> 0XF8000784[11:9] = 0x00000001U | ||
| 10585 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10586 | // .. PULLUP = 0 | ||
| 10587 | // .. ==> 0XF8000784[12:12] = 0x00000000U | ||
| 10588 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10589 | // .. DisableRcvr = 0 | ||
| 10590 | // .. ==> 0XF8000784[13:13] = 0x00000000U | ||
| 10591 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10592 | // .. | ||
| 10593 | EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U), | ||
| 10594 | // .. TRI_ENABLE = 0 | ||
| 10595 | // .. ==> 0XF8000788[0:0] = 0x00000000U | ||
| 10596 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10597 | // .. L0_SEL = 0 | ||
| 10598 | // .. ==> 0XF8000788[1:1] = 0x00000000U | ||
| 10599 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10600 | // .. L1_SEL = 1 | ||
| 10601 | // .. ==> 0XF8000788[2:2] = 0x00000001U | ||
| 10602 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 10603 | // .. L2_SEL = 0 | ||
| 10604 | // .. ==> 0XF8000788[4:3] = 0x00000000U | ||
| 10605 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10606 | // .. L3_SEL = 0 | ||
| 10607 | // .. ==> 0XF8000788[7:5] = 0x00000000U | ||
| 10608 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10609 | // .. Speed = 1 | ||
| 10610 | // .. ==> 0XF8000788[8:8] = 0x00000001U | ||
| 10611 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10612 | // .. IO_Type = 1 | ||
| 10613 | // .. ==> 0XF8000788[11:9] = 0x00000001U | ||
| 10614 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10615 | // .. PULLUP = 0 | ||
| 10616 | // .. ==> 0XF8000788[12:12] = 0x00000000U | ||
| 10617 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10618 | // .. DisableRcvr = 0 | ||
| 10619 | // .. ==> 0XF8000788[13:13] = 0x00000000U | ||
| 10620 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10621 | // .. | ||
| 10622 | EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U), | ||
| 10623 | // .. TRI_ENABLE = 0 | ||
| 10624 | // .. ==> 0XF800078C[0:0] = 0x00000000U | ||
| 10625 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10626 | // .. L0_SEL = 0 | ||
| 10627 | // .. ==> 0XF800078C[1:1] = 0x00000000U | ||
| 10628 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10629 | // .. L1_SEL = 1 | ||
| 10630 | // .. ==> 0XF800078C[2:2] = 0x00000001U | ||
| 10631 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 10632 | // .. L2_SEL = 0 | ||
| 10633 | // .. ==> 0XF800078C[4:3] = 0x00000000U | ||
| 10634 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10635 | // .. L3_SEL = 0 | ||
| 10636 | // .. ==> 0XF800078C[7:5] = 0x00000000U | ||
| 10637 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10638 | // .. Speed = 1 | ||
| 10639 | // .. ==> 0XF800078C[8:8] = 0x00000001U | ||
| 10640 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10641 | // .. IO_Type = 1 | ||
| 10642 | // .. ==> 0XF800078C[11:9] = 0x00000001U | ||
| 10643 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10644 | // .. PULLUP = 0 | ||
| 10645 | // .. ==> 0XF800078C[12:12] = 0x00000000U | ||
| 10646 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10647 | // .. DisableRcvr = 0 | ||
| 10648 | // .. ==> 0XF800078C[13:13] = 0x00000000U | ||
| 10649 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10650 | // .. | ||
| 10651 | EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U), | ||
| 10652 | // .. TRI_ENABLE = 1 | ||
| 10653 | // .. ==> 0XF8000790[0:0] = 0x00000001U | ||
| 10654 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 10655 | // .. L0_SEL = 0 | ||
| 10656 | // .. ==> 0XF8000790[1:1] = 0x00000000U | ||
| 10657 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10658 | // .. L1_SEL = 1 | ||
| 10659 | // .. ==> 0XF8000790[2:2] = 0x00000001U | ||
| 10660 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 10661 | // .. L2_SEL = 0 | ||
| 10662 | // .. ==> 0XF8000790[4:3] = 0x00000000U | ||
| 10663 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10664 | // .. L3_SEL = 0 | ||
| 10665 | // .. ==> 0XF8000790[7:5] = 0x00000000U | ||
| 10666 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10667 | // .. Speed = 1 | ||
| 10668 | // .. ==> 0XF8000790[8:8] = 0x00000001U | ||
| 10669 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10670 | // .. IO_Type = 1 | ||
| 10671 | // .. ==> 0XF8000790[11:9] = 0x00000001U | ||
| 10672 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10673 | // .. PULLUP = 0 | ||
| 10674 | // .. ==> 0XF8000790[12:12] = 0x00000000U | ||
| 10675 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10676 | // .. DisableRcvr = 0 | ||
| 10677 | // .. ==> 0XF8000790[13:13] = 0x00000000U | ||
| 10678 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10679 | // .. | ||
| 10680 | EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U), | ||
| 10681 | // .. TRI_ENABLE = 0 | ||
| 10682 | // .. ==> 0XF8000794[0:0] = 0x00000000U | ||
| 10683 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10684 | // .. L0_SEL = 0 | ||
| 10685 | // .. ==> 0XF8000794[1:1] = 0x00000000U | ||
| 10686 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10687 | // .. L1_SEL = 1 | ||
| 10688 | // .. ==> 0XF8000794[2:2] = 0x00000001U | ||
| 10689 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 10690 | // .. L2_SEL = 0 | ||
| 10691 | // .. ==> 0XF8000794[4:3] = 0x00000000U | ||
| 10692 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10693 | // .. L3_SEL = 0 | ||
| 10694 | // .. ==> 0XF8000794[7:5] = 0x00000000U | ||
| 10695 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10696 | // .. Speed = 1 | ||
| 10697 | // .. ==> 0XF8000794[8:8] = 0x00000001U | ||
| 10698 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10699 | // .. IO_Type = 1 | ||
| 10700 | // .. ==> 0XF8000794[11:9] = 0x00000001U | ||
| 10701 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10702 | // .. PULLUP = 0 | ||
| 10703 | // .. ==> 0XF8000794[12:12] = 0x00000000U | ||
| 10704 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10705 | // .. DisableRcvr = 0 | ||
| 10706 | // .. ==> 0XF8000794[13:13] = 0x00000000U | ||
| 10707 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10708 | // .. | ||
| 10709 | EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U), | ||
| 10710 | // .. TRI_ENABLE = 0 | ||
| 10711 | // .. ==> 0XF8000798[0:0] = 0x00000000U | ||
| 10712 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10713 | // .. L0_SEL = 0 | ||
| 10714 | // .. ==> 0XF8000798[1:1] = 0x00000000U | ||
| 10715 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10716 | // .. L1_SEL = 1 | ||
| 10717 | // .. ==> 0XF8000798[2:2] = 0x00000001U | ||
| 10718 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 10719 | // .. L2_SEL = 0 | ||
| 10720 | // .. ==> 0XF8000798[4:3] = 0x00000000U | ||
| 10721 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10722 | // .. L3_SEL = 0 | ||
| 10723 | // .. ==> 0XF8000798[7:5] = 0x00000000U | ||
| 10724 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10725 | // .. Speed = 1 | ||
| 10726 | // .. ==> 0XF8000798[8:8] = 0x00000001U | ||
| 10727 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10728 | // .. IO_Type = 1 | ||
| 10729 | // .. ==> 0XF8000798[11:9] = 0x00000001U | ||
| 10730 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10731 | // .. PULLUP = 0 | ||
| 10732 | // .. ==> 0XF8000798[12:12] = 0x00000000U | ||
| 10733 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10734 | // .. DisableRcvr = 0 | ||
| 10735 | // .. ==> 0XF8000798[13:13] = 0x00000000U | ||
| 10736 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10737 | // .. | ||
| 10738 | EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U), | ||
| 10739 | // .. TRI_ENABLE = 0 | ||
| 10740 | // .. ==> 0XF800079C[0:0] = 0x00000000U | ||
| 10741 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10742 | // .. L0_SEL = 0 | ||
| 10743 | // .. ==> 0XF800079C[1:1] = 0x00000000U | ||
| 10744 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10745 | // .. L1_SEL = 1 | ||
| 10746 | // .. ==> 0XF800079C[2:2] = 0x00000001U | ||
| 10747 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 10748 | // .. L2_SEL = 0 | ||
| 10749 | // .. ==> 0XF800079C[4:3] = 0x00000000U | ||
| 10750 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10751 | // .. L3_SEL = 0 | ||
| 10752 | // .. ==> 0XF800079C[7:5] = 0x00000000U | ||
| 10753 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
| 10754 | // .. Speed = 1 | ||
| 10755 | // .. ==> 0XF800079C[8:8] = 0x00000001U | ||
| 10756 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10757 | // .. IO_Type = 1 | ||
| 10758 | // .. ==> 0XF800079C[11:9] = 0x00000001U | ||
| 10759 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10760 | // .. PULLUP = 0 | ||
| 10761 | // .. ==> 0XF800079C[12:12] = 0x00000000U | ||
| 10762 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10763 | // .. DisableRcvr = 0 | ||
| 10764 | // .. ==> 0XF800079C[13:13] = 0x00000000U | ||
| 10765 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10766 | // .. | ||
| 10767 | EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U), | ||
| 10768 | // .. TRI_ENABLE = 0 | ||
| 10769 | // .. ==> 0XF80007A0[0:0] = 0x00000000U | ||
| 10770 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10771 | // .. L0_SEL = 0 | ||
| 10772 | // .. ==> 0XF80007A0[1:1] = 0x00000000U | ||
| 10773 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10774 | // .. L1_SEL = 0 | ||
| 10775 | // .. ==> 0XF80007A0[2:2] = 0x00000000U | ||
| 10776 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10777 | // .. L2_SEL = 0 | ||
| 10778 | // .. ==> 0XF80007A0[4:3] = 0x00000000U | ||
| 10779 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10780 | // .. L3_SEL = 4 | ||
| 10781 | // .. ==> 0XF80007A0[7:5] = 0x00000004U | ||
| 10782 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 10783 | // .. Speed = 1 | ||
| 10784 | // .. ==> 0XF80007A0[8:8] = 0x00000001U | ||
| 10785 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10786 | // .. IO_Type = 1 | ||
| 10787 | // .. ==> 0XF80007A0[11:9] = 0x00000001U | ||
| 10788 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10789 | // .. PULLUP = 0 | ||
| 10790 | // .. ==> 0XF80007A0[12:12] = 0x00000000U | ||
| 10791 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10792 | // .. DisableRcvr = 0 | ||
| 10793 | // .. ==> 0XF80007A0[13:13] = 0x00000000U | ||
| 10794 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10795 | // .. | ||
| 10796 | EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U), | ||
| 10797 | // .. TRI_ENABLE = 0 | ||
| 10798 | // .. ==> 0XF80007A4[0:0] = 0x00000000U | ||
| 10799 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10800 | // .. L0_SEL = 0 | ||
| 10801 | // .. ==> 0XF80007A4[1:1] = 0x00000000U | ||
| 10802 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10803 | // .. L1_SEL = 0 | ||
| 10804 | // .. ==> 0XF80007A4[2:2] = 0x00000000U | ||
| 10805 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10806 | // .. L2_SEL = 0 | ||
| 10807 | // .. ==> 0XF80007A4[4:3] = 0x00000000U | ||
| 10808 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10809 | // .. L3_SEL = 4 | ||
| 10810 | // .. ==> 0XF80007A4[7:5] = 0x00000004U | ||
| 10811 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 10812 | // .. Speed = 1 | ||
| 10813 | // .. ==> 0XF80007A4[8:8] = 0x00000001U | ||
| 10814 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10815 | // .. IO_Type = 1 | ||
| 10816 | // .. ==> 0XF80007A4[11:9] = 0x00000001U | ||
| 10817 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10818 | // .. PULLUP = 0 | ||
| 10819 | // .. ==> 0XF80007A4[12:12] = 0x00000000U | ||
| 10820 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10821 | // .. DisableRcvr = 0 | ||
| 10822 | // .. ==> 0XF80007A4[13:13] = 0x00000000U | ||
| 10823 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10824 | // .. | ||
| 10825 | EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U), | ||
| 10826 | // .. TRI_ENABLE = 0 | ||
| 10827 | // .. ==> 0XF80007A8[0:0] = 0x00000000U | ||
| 10828 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10829 | // .. L0_SEL = 0 | ||
| 10830 | // .. ==> 0XF80007A8[1:1] = 0x00000000U | ||
| 10831 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10832 | // .. L1_SEL = 0 | ||
| 10833 | // .. ==> 0XF80007A8[2:2] = 0x00000000U | ||
| 10834 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10835 | // .. L2_SEL = 0 | ||
| 10836 | // .. ==> 0XF80007A8[4:3] = 0x00000000U | ||
| 10837 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10838 | // .. L3_SEL = 4 | ||
| 10839 | // .. ==> 0XF80007A8[7:5] = 0x00000004U | ||
| 10840 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 10841 | // .. Speed = 1 | ||
| 10842 | // .. ==> 0XF80007A8[8:8] = 0x00000001U | ||
| 10843 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10844 | // .. IO_Type = 1 | ||
| 10845 | // .. ==> 0XF80007A8[11:9] = 0x00000001U | ||
| 10846 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10847 | // .. PULLUP = 0 | ||
| 10848 | // .. ==> 0XF80007A8[12:12] = 0x00000000U | ||
| 10849 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10850 | // .. DisableRcvr = 0 | ||
| 10851 | // .. ==> 0XF80007A8[13:13] = 0x00000000U | ||
| 10852 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10853 | // .. | ||
| 10854 | EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U), | ||
| 10855 | // .. TRI_ENABLE = 0 | ||
| 10856 | // .. ==> 0XF80007AC[0:0] = 0x00000000U | ||
| 10857 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10858 | // .. L0_SEL = 0 | ||
| 10859 | // .. ==> 0XF80007AC[1:1] = 0x00000000U | ||
| 10860 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10861 | // .. L1_SEL = 0 | ||
| 10862 | // .. ==> 0XF80007AC[2:2] = 0x00000000U | ||
| 10863 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10864 | // .. L2_SEL = 0 | ||
| 10865 | // .. ==> 0XF80007AC[4:3] = 0x00000000U | ||
| 10866 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10867 | // .. L3_SEL = 4 | ||
| 10868 | // .. ==> 0XF80007AC[7:5] = 0x00000004U | ||
| 10869 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 10870 | // .. Speed = 1 | ||
| 10871 | // .. ==> 0XF80007AC[8:8] = 0x00000001U | ||
| 10872 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10873 | // .. IO_Type = 1 | ||
| 10874 | // .. ==> 0XF80007AC[11:9] = 0x00000001U | ||
| 10875 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10876 | // .. PULLUP = 0 | ||
| 10877 | // .. ==> 0XF80007AC[12:12] = 0x00000000U | ||
| 10878 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10879 | // .. DisableRcvr = 0 | ||
| 10880 | // .. ==> 0XF80007AC[13:13] = 0x00000000U | ||
| 10881 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10882 | // .. | ||
| 10883 | EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U), | ||
| 10884 | // .. TRI_ENABLE = 0 | ||
| 10885 | // .. ==> 0XF80007B0[0:0] = 0x00000000U | ||
| 10886 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10887 | // .. L0_SEL = 0 | ||
| 10888 | // .. ==> 0XF80007B0[1:1] = 0x00000000U | ||
| 10889 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10890 | // .. L1_SEL = 0 | ||
| 10891 | // .. ==> 0XF80007B0[2:2] = 0x00000000U | ||
| 10892 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10893 | // .. L2_SEL = 0 | ||
| 10894 | // .. ==> 0XF80007B0[4:3] = 0x00000000U | ||
| 10895 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10896 | // .. L3_SEL = 4 | ||
| 10897 | // .. ==> 0XF80007B0[7:5] = 0x00000004U | ||
| 10898 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 10899 | // .. Speed = 1 | ||
| 10900 | // .. ==> 0XF80007B0[8:8] = 0x00000001U | ||
| 10901 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10902 | // .. IO_Type = 1 | ||
| 10903 | // .. ==> 0XF80007B0[11:9] = 0x00000001U | ||
| 10904 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10905 | // .. PULLUP = 0 | ||
| 10906 | // .. ==> 0XF80007B0[12:12] = 0x00000000U | ||
| 10907 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10908 | // .. DisableRcvr = 0 | ||
| 10909 | // .. ==> 0XF80007B0[13:13] = 0x00000000U | ||
| 10910 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10911 | // .. | ||
| 10912 | EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U), | ||
| 10913 | // .. TRI_ENABLE = 0 | ||
| 10914 | // .. ==> 0XF80007B4[0:0] = 0x00000000U | ||
| 10915 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10916 | // .. L0_SEL = 0 | ||
| 10917 | // .. ==> 0XF80007B4[1:1] = 0x00000000U | ||
| 10918 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10919 | // .. L1_SEL = 0 | ||
| 10920 | // .. ==> 0XF80007B4[2:2] = 0x00000000U | ||
| 10921 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10922 | // .. L2_SEL = 0 | ||
| 10923 | // .. ==> 0XF80007B4[4:3] = 0x00000000U | ||
| 10924 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10925 | // .. L3_SEL = 4 | ||
| 10926 | // .. ==> 0XF80007B4[7:5] = 0x00000004U | ||
| 10927 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 10928 | // .. Speed = 1 | ||
| 10929 | // .. ==> 0XF80007B4[8:8] = 0x00000001U | ||
| 10930 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 10931 | // .. IO_Type = 1 | ||
| 10932 | // .. ==> 0XF80007B4[11:9] = 0x00000001U | ||
| 10933 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10934 | // .. PULLUP = 0 | ||
| 10935 | // .. ==> 0XF80007B4[12:12] = 0x00000000U | ||
| 10936 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10937 | // .. DisableRcvr = 0 | ||
| 10938 | // .. ==> 0XF80007B4[13:13] = 0x00000000U | ||
| 10939 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10940 | // .. | ||
| 10941 | EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U), | ||
| 10942 | // .. TRI_ENABLE = 1 | ||
| 10943 | // .. ==> 0XF80007BC[0:0] = 0x00000001U | ||
| 10944 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 10945 | // .. Speed = 0 | ||
| 10946 | // .. ==> 0XF80007BC[8:8] = 0x00000000U | ||
| 10947 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 10948 | // .. IO_Type = 1 | ||
| 10949 | // .. ==> 0XF80007BC[11:9] = 0x00000001U | ||
| 10950 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10951 | // .. PULLUP = 0 | ||
| 10952 | // .. ==> 0XF80007BC[12:12] = 0x00000000U | ||
| 10953 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10954 | // .. DisableRcvr = 0 | ||
| 10955 | // .. ==> 0XF80007BC[13:13] = 0x00000000U | ||
| 10956 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10957 | // .. | ||
| 10958 | EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U), | ||
| 10959 | // .. TRI_ENABLE = 0 | ||
| 10960 | // .. ==> 0XF80007C0[0:0] = 0x00000000U | ||
| 10961 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 10962 | // .. L0_SEL = 0 | ||
| 10963 | // .. ==> 0XF80007C0[1:1] = 0x00000000U | ||
| 10964 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10965 | // .. L1_SEL = 0 | ||
| 10966 | // .. ==> 0XF80007C0[2:2] = 0x00000000U | ||
| 10967 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10968 | // .. L2_SEL = 0 | ||
| 10969 | // .. ==> 0XF80007C0[4:3] = 0x00000000U | ||
| 10970 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 10971 | // .. L3_SEL = 7 | ||
| 10972 | // .. ==> 0XF80007C0[7:5] = 0x00000007U | ||
| 10973 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | ||
| 10974 | // .. Speed = 0 | ||
| 10975 | // .. ==> 0XF80007C0[8:8] = 0x00000000U | ||
| 10976 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 10977 | // .. IO_Type = 1 | ||
| 10978 | // .. ==> 0XF80007C0[11:9] = 0x00000001U | ||
| 10979 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 10980 | // .. PULLUP = 0 | ||
| 10981 | // .. ==> 0XF80007C0[12:12] = 0x00000000U | ||
| 10982 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 10983 | // .. DisableRcvr = 0 | ||
| 10984 | // .. ==> 0XF80007C0[13:13] = 0x00000000U | ||
| 10985 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 10986 | // .. | ||
| 10987 | EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), | ||
| 10988 | // .. TRI_ENABLE = 1 | ||
| 10989 | // .. ==> 0XF80007C4[0:0] = 0x00000001U | ||
| 10990 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 10991 | // .. L0_SEL = 0 | ||
| 10992 | // .. ==> 0XF80007C4[1:1] = 0x00000000U | ||
| 10993 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 10994 | // .. L1_SEL = 0 | ||
| 10995 | // .. ==> 0XF80007C4[2:2] = 0x00000000U | ||
| 10996 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 10997 | // .. L2_SEL = 0 | ||
| 10998 | // .. ==> 0XF80007C4[4:3] = 0x00000000U | ||
| 10999 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 11000 | // .. L3_SEL = 7 | ||
| 11001 | // .. ==> 0XF80007C4[7:5] = 0x00000007U | ||
| 11002 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | ||
| 11003 | // .. Speed = 0 | ||
| 11004 | // .. ==> 0XF80007C4[8:8] = 0x00000000U | ||
| 11005 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 11006 | // .. IO_Type = 1 | ||
| 11007 | // .. ==> 0XF80007C4[11:9] = 0x00000001U | ||
| 11008 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 11009 | // .. PULLUP = 0 | ||
| 11010 | // .. ==> 0XF80007C4[12:12] = 0x00000000U | ||
| 11011 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 11012 | // .. DisableRcvr = 0 | ||
| 11013 | // .. ==> 0XF80007C4[13:13] = 0x00000000U | ||
| 11014 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 11015 | // .. | ||
| 11016 | EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), | ||
| 11017 | // .. TRI_ENABLE = 0 | ||
| 11018 | // .. ==> 0XF80007D0[0:0] = 0x00000000U | ||
| 11019 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 11020 | // .. L0_SEL = 0 | ||
| 11021 | // .. ==> 0XF80007D0[1:1] = 0x00000000U | ||
| 11022 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 11023 | // .. L1_SEL = 0 | ||
| 11024 | // .. ==> 0XF80007D0[2:2] = 0x00000000U | ||
| 11025 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 11026 | // .. L2_SEL = 0 | ||
| 11027 | // .. ==> 0XF80007D0[4:3] = 0x00000000U | ||
| 11028 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 11029 | // .. L3_SEL = 4 | ||
| 11030 | // .. ==> 0XF80007D0[7:5] = 0x00000004U | ||
| 11031 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 11032 | // .. Speed = 0 | ||
| 11033 | // .. ==> 0XF80007D0[8:8] = 0x00000000U | ||
| 11034 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 11035 | // .. IO_Type = 1 | ||
| 11036 | // .. ==> 0XF80007D0[11:9] = 0x00000001U | ||
| 11037 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 11038 | // .. PULLUP = 0 | ||
| 11039 | // .. ==> 0XF80007D0[12:12] = 0x00000000U | ||
| 11040 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 11041 | // .. DisableRcvr = 0 | ||
| 11042 | // .. ==> 0XF80007D0[13:13] = 0x00000000U | ||
| 11043 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 11044 | // .. | ||
| 11045 | EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), | ||
| 11046 | // .. TRI_ENABLE = 0 | ||
| 11047 | // .. ==> 0XF80007D4[0:0] = 0x00000000U | ||
| 11048 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 11049 | // .. L0_SEL = 0 | ||
| 11050 | // .. ==> 0XF80007D4[1:1] = 0x00000000U | ||
| 11051 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 11052 | // .. L1_SEL = 0 | ||
| 11053 | // .. ==> 0XF80007D4[2:2] = 0x00000000U | ||
| 11054 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 11055 | // .. L2_SEL = 0 | ||
| 11056 | // .. ==> 0XF80007D4[4:3] = 0x00000000U | ||
| 11057 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
| 11058 | // .. L3_SEL = 4 | ||
| 11059 | // .. ==> 0XF80007D4[7:5] = 0x00000004U | ||
| 11060 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
| 11061 | // .. Speed = 0 | ||
| 11062 | // .. ==> 0XF80007D4[8:8] = 0x00000000U | ||
| 11063 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 11064 | // .. IO_Type = 1 | ||
| 11065 | // .. ==> 0XF80007D4[11:9] = 0x00000001U | ||
| 11066 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
| 11067 | // .. PULLUP = 0 | ||
| 11068 | // .. ==> 0XF80007D4[12:12] = 0x00000000U | ||
| 11069 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 11070 | // .. DisableRcvr = 0 | ||
| 11071 | // .. ==> 0XF80007D4[13:13] = 0x00000000U | ||
| 11072 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 11073 | // .. | ||
| 11074 | EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), | ||
| 11075 | // .. SDIO0_WP_SEL = 55 | ||
| 11076 | // .. ==> 0XF8000830[5:0] = 0x00000037U | ||
| 11077 | // .. ==> MASK : 0x0000003FU VAL : 0x00000037U | ||
| 11078 | // .. SDIO0_CD_SEL = 47 | ||
| 11079 | // .. ==> 0XF8000830[21:16] = 0x0000002FU | ||
| 11080 | // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U | ||
| 11081 | // .. | ||
| 11082 | EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U), | ||
| 11083 | // .. FINISH: MIO PROGRAMMING | ||
| 11084 | // .. START: LOCK IT BACK | ||
| 11085 | // .. LOCK_KEY = 0X767B | ||
| 11086 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
| 11087 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
| 11088 | // .. | ||
| 11089 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
| 11090 | // .. FINISH: LOCK IT BACK | ||
| 11091 | // FINISH: top | ||
| 11092 | // | ||
| 11093 | EMIT_EXIT(), | ||
| 11094 | |||
| 11095 | // | ||
| 11096 | }; | ||
| 11097 | |||
| 11098 | unsigned long ps7_peripherals_init_data_1_0[] = { | ||
| 11099 | // START: top | ||
| 11100 | // .. START: SLCR SETTINGS | ||
| 11101 | // .. UNLOCK_KEY = 0XDF0D | ||
| 11102 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
| 11103 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
| 11104 | // .. | ||
| 11105 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
| 11106 | // .. FINISH: SLCR SETTINGS | ||
| 11107 | // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS | ||
| 11108 | // .. IBUF_DISABLE_MODE = 0x1 | ||
| 11109 | // .. ==> 0XF8000B48[7:7] = 0x00000001U | ||
| 11110 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
| 11111 | // .. TERM_DISABLE_MODE = 0x1 | ||
| 11112 | // .. ==> 0XF8000B48[8:8] = 0x00000001U | ||
| 11113 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 11114 | // .. | ||
| 11115 | EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), | ||
| 11116 | // .. IBUF_DISABLE_MODE = 0x1 | ||
| 11117 | // .. ==> 0XF8000B4C[7:7] = 0x00000001U | ||
| 11118 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
| 11119 | // .. TERM_DISABLE_MODE = 0x1 | ||
| 11120 | // .. ==> 0XF8000B4C[8:8] = 0x00000001U | ||
| 11121 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 11122 | // .. | ||
| 11123 | EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), | ||
| 11124 | // .. IBUF_DISABLE_MODE = 0x1 | ||
| 11125 | // .. ==> 0XF8000B50[7:7] = 0x00000001U | ||
| 11126 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
| 11127 | // .. TERM_DISABLE_MODE = 0x1 | ||
| 11128 | // .. ==> 0XF8000B50[8:8] = 0x00000001U | ||
| 11129 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 11130 | // .. | ||
| 11131 | EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), | ||
| 11132 | // .. IBUF_DISABLE_MODE = 0x1 | ||
| 11133 | // .. ==> 0XF8000B54[7:7] = 0x00000001U | ||
| 11134 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
| 11135 | // .. TERM_DISABLE_MODE = 0x1 | ||
| 11136 | // .. ==> 0XF8000B54[8:8] = 0x00000001U | ||
| 11137 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
| 11138 | // .. | ||
| 11139 | EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), | ||
| 11140 | // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS | ||
| 11141 | // .. START: LOCK IT BACK | ||
| 11142 | // .. LOCK_KEY = 0X767B | ||
| 11143 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
| 11144 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
| 11145 | // .. | ||
| 11146 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
| 11147 | // .. FINISH: LOCK IT BACK | ||
| 11148 | // .. START: SRAM/NOR SET OPMODE | ||
| 11149 | // .. FINISH: SRAM/NOR SET OPMODE | ||
| 11150 | // .. START: UART REGISTERS | ||
| 11151 | // .. BDIV = 0x6 | ||
| 11152 | // .. ==> 0XE0001034[7:0] = 0x00000006U | ||
| 11153 | // .. ==> MASK : 0x000000FFU VAL : 0x00000006U | ||
| 11154 | // .. | ||
| 11155 | EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), | ||
| 11156 | // .. CD = 0x3e | ||
| 11157 | // .. ==> 0XE0001018[15:0] = 0x0000003EU | ||
| 11158 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU | ||
| 11159 | // .. | ||
| 11160 | EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), | ||
| 11161 | // .. STPBRK = 0x0 | ||
| 11162 | // .. ==> 0XE0001000[8:8] = 0x00000000U | ||
| 11163 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 11164 | // .. STTBRK = 0x0 | ||
| 11165 | // .. ==> 0XE0001000[7:7] = 0x00000000U | ||
| 11166 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
| 11167 | // .. RSTTO = 0x0 | ||
| 11168 | // .. ==> 0XE0001000[6:6] = 0x00000000U | ||
| 11169 | // .. ==> MASK : 0x00000040U VAL : 0x00000000U | ||
| 11170 | // .. TXDIS = 0x0 | ||
| 11171 | // .. ==> 0XE0001000[5:5] = 0x00000000U | ||
| 11172 | // .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
| 11173 | // .. TXEN = 0x1 | ||
| 11174 | // .. ==> 0XE0001000[4:4] = 0x00000001U | ||
| 11175 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
| 11176 | // .. RXDIS = 0x0 | ||
| 11177 | // .. ==> 0XE0001000[3:3] = 0x00000000U | ||
| 11178 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 11179 | // .. RXEN = 0x1 | ||
| 11180 | // .. ==> 0XE0001000[2:2] = 0x00000001U | ||
| 11181 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
| 11182 | // .. TXRES = 0x1 | ||
| 11183 | // .. ==> 0XE0001000[1:1] = 0x00000001U | ||
| 11184 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
| 11185 | // .. RXRES = 0x1 | ||
| 11186 | // .. ==> 0XE0001000[0:0] = 0x00000001U | ||
| 11187 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
| 11188 | // .. | ||
| 11189 | EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), | ||
| 11190 | // .. IRMODE = 0x0 | ||
| 11191 | // .. ==> 0XE0001004[11:11] = 0x00000000U | ||
| 11192 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 11193 | // .. UCLKEN = 0x0 | ||
| 11194 | // .. ==> 0XE0001004[10:10] = 0x00000000U | ||
| 11195 | // .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 11196 | // .. CHMODE = 0x0 | ||
| 11197 | // .. ==> 0XE0001004[9:8] = 0x00000000U | ||
| 11198 | // .. ==> MASK : 0x00000300U VAL : 0x00000000U | ||
| 11199 | // .. NBSTOP = 0x0 | ||
| 11200 | // .. ==> 0XE0001004[7:6] = 0x00000000U | ||
| 11201 | // .. ==> MASK : 0x000000C0U VAL : 0x00000000U | ||
| 11202 | // .. PAR = 0x4 | ||
| 11203 | // .. ==> 0XE0001004[5:3] = 0x00000004U | ||
| 11204 | // .. ==> MASK : 0x00000038U VAL : 0x00000020U | ||
| 11205 | // .. CHRL = 0x0 | ||
| 11206 | // .. ==> 0XE0001004[2:1] = 0x00000000U | ||
| 11207 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
| 11208 | // .. CLKS = 0x0 | ||
| 11209 | // .. ==> 0XE0001004[0:0] = 0x00000000U | ||
| 11210 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 11211 | // .. | ||
| 11212 | EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), | ||
| 11213 | // .. FINISH: UART REGISTERS | ||
| 11214 | // .. START: TPIU WIDTH IN CASE OF EMIO | ||
| 11215 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
| 11216 | // .. .. a = 0XC5ACCE55 | ||
| 11217 | // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U | ||
| 11218 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
| 11219 | // .. .. | ||
| 11220 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
| 11221 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
| 11222 | // .. .. START: TRACE CURRENT PORT SIZE | ||
| 11223 | // .. .. a = 2 | ||
| 11224 | // .. .. ==> 0XF8803004[31:0] = 0x00000002U | ||
| 11225 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U | ||
| 11226 | // .. .. | ||
| 11227 | EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), | ||
| 11228 | // .. .. FINISH: TRACE CURRENT PORT SIZE | ||
| 11229 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
| 11230 | // .. .. a = 0X0 | ||
| 11231 | // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U | ||
| 11232 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
| 11233 | // .. .. | ||
| 11234 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), | ||
| 11235 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
| 11236 | // .. FINISH: TPIU WIDTH IN CASE OF EMIO | ||
| 11237 | // .. START: QSPI REGISTERS | ||
| 11238 | // .. Holdb_dr = 1 | ||
| 11239 | // .. ==> 0XE000D000[19:19] = 0x00000001U | ||
| 11240 | // .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
| 11241 | // .. | ||
| 11242 | EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), | ||
| 11243 | // .. FINISH: QSPI REGISTERS | ||
| 11244 | // .. START: PL POWER ON RESET REGISTERS | ||
| 11245 | // .. PCFG_POR_CNT_4K = 0 | ||
| 11246 | // .. ==> 0XF8007000[29:29] = 0x00000000U | ||
| 11247 | // .. ==> MASK : 0x20000000U VAL : 0x00000000U | ||
| 11248 | // .. | ||
| 11249 | EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), | ||
| 11250 | // .. FINISH: PL POWER ON RESET REGISTERS | ||
| 11251 | // .. START: SMC TIMING CALCULATION REGISTER UPDATE | ||
| 11252 | // .. .. START: NAND SET CYCLE | ||
| 11253 | // .. .. FINISH: NAND SET CYCLE | ||
| 11254 | // .. .. START: OPMODE | ||
| 11255 | // .. .. FINISH: OPMODE | ||
| 11256 | // .. .. START: DIRECT COMMAND | ||
| 11257 | // .. .. FINISH: DIRECT COMMAND | ||
| 11258 | // .. .. START: SRAM/NOR CS0 SET CYCLE | ||
| 11259 | // .. .. FINISH: SRAM/NOR CS0 SET CYCLE | ||
| 11260 | // .. .. START: DIRECT COMMAND | ||
| 11261 | // .. .. FINISH: DIRECT COMMAND | ||
| 11262 | // .. .. START: NOR CS0 BASE ADDRESS | ||
| 11263 | // .. .. FINISH: NOR CS0 BASE ADDRESS | ||
| 11264 | // .. .. START: SRAM/NOR CS1 SET CYCLE | ||
| 11265 | // .. .. FINISH: SRAM/NOR CS1 SET CYCLE | ||
| 11266 | // .. .. START: DIRECT COMMAND | ||
| 11267 | // .. .. FINISH: DIRECT COMMAND | ||
| 11268 | // .. .. START: NOR CS1 BASE ADDRESS | ||
| 11269 | // .. .. FINISH: NOR CS1 BASE ADDRESS | ||
| 11270 | // .. .. START: USB RESET | ||
| 11271 | // .. .. .. START: USB0 RESET | ||
| 11272 | // .. .. .. .. START: DIR MODE BANK 0 | ||
| 11273 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
| 11274 | // .. .. .. .. START: DIR MODE BANK 1 | ||
| 11275 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
| 11276 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11277 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11278 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11279 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11280 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11281 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11282 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11283 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11284 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
| 11285 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
| 11286 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
| 11287 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
| 11288 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 11289 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 11290 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 11291 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 11292 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 11293 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 11294 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 11295 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 11296 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 11297 | // .. .. .. .. | ||
| 11298 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 11299 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 11300 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11301 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11302 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11303 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11304 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11305 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11306 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11307 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11308 | // .. .. .. FINISH: USB0 RESET | ||
| 11309 | // .. .. .. START: USB1 RESET | ||
| 11310 | // .. .. .. .. START: DIR MODE BANK 0 | ||
| 11311 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
| 11312 | // .. .. .. .. START: DIR MODE BANK 1 | ||
| 11313 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
| 11314 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11315 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11316 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11317 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11318 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11319 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11320 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11321 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11322 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
| 11323 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
| 11324 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
| 11325 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
| 11326 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 11327 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 11328 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 11329 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 11330 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 11331 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 11332 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 11333 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 11334 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 11335 | // .. .. .. .. | ||
| 11336 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 11337 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 11338 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11339 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11340 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11341 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11342 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11343 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11344 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11345 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11346 | // .. .. .. FINISH: USB1 RESET | ||
| 11347 | // .. .. FINISH: USB RESET | ||
| 11348 | // .. .. START: ENET RESET | ||
| 11349 | // .. .. .. START: ENET0 RESET | ||
| 11350 | // .. .. .. .. START: DIR MODE BANK 0 | ||
| 11351 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
| 11352 | // .. .. .. .. START: DIR MODE BANK 1 | ||
| 11353 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
| 11354 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11355 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11356 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11357 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11358 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11359 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11360 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11361 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11362 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
| 11363 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
| 11364 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
| 11365 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
| 11366 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 11367 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 11368 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 11369 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 11370 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 11371 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 11372 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 11373 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 11374 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 11375 | // .. .. .. .. | ||
| 11376 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 11377 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 11378 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11379 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11380 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11381 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11382 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11383 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11384 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11385 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11386 | // .. .. .. FINISH: ENET0 RESET | ||
| 11387 | // .. .. .. START: ENET1 RESET | ||
| 11388 | // .. .. .. .. START: DIR MODE BANK 0 | ||
| 11389 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
| 11390 | // .. .. .. .. START: DIR MODE BANK 1 | ||
| 11391 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
| 11392 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11393 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11394 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11395 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11396 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11397 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11398 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11399 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11400 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
| 11401 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
| 11402 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
| 11403 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
| 11404 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 11405 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 11406 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 11407 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 11408 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 11409 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 11410 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 11411 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 11412 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 11413 | // .. .. .. .. | ||
| 11414 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 11415 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 11416 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11417 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11418 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11419 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11420 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11421 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11422 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11423 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11424 | // .. .. .. FINISH: ENET1 RESET | ||
| 11425 | // .. .. FINISH: ENET RESET | ||
| 11426 | // .. .. START: I2C RESET | ||
| 11427 | // .. .. .. START: I2C0 RESET | ||
| 11428 | // .. .. .. .. START: DIR MODE GPIO BANK0 | ||
| 11429 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | ||
| 11430 | // .. .. .. .. START: DIR MODE GPIO BANK1 | ||
| 11431 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | ||
| 11432 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11433 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11434 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11435 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11436 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11437 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11438 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11439 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11440 | // .. .. .. .. START: OUTPUT ENABLE | ||
| 11441 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
| 11442 | // .. .. .. .. START: OUTPUT ENABLE | ||
| 11443 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
| 11444 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 11445 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 11446 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 11447 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 11448 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 11449 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 11450 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 11451 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 11452 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 11453 | // .. .. .. .. | ||
| 11454 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 11455 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 11456 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11457 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11458 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11459 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11460 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11461 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11462 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11463 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11464 | // .. .. .. FINISH: I2C0 RESET | ||
| 11465 | // .. .. .. START: I2C1 RESET | ||
| 11466 | // .. .. .. .. START: DIR MODE GPIO BANK0 | ||
| 11467 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | ||
| 11468 | // .. .. .. .. START: DIR MODE GPIO BANK1 | ||
| 11469 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | ||
| 11470 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11471 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11472 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11473 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11474 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11475 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11476 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11477 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11478 | // .. .. .. .. START: OUTPUT ENABLE | ||
| 11479 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
| 11480 | // .. .. .. .. START: OUTPUT ENABLE | ||
| 11481 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
| 11482 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 11483 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
| 11484 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 11485 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
| 11486 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 11487 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
| 11488 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 11489 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
| 11490 | // .. .. .. .. START: ADD 1 MS DELAY | ||
| 11491 | // .. .. .. .. | ||
| 11492 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
| 11493 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
| 11494 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11495 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11496 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11497 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
| 11498 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11499 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
| 11500 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11501 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
| 11502 | // .. .. .. FINISH: I2C1 RESET | ||
| 11503 | // .. .. FINISH: I2C RESET | ||
| 11504 | // .. .. START: NOR CHIP SELECT | ||
| 11505 | // .. .. .. START: DIR MODE BANK 0 | ||
| 11506 | // .. .. .. FINISH: DIR MODE BANK 0 | ||
| 11507 | // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11508 | // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
| 11509 | // .. .. .. START: OUTPUT ENABLE BANK 0 | ||
| 11510 | // .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
| 11511 | // .. .. FINISH: NOR CHIP SELECT | ||
| 11512 | // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE | ||
| 11513 | // FINISH: top | ||
| 11514 | // | ||
| 11515 | EMIT_EXIT(), | ||
| 11516 | |||
| 11517 | // | ||
| 11518 | }; | ||
| 11519 | |||
| 11520 | unsigned long ps7_post_config_1_0[] = { | ||
| 11521 | // START: top | ||
| 11522 | // .. START: SLCR SETTINGS | ||
| 11523 | // .. UNLOCK_KEY = 0XDF0D | ||
| 11524 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
| 11525 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
| 11526 | // .. | ||
| 11527 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
| 11528 | // .. FINISH: SLCR SETTINGS | ||
| 11529 | // .. START: ENABLING LEVEL SHIFTER | ||
| 11530 | // .. USER_INP_ICT_EN_0 = 3 | ||
| 11531 | // .. ==> 0XF8000900[1:0] = 0x00000003U | ||
| 11532 | // .. ==> MASK : 0x00000003U VAL : 0x00000003U | ||
| 11533 | // .. USER_INP_ICT_EN_1 = 3 | ||
| 11534 | // .. ==> 0XF8000900[3:2] = 0x00000003U | ||
| 11535 | // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU | ||
| 11536 | // .. | ||
| 11537 | EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), | ||
| 11538 | // .. FINISH: ENABLING LEVEL SHIFTER | ||
| 11539 | // .. START: TPIU WIDTH IN CASE OF EMIO | ||
| 11540 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
| 11541 | // .. .. a = 0XC5ACCE55 | ||
| 11542 | // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U | ||
| 11543 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
| 11544 | // .. .. | ||
| 11545 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
| 11546 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
| 11547 | // .. .. START: TRACE CURRENT PORT SIZE | ||
| 11548 | // .. .. a = 2 | ||
| 11549 | // .. .. ==> 0XF8803004[31:0] = 0x00000002U | ||
| 11550 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U | ||
| 11551 | // .. .. | ||
| 11552 | EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), | ||
| 11553 | // .. .. FINISH: TRACE CURRENT PORT SIZE | ||
| 11554 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
| 11555 | // .. .. a = 0X0 | ||
| 11556 | // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U | ||
| 11557 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
| 11558 | // .. .. | ||
| 11559 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), | ||
| 11560 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
| 11561 | // .. FINISH: TPIU WIDTH IN CASE OF EMIO | ||
| 11562 | // .. START: FPGA RESETS TO 0 | ||
| 11563 | // .. reserved_3 = 0 | ||
| 11564 | // .. ==> 0XF8000240[31:25] = 0x00000000U | ||
| 11565 | // .. ==> MASK : 0xFE000000U VAL : 0x00000000U | ||
| 11566 | // .. FPGA_ACP_RST = 0 | ||
| 11567 | // .. ==> 0XF8000240[24:24] = 0x00000000U | ||
| 11568 | // .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
| 11569 | // .. FPGA_AXDS3_RST = 0 | ||
| 11570 | // .. ==> 0XF8000240[23:23] = 0x00000000U | ||
| 11571 | // .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
| 11572 | // .. FPGA_AXDS2_RST = 0 | ||
| 11573 | // .. ==> 0XF8000240[22:22] = 0x00000000U | ||
| 11574 | // .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
| 11575 | // .. FPGA_AXDS1_RST = 0 | ||
| 11576 | // .. ==> 0XF8000240[21:21] = 0x00000000U | ||
| 11577 | // .. ==> MASK : 0x00200000U VAL : 0x00000000U | ||
| 11578 | // .. FPGA_AXDS0_RST = 0 | ||
| 11579 | // .. ==> 0XF8000240[20:20] = 0x00000000U | ||
| 11580 | // .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
| 11581 | // .. reserved_2 = 0 | ||
| 11582 | // .. ==> 0XF8000240[19:18] = 0x00000000U | ||
| 11583 | // .. ==> MASK : 0x000C0000U VAL : 0x00000000U | ||
| 11584 | // .. FSSW1_FPGA_RST = 0 | ||
| 11585 | // .. ==> 0XF8000240[17:17] = 0x00000000U | ||
| 11586 | // .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
| 11587 | // .. FSSW0_FPGA_RST = 0 | ||
| 11588 | // .. ==> 0XF8000240[16:16] = 0x00000000U | ||
| 11589 | // .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
| 11590 | // .. reserved_1 = 0 | ||
| 11591 | // .. ==> 0XF8000240[15:14] = 0x00000000U | ||
| 11592 | // .. ==> MASK : 0x0000C000U VAL : 0x00000000U | ||
| 11593 | // .. FPGA_FMSW1_RST = 0 | ||
| 11594 | // .. ==> 0XF8000240[13:13] = 0x00000000U | ||
| 11595 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
| 11596 | // .. FPGA_FMSW0_RST = 0 | ||
| 11597 | // .. ==> 0XF8000240[12:12] = 0x00000000U | ||
| 11598 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
| 11599 | // .. FPGA_DMA3_RST = 0 | ||
| 11600 | // .. ==> 0XF8000240[11:11] = 0x00000000U | ||
| 11601 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
| 11602 | // .. FPGA_DMA2_RST = 0 | ||
| 11603 | // .. ==> 0XF8000240[10:10] = 0x00000000U | ||
| 11604 | // .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
| 11605 | // .. FPGA_DMA1_RST = 0 | ||
| 11606 | // .. ==> 0XF8000240[9:9] = 0x00000000U | ||
| 11607 | // .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
| 11608 | // .. FPGA_DMA0_RST = 0 | ||
| 11609 | // .. ==> 0XF8000240[8:8] = 0x00000000U | ||
| 11610 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
| 11611 | // .. reserved = 0 | ||
| 11612 | // .. ==> 0XF8000240[7:4] = 0x00000000U | ||
| 11613 | // .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
| 11614 | // .. FPGA3_OUT_RST = 0 | ||
| 11615 | // .. ==> 0XF8000240[3:3] = 0x00000000U | ||
| 11616 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
| 11617 | // .. FPGA2_OUT_RST = 0 | ||
| 11618 | // .. ==> 0XF8000240[2:2] = 0x00000000U | ||
| 11619 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
| 11620 | // .. FPGA1_OUT_RST = 0 | ||
| 11621 | // .. ==> 0XF8000240[1:1] = 0x00000000U | ||
| 11622 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
| 11623 | // .. FPGA0_OUT_RST = 0 | ||
| 11624 | // .. ==> 0XF8000240[0:0] = 0x00000000U | ||
| 11625 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
| 11626 | // .. | ||
| 11627 | EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), | ||
| 11628 | // .. FINISH: FPGA RESETS TO 0 | ||
| 11629 | // .. START: AFI REGISTERS | ||
| 11630 | // .. .. START: AFI0 REGISTERS | ||
| 11631 | // .. .. FINISH: AFI0 REGISTERS | ||
| 11632 | // .. .. START: AFI1 REGISTERS | ||
| 11633 | // .. .. FINISH: AFI1 REGISTERS | ||
| 11634 | // .. .. START: AFI2 REGISTERS | ||
| 11635 | // .. .. FINISH: AFI2 REGISTERS | ||
| 11636 | // .. .. START: AFI3 REGISTERS | ||
| 11637 | // .. .. FINISH: AFI3 REGISTERS | ||
| 11638 | // .. FINISH: AFI REGISTERS | ||
| 11639 | // .. START: LOCK IT BACK | ||
| 11640 | // .. LOCK_KEY = 0X767B | ||
| 11641 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
| 11642 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
| 11643 | // .. | ||
| 11644 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
| 11645 | // .. FINISH: LOCK IT BACK | ||
| 11646 | // FINISH: top | ||
| 11647 | // | ||
| 11648 | EMIT_EXIT(), | ||
| 11649 | |||
| 11650 | // | ||
| 11651 | }; | ||
| 11652 | |||
| 11653 | unsigned long ps7_debug_1_0[] = { | ||
| 11654 | // START: top | ||
| 11655 | // .. START: CROSS TRIGGER CONFIGURATIONS | ||
| 11656 | // .. .. START: UNLOCKING CTI REGISTERS | ||
| 11657 | // .. .. KEY = 0XC5ACCE55 | ||
| 11658 | // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U | ||
| 11659 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
| 11660 | // .. .. | ||
| 11661 | EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
| 11662 | // .. .. KEY = 0XC5ACCE55 | ||
| 11663 | // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U | ||
| 11664 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
| 11665 | // .. .. | ||
| 11666 | EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
| 11667 | // .. .. KEY = 0XC5ACCE55 | ||
| 11668 | // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U | ||
| 11669 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
| 11670 | // .. .. | ||
| 11671 | EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
| 11672 | // .. .. FINISH: UNLOCKING CTI REGISTERS | ||
| 11673 | // .. .. START: ENABLING CTI MODULES AND CHANNELS | ||
| 11674 | // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS | ||
| 11675 | // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS | ||
| 11676 | // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS | ||
| 11677 | // .. FINISH: CROSS TRIGGER CONFIGURATIONS | ||
| 11678 | // FINISH: top | ||
| 11679 | // | ||
| 11680 | EMIT_EXIT(), | ||
| 11681 | |||
| 11682 | // | ||
| 11683 | }; | ||
| 11684 | |||
| 11685 | |||
| 11686 | #include "xil_io.h" | ||
| 11687 | #define PS7_MASK_POLL_TIME 100000000 | ||
| 11688 | |||
| 11689 | char* | ||
| 11690 | getPS7MessageInfo(unsigned key) { | ||
| 11691 | |||
| 11692 | char* err_msg = ""; | ||
| 11693 | switch (key) { | ||
| 11694 | case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; | ||
| 11695 | case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; | ||
| 11696 | case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; | ||
| 11697 | case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; | ||
| 11698 | case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; | ||
| 11699 | case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; | ||
| 11700 | default: err_msg = "Undefined error status"; break; | ||
| 11701 | } | ||
| 11702 | |||
| 11703 | return err_msg; | ||
| 11704 | } | ||
| 11705 | |||
| 11706 | unsigned long | ||
| 11707 | ps7GetSiliconVersion () { | ||
| 11708 | // Read PS version from MCTRL register [31:28] | ||
| 11709 | unsigned long mask = 0xF0000000; | ||
| 11710 | unsigned long *addr = (unsigned long*) 0XF8007080; | ||
| 11711 | unsigned long ps_version = (*addr & mask) >> 28; | ||
| 11712 | return ps_version; | ||
| 11713 | } | ||
| 11714 | |||
| 11715 | void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { | ||
| 11716 | unsigned long *addr = (unsigned long*) add; | ||
| 11717 | *addr = ( val & mask ) | ( *addr & ~mask); | ||
| 11718 | //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); | ||
| 11719 | } | ||
| 11720 | |||
| 11721 | |||
| 11722 | int mask_poll(unsigned long add , unsigned long mask ) { | ||
| 11723 | volatile unsigned long *addr = (volatile unsigned long*) add; | ||
| 11724 | int i = 0; | ||
| 11725 | while (!(*addr & mask)) { | ||
| 11726 | if (i == PS7_MASK_POLL_TIME) { | ||
| 11727 | return -1; | ||
| 11728 | } | ||
| 11729 | i++; | ||
| 11730 | } | ||
| 11731 | return 1; | ||
| 11732 | //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); | ||
| 11733 | } | ||
| 11734 | |||
| 11735 | unsigned long mask_read(unsigned long add , unsigned long mask ) { | ||
| 11736 | unsigned long *addr = (unsigned long*) add; | ||
| 11737 | unsigned long val = (*addr & mask); | ||
| 11738 | //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); | ||
| 11739 | return val; | ||
| 11740 | } | ||
| 11741 | |||
| 11742 | |||
| 11743 | |||
| 11744 | int | ||
| 11745 | ps7_config(unsigned long * ps7_config_init) | ||
| 11746 | { | ||
| 11747 | unsigned long *ptr = ps7_config_init; | ||
| 11748 | |||
| 11749 | unsigned long opcode; // current instruction .. | ||
| 11750 | unsigned long args[16]; // no opcode has so many args ... | ||
| 11751 | int numargs; // number of arguments of this instruction | ||
| 11752 | int j; // general purpose index | ||
| 11753 | |||
| 11754 | volatile unsigned long *addr; // some variable to make code readable | ||
| 11755 | unsigned long val,mask; // some variable to make code readable | ||
| 11756 | |||
| 11757 | int finish = -1 ; // loop while this is negative ! | ||
| 11758 | int i = 0; // Timeout variable | ||
| 11759 | |||
| 11760 | while( finish < 0 ) { | ||
| 11761 | numargs = ptr[0] & 0xF; | ||
| 11762 | opcode = ptr[0] >> 4; | ||
| 11763 | |||
| 11764 | for( j = 0 ; j < numargs ; j ++ ) | ||
| 11765 | args[j] = ptr[j+1]; | ||
| 11766 | ptr += numargs + 1; | ||
| 11767 | |||
| 11768 | |||
| 11769 | switch ( opcode ) { | ||
| 11770 | |||
| 11771 | case OPCODE_EXIT: | ||
| 11772 | finish = PS7_INIT_SUCCESS; | ||
| 11773 | break; | ||
| 11774 | |||
| 11775 | case OPCODE_CLEAR: | ||
| 11776 | addr = (unsigned long*) args[0]; | ||
| 11777 | *addr = 0; | ||
| 11778 | break; | ||
| 11779 | |||
| 11780 | case OPCODE_WRITE: | ||
| 11781 | addr = (unsigned long*) args[0]; | ||
| 11782 | val = args[1]; | ||
| 11783 | *addr = val; | ||
| 11784 | break; | ||
| 11785 | |||
| 11786 | case OPCODE_MASKWRITE: | ||
| 11787 | addr = (unsigned long*) args[0]; | ||
| 11788 | mask = args[1]; | ||
| 11789 | val = args[2]; | ||
| 11790 | *addr = ( val & mask ) | ( *addr & ~mask); | ||
| 11791 | break; | ||
| 11792 | |||
| 11793 | case OPCODE_MASKPOLL: | ||
| 11794 | addr = (unsigned long*) args[0]; | ||
| 11795 | mask = args[1]; | ||
| 11796 | i = 0; | ||
| 11797 | while (!(*addr & mask)) { | ||
| 11798 | if (i == PS7_MASK_POLL_TIME) { | ||
| 11799 | finish = PS7_INIT_TIMEOUT; | ||
| 11800 | break; | ||
| 11801 | } | ||
| 11802 | i++; | ||
| 11803 | } | ||
| 11804 | break; | ||
| 11805 | case OPCODE_MASKDELAY: | ||
| 11806 | addr = (unsigned long*) args[0]; | ||
| 11807 | mask = args[1]; | ||
| 11808 | int delay = get_number_of_cycles_for_delay(mask); | ||
| 11809 | perf_reset_and_start_timer(); | ||
| 11810 | while ((*addr < delay)) { | ||
| 11811 | } | ||
| 11812 | break; | ||
| 11813 | default: | ||
| 11814 | finish = PS7_INIT_CORRUPT; | ||
| 11815 | break; | ||
| 11816 | } | ||
| 11817 | } | ||
| 11818 | return finish; | ||
| 11819 | } | ||
| 11820 | |||
| 11821 | unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; | ||
| 11822 | unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; | ||
| 11823 | unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; | ||
| 11824 | unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; | ||
| 11825 | unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; | ||
| 11826 | |||
| 11827 | int | ||
| 11828 | ps7_post_config() | ||
| 11829 | { | ||
| 11830 | // Get the PS_VERSION on run time | ||
| 11831 | unsigned long si_ver = ps7GetSiliconVersion (); | ||
| 11832 | int ret = -1; | ||
| 11833 | if (si_ver == PCW_SILICON_VERSION_1) { | ||
| 11834 | ret = ps7_config (ps7_post_config_1_0); | ||
| 11835 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
| 11836 | } else if (si_ver == PCW_SILICON_VERSION_2) { | ||
| 11837 | ret = ps7_config (ps7_post_config_2_0); | ||
| 11838 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
| 11839 | } else { | ||
| 11840 | ret = ps7_config (ps7_post_config_3_0); | ||
| 11841 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
| 11842 | } | ||
| 11843 | return PS7_INIT_SUCCESS; | ||
| 11844 | } | ||
| 11845 | |||
| 11846 | int | ||
| 11847 | ps7_debug() | ||
| 11848 | { | ||
| 11849 | // Get the PS_VERSION on run time | ||
| 11850 | unsigned long si_ver = ps7GetSiliconVersion (); | ||
| 11851 | int ret = -1; | ||
| 11852 | if (si_ver == PCW_SILICON_VERSION_1) { | ||
| 11853 | ret = ps7_config (ps7_debug_1_0); | ||
| 11854 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
| 11855 | } else if (si_ver == PCW_SILICON_VERSION_2) { | ||
| 11856 | ret = ps7_config (ps7_debug_2_0); | ||
| 11857 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
| 11858 | } else { | ||
| 11859 | ret = ps7_config (ps7_debug_3_0); | ||
| 11860 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
| 11861 | } | ||
| 11862 | return PS7_INIT_SUCCESS; | ||
| 11863 | } | ||
| 11864 | |||
| 11865 | int | ||
| 11866 | ps7_init() | ||
| 11867 | { | ||
| 11868 | // Get the PS_VERSION on run time | ||
| 11869 | unsigned long si_ver = ps7GetSiliconVersion (); | ||
| 11870 | int ret; | ||
| 11871 | //int pcw_ver = 0; | ||
| 11872 | |||
| 11873 | if (si_ver == PCW_SILICON_VERSION_1) { | ||
| 11874 | ps7_mio_init_data = ps7_mio_init_data_1_0; | ||
| 11875 | ps7_pll_init_data = ps7_pll_init_data_1_0; | ||
| 11876 | ps7_clock_init_data = ps7_clock_init_data_1_0; | ||
| 11877 | ps7_ddr_init_data = ps7_ddr_init_data_1_0; | ||
| 11878 | ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; | ||
| 11879 | //pcw_ver = 1; | ||
| 11880 | |||
| 11881 | } else if (si_ver == PCW_SILICON_VERSION_2) { | ||
| 11882 | ps7_mio_init_data = ps7_mio_init_data_2_0; | ||
| 11883 | ps7_pll_init_data = ps7_pll_init_data_2_0; | ||
| 11884 | ps7_clock_init_data = ps7_clock_init_data_2_0; | ||
| 11885 | ps7_ddr_init_data = ps7_ddr_init_data_2_0; | ||
| 11886 | ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; | ||
| 11887 | //pcw_ver = 2; | ||
| 11888 | |||
| 11889 | } else { | ||
| 11890 | ps7_mio_init_data = ps7_mio_init_data_3_0; | ||
| 11891 | ps7_pll_init_data = ps7_pll_init_data_3_0; | ||
| 11892 | ps7_clock_init_data = ps7_clock_init_data_3_0; | ||
| 11893 | ps7_ddr_init_data = ps7_ddr_init_data_3_0; | ||
| 11894 | ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; | ||
| 11895 | //pcw_ver = 3; | ||
| 11896 | } | ||
| 11897 | |||
| 11898 | // MIO init | ||
| 11899 | ret = ps7_config (ps7_mio_init_data); | ||
| 11900 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
| 11901 | |||
| 11902 | // PLL init | ||
| 11903 | ret = ps7_config (ps7_pll_init_data); | ||
| 11904 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
| 11905 | |||
| 11906 | // Clock init | ||
| 11907 | ret = ps7_config (ps7_clock_init_data); | ||
| 11908 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
| 11909 | |||
| 11910 | // DDR init | ||
| 11911 | ret = ps7_config (ps7_ddr_init_data); | ||
| 11912 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
| 11913 | |||
| 11914 | |||
| 11915 | |||
| 11916 | // Peripherals init | ||
| 11917 | ret = ps7_config (ps7_peripherals_init_data); | ||
| 11918 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
| 11919 | //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); | ||
| 11920 | return PS7_INIT_SUCCESS; | ||
| 11921 | } | ||
| 11922 | |||
| 11923 | |||
| 11924 | |||
| 11925 | |||
| 11926 | /* For delay calculation using global timer */ | ||
| 11927 | |||
| 11928 | /* start timer */ | ||
| 11929 | void perf_start_clock(void) | ||
| 11930 | { | ||
| 11931 | *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable | ||
| 11932 | (1 << 3) | // Auto-increment | ||
| 11933 | (0 << 8) // Pre-scale | ||
| 11934 | ); | ||
| 11935 | } | ||
| 11936 | |||
| 11937 | /* stop timer and reset timer count regs */ | ||
| 11938 | void perf_reset_clock(void) | ||
| 11939 | { | ||
| 11940 | perf_disable_clock(); | ||
| 11941 | *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; | ||
| 11942 | *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; | ||
| 11943 | } | ||
| 11944 | |||
| 11945 | /* Compute mask for given delay in miliseconds*/ | ||
| 11946 | int get_number_of_cycles_for_delay(unsigned int delay) | ||
| 11947 | { | ||
| 11948 | // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) | ||
| 11949 | return (APU_FREQ*delay/(2*1000)); | ||
| 11950 | |||
| 11951 | } | ||
| 11952 | |||
| 11953 | /* stop timer */ | ||
| 11954 | void perf_disable_clock(void) | ||
| 11955 | { | ||
| 11956 | *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; | ||
| 11957 | } | ||
| 11958 | |||
| 11959 | void perf_reset_and_start_timer() | ||
| 11960 | { | ||
| 11961 | perf_reset_clock(); | ||
| 11962 | perf_start_clock(); | ||
| 11963 | } | ||
| 11964 | |||
| 11965 | |||
| 11966 | |||
| 11967 | |||
diff --git a/recipes-bsp/platform-init/platform-init/zybo-zynq7/ps7_init_gpl.h b/recipes-bsp/platform-init/platform-init/zybo-zynq7/ps7_init_gpl.h new file mode 100644 index 00000000..41c0480b --- /dev/null +++ b/recipes-bsp/platform-init/platform-init/zybo-zynq7/ps7_init_gpl.h | |||
| @@ -0,0 +1,130 @@ | |||
| 1 | |||
| 2 | /****************************************************************************** | ||
| 3 | * | ||
| 4 | * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License along | ||
| 17 | * with this program; if not, see <http://www.gnu.org/licenses/> | ||
| 18 | * | ||
| 19 | * | ||
| 20 | *******************************************************************************/ | ||
| 21 | /****************************************************************************/ | ||
| 22 | /** | ||
| 23 | * | ||
| 24 | * @file ps7_init.h | ||
| 25 | * | ||
| 26 | * This file can be included in FSBL code | ||
| 27 | * to get prototype of ps7_init() function | ||
| 28 | * and error codes | ||
| 29 | * | ||
| 30 | *****************************************************************************/ | ||
| 31 | |||
| 32 | #ifdef __cplusplus | ||
| 33 | extern "C" { | ||
| 34 | #endif | ||
| 35 | |||
| 36 | |||
| 37 | //typedef unsigned int u32; | ||
| 38 | |||
| 39 | |||
| 40 | /** do we need to make this name more unique ? **/ | ||
| 41 | //extern u32 ps7_init_data[]; | ||
| 42 | extern unsigned long * ps7_ddr_init_data; | ||
| 43 | extern unsigned long * ps7_mio_init_data; | ||
| 44 | extern unsigned long * ps7_pll_init_data; | ||
| 45 | extern unsigned long * ps7_clock_init_data; | ||
| 46 | extern unsigned long * ps7_peripherals_init_data; | ||
| 47 | |||
| 48 | |||
| 49 | |||
| 50 | #define OPCODE_EXIT 0U | ||
| 51 | #define OPCODE_CLEAR 1U | ||
| 52 | #define OPCODE_WRITE 2U | ||
| 53 | #define OPCODE_MASKWRITE 3U | ||
| 54 | #define OPCODE_MASKPOLL 4U | ||
| 55 | #define OPCODE_MASKDELAY 5U | ||
| 56 | #define NEW_PS7_ERR_CODE 1 | ||
| 57 | |||
| 58 | /* Encode number of arguments in last nibble */ | ||
| 59 | #define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) | ||
| 60 | #define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr | ||
| 61 | #define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val | ||
| 62 | #define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val | ||
| 63 | #define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask | ||
| 64 | #define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask | ||
| 65 | |||
| 66 | /* Returns codes of PS7_Init */ | ||
| 67 | #define PS7_INIT_SUCCESS (0) // 0 is success in good old C | ||
| 68 | #define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now | ||
| 69 | #define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out | ||
| 70 | #define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init | ||
| 71 | #define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit | ||
| 72 | #define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init | ||
| 73 | |||
| 74 | |||
| 75 | /* Silicon Versions */ | ||
| 76 | #define PCW_SILICON_VERSION_1 0 | ||
| 77 | #define PCW_SILICON_VERSION_2 1 | ||
| 78 | #define PCW_SILICON_VERSION_3 2 | ||
| 79 | |||
| 80 | /* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ | ||
| 81 | #define PS7_POST_CONFIG | ||
| 82 | |||
| 83 | /* Freq of all peripherals */ | ||
| 84 | |||
| 85 | #define APU_FREQ 650000000 | ||
| 86 | #define DDR_FREQ 525000000 | ||
| 87 | #define DCI_FREQ 10096154 | ||
| 88 | #define QSPI_FREQ 200000000 | ||
| 89 | #define SMC_FREQ 10000000 | ||
| 90 | #define ENET0_FREQ 125000000 | ||
| 91 | #define ENET1_FREQ 10000000 | ||
| 92 | #define USB0_FREQ 60000000 | ||
| 93 | #define USB1_FREQ 60000000 | ||
| 94 | #define SDIO_FREQ 50000000 | ||
| 95 | #define UART_FREQ 50000000 | ||
| 96 | #define SPI_FREQ 10000000 | ||
| 97 | #define I2C_FREQ 108333336 | ||
| 98 | #define WDT_FREQ 108333336 | ||
| 99 | #define TTC_FREQ 50000000 | ||
| 100 | #define CAN_FREQ 10000000 | ||
| 101 | #define PCAP_FREQ 200000000 | ||
| 102 | #define TPIU_FREQ 200000000 | ||
| 103 | #define FPGA0_FREQ 100000000 | ||
| 104 | #define FPGA1_FREQ 175000000 | ||
| 105 | #define FPGA2_FREQ 12264151 | ||
| 106 | #define FPGA3_FREQ 100000000 | ||
| 107 | |||
| 108 | |||
| 109 | /* For delay calculation using global registers*/ | ||
| 110 | #define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 | ||
| 111 | #define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 | ||
| 112 | #define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 | ||
| 113 | #define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 | ||
| 114 | |||
| 115 | int ps7_config( unsigned long*); | ||
| 116 | int ps7_init(); | ||
| 117 | int ps7_post_config(); | ||
| 118 | int ps7_debug(); | ||
| 119 | char* getPS7MessageInfo(unsigned key); | ||
| 120 | |||
| 121 | void perf_start_clock(void); | ||
| 122 | void perf_disable_clock(void); | ||
| 123 | void perf_reset_clock(void); | ||
| 124 | void perf_reset_and_start_timer(); | ||
| 125 | int get_number_of_cycles_for_delay(unsigned int delay); | ||
| 126 | #ifdef __cplusplus | ||
| 127 | } | ||
| 128 | #endif | ||
| 129 | |||
| 130 | |||