Start 2023.2 development

Signed-off-by: Mark Hatle <mark.hatle@amd.com>

28 files changed, 1413 insertions, 10 deletions

diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch
new file mode 100644
index 00000000..660bc218
--- /dev/null
+++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch
@@ -0,0 +1,305 @@
+From 21cc8144efdaa3cd8dbd7279f87b14fa3432fae4 Mon Sep 17 00:00:00 2001
+From: Jason Wu <jason.wu.misc@gmail.com>
+Date: Sun, 10 Apr 2016 13:14:13 +1000
+Subject: [PATCH 1/3] drm: xilinx: Add encoder for Digilent boards
+
+Add the dglnt_encoder driver that enables DRM support for the VGA and
+HDMI output ports found on many Digilent boards.
+
+Upstream-Status: Pending
+
+Signed-off-by: Sam Bobrowicz <sbobrowicz@digilentinc.com>
+Signed-off-by: Jason Wu <jason.wu.misc@gmail.com>
+---
+ .../bindings/drm/xilinx/dglnt_encoder.txt          |  23 +++
+ drivers/gpu/drm/xilinx/Kconfig                     |   6 +
+ drivers/gpu/drm/xilinx/Makefile                    |   1 +
+ drivers/gpu/drm/xilinx/dglnt_encoder.c             | 217 +++++++++++++++++++++
+ 4 files changed, 247 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
+ create mode 100644 drivers/gpu/drm/xilinx/dglnt_encoder.c
+
+diff --git a/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
+new file mode 100644
+index 0000000..242b24e
+--- /dev/null
++++ b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
+@@ -0,0 +1,23 @@
++Device-Tree bindings for Digilent DRM Encoder Slave
++
++This driver provides support for VGA and HDMI outputs on Digilent FPGA boards.
++The VGA or HDMI port must be connected to a Xilinx display pipeline via an
++axi2vid IP core.
++
++Required properties:
++ - compatible: Should be "digilent,drm-encoder".
++
++Optional properties:
++ - dglnt,edid-i2c: The I2C device connected to the DDC bus on the video
++                   connector. This is used to obtain the supported resolutions
++                   of an attached monitor. If not defined, then a default
++                   set of resolutions is used and the display will initialize
++                   to 720p. Note most VGA connectors on Digilent boards do
++                   not have the DDC bus routed out.
++
++Example:
++
++       encoder_0: digilent_encoder {
++               compatible = "digilent,drm-encoder";
++               dglnt,edid-i2c = <&i2c1>;
++       };
+diff --git a/drivers/gpu/drm/xilinx/Kconfig b/drivers/gpu/drm/xilinx/Kconfig
+index 57e18a9..d9ecff2 100644
+--- a/drivers/gpu/drm/xilinx/Kconfig
++++ b/drivers/gpu/drm/xilinx/Kconfig
+@@ -33,6 +33,12 @@ config DRM_XILINX_DP_SUB
+        help
+          DRM driver for Xilinx Display Port Subsystem.
+ 
++config DRM_DIGILENT_ENCODER
++   tristate "Digilent VGA/HDMI DRM Encoder Driver"
++   depends on DRM_XILINX
++   help
++     DRM slave encoder for Video-out on Digilent boards.
++
+ config DRM_XILINX_DP_SUB_DEBUG_FS
+        bool "Xilinx DRM DPSUB debugfs"
+        depends on DEBUG_FS && DRM_XILINX_DP_SUB
+diff --git a/drivers/gpu/drm/xilinx/Makefile b/drivers/gpu/drm/xilinx/Makefile
+index 19bc154..c2717e40 100644
+--- a/drivers/gpu/drm/xilinx/Makefile
++++ b/drivers/gpu/drm/xilinx/Makefile
+@@ -7,6 +7,7 @@ xilinx_drm-y := xilinx_drm_crtc.o xilinx_drm_connector.o xilinx_drm_drv.o \
+                xilinx_drm_plane.o
+ xilinx_drm-y += xilinx_cresample.o xilinx_osd.o xilinx_rgb2yuv.o xilinx_vtc.o
+ 
++obj-$(CONFIG_DRM_DIGILENT_ENCODER) += dglnt_encoder.o
+ obj-$(CONFIG_DRM_XILINX) += xilinx_drm.o
+ obj-$(CONFIG_DRM_XILINX_DP) += xilinx_drm_dp.o
+ obj-$(CONFIG_DRM_XILINX_DP_SUB) += xilinx_drm_dp_sub.o
+diff --git a/drivers/gpu/drm/xilinx/dglnt_encoder.c b/drivers/gpu/drm/xilinx/dglnt_encoder.c
+new file mode 100644
+index 0000000..cb9fc7d
+--- /dev/null
++++ b/drivers/gpu/drm/xilinx/dglnt_encoder.c
+@@ -0,0 +1,217 @@
++/*
++ * dglnt_encoder.c - DRM slave encoder for Video-out on Digilent boards
++ *
++ * Copyright (C) 2015 Digilent
++ * Author: Sam Bobrowicz <sbobrowicz@digilentinc.com>
++ *
++ * Based on udl_encoder.c and udl_connector.c, Copyright (C) 2012 Red Hat.
++ * Also based on xilinx_drm_dp.c, Copyright (C) 2014 Xilinx, Inc.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <drm/drmP.h>
++#include <drm/drm_edid.h>
++#include <drm/drm_encoder_slave.h>
++
++#include <linux/device.h>
++#include <linux/module.h>
++#include <linux/err.h>
++#include <linux/i2c.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++
++#define DGLNT_ENC_MAX_FREQ 150000
++#define DGLNT_ENC_MAX_H 1920
++#define DGLNT_ENC_MAX_V 1080
++#define DGLNT_ENC_PREF_H 1280
++#define DGLNT_ENC_PREF_V 720
++
++struct dglnt_encoder {
++       struct drm_encoder *encoder;
++       struct i2c_adapter *i2c_bus;
++       bool i2c_present;
++};
++
++static inline struct dglnt_encoder *to_dglnt_encoder(
++                                       struct drm_encoder *encoder)
++{
++       return to_encoder_slave(encoder)->slave_priv;
++}
++
++static bool dglnt_mode_fixup(struct drm_encoder *encoder,
++                               const struct drm_display_mode *mode,
++                               struct drm_display_mode *adjusted_mode)
++{
++       return true;
++}
++
++static void dglnt_encoder_mode_set(struct drm_encoder *encoder,
++                               struct drm_display_mode *mode,
++                               struct drm_display_mode *adjusted_mode)
++{
++}
++
++static void
++dglnt_encoder_dpms(struct drm_encoder *encoder, int mode)
++{
++}
++
++static void dglnt_encoder_save(struct drm_encoder *encoder)
++{
++}
++
++static void dglnt_encoder_restore(struct drm_encoder *encoder)
++{
++}
++
++static int dglnt_encoder_mode_valid(struct drm_encoder *encoder,
++                               struct drm_display_mode *mode)
++{
++       if (mode &&
++               !(mode->flags & ((DRM_MODE_FLAG_INTERLACE |
++                       DRM_MODE_FLAG_DBLCLK) | DRM_MODE_FLAG_3D_MASK)) &&
++               (mode->clock <= DGLNT_ENC_MAX_FREQ) &&
++               (mode->hdisplay <= DGLNT_ENC_MAX_H) &&
++               (mode->vdisplay <= DGLNT_ENC_MAX_V))
++               return MODE_OK;
++       return MODE_BAD;
++}
++
++static int dglnt_encoder_get_modes(struct drm_encoder *encoder,
++                               struct drm_connector *connector)
++{
++       struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder);
++       struct edid *edid;
++       int num_modes = 0;
++
++       if (dglnt->i2c_present) {
++               edid = drm_get_edid(connector, dglnt->i2c_bus);
++               drm_connector_update_edid_property(connector, edid);
++               if (edid) {
++                       num_modes = drm_add_edid_modes(connector, edid);
++                       kfree(edid);
++               }
++       } else {
++               num_modes = drm_add_modes_noedid(connector, DGLNT_ENC_MAX_H,
++                                               DGLNT_ENC_MAX_V);
++               drm_set_preferred_mode(connector, DGLNT_ENC_PREF_H,
++                                       DGLNT_ENC_PREF_V);
++       }
++       return num_modes;
++}
++
++static enum drm_connector_status dglnt_encoder_detect(
++                                       struct drm_encoder *encoder,
++                                       struct drm_connector *connector)
++{
++       struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder);
++
++       if (dglnt->i2c_present) {
++               if (drm_probe_ddc(dglnt->i2c_bus))
++                       return connector_status_connected;
++               return connector_status_disconnected;
++       } else
++               return connector_status_unknown;
++}
++
++static struct drm_encoder_slave_funcs dglnt_encoder_slave_funcs = {
++       .dpms                   = dglnt_encoder_dpms,
++       .save                   = dglnt_encoder_save,
++       .restore                = dglnt_encoder_restore,
++       .mode_fixup             = dglnt_mode_fixup,
++       .mode_valid             = dglnt_encoder_mode_valid,
++       .mode_set               = dglnt_encoder_mode_set,
++       .detect                 = dglnt_encoder_detect,
++       .get_modes              = dglnt_encoder_get_modes,
++};
++
++static int dglnt_encoder_encoder_init(struct platform_device *pdev,
++                               struct drm_device *dev,
++                               struct drm_encoder_slave *encoder)
++{
++       struct dglnt_encoder *dglnt = platform_get_drvdata(pdev);
++       struct device_node *sub_node;
++
++       encoder->slave_priv = dglnt;
++       encoder->slave_funcs = &dglnt_encoder_slave_funcs;
++
++       dglnt->encoder = &encoder->base;
++
++       /* get i2c adapter for edid */
++       dglnt->i2c_present = false;
++       sub_node = of_parse_phandle(pdev->dev.of_node, "dglnt,edid-i2c", 0);
++       if (sub_node) {
++               dglnt->i2c_bus = of_find_i2c_adapter_by_node(sub_node);
++               if (!dglnt->i2c_bus)
++                       DRM_INFO("failed to get the edid i2c adapter, using default modes\n");
++               else
++                       dglnt->i2c_present = true;
++               of_node_put(sub_node);
++       }
++
++       return 0;
++}
++
++static int dglnt_encoder_probe(struct platform_device *pdev)
++{
++       struct dglnt_encoder *dglnt;
++
++       dglnt = devm_kzalloc(&pdev->dev, sizeof(*dglnt), GFP_KERNEL);
++       if (!dglnt)
++               return -ENOMEM;
++
++       platform_set_drvdata(pdev, dglnt);
++
++       return 0;
++}
++
++static int dglnt_encoder_remove(struct platform_device *pdev)
++{
++       return 0;
++}
++
++static const struct of_device_id dglnt_encoder_of_match[] = {
++       { .compatible = "digilent,drm-encoder", },
++       { /* end of table */ },
++};
++MODULE_DEVICE_TABLE(of, dglnt_encoder_of_match);
++
++static struct drm_platform_encoder_driver dglnt_encoder_driver = {
++       .platform_driver = {
++               .probe                  = dglnt_encoder_probe,
++               .remove                 = dglnt_encoder_remove,
++               .driver                 = {
++                       .owner          = THIS_MODULE,
++                       .name           = "dglnt-drm-enc",
++                       .of_match_table = dglnt_encoder_of_match,
++               },
++       },
++
++       .encoder_init = dglnt_encoder_encoder_init,
++};
++
++static int __init dglnt_encoder_init(void)
++{
++       return platform_driver_register(&dglnt_encoder_driver.platform_driver);
++}
++
++static void __exit dglnt_encoder_exit(void)
++{
++       platform_driver_unregister(&dglnt_encoder_driver.platform_driver);
++}
++
++module_init(dglnt_encoder_init);
++module_exit(dglnt_encoder_exit);
++
++MODULE_AUTHOR("Digilent, Inc.");
++MODULE_DESCRIPTION("DRM slave encoder for Video-out on Digilent boards");
++MODULE_LICENSE("GPL v2");
+-- 
+2.7.4
+
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch
new file mode 100644
index 00000000..9b6229db
--- /dev/null
+++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch
@@ -0,0 +1,607 @@
+From 217e3b6f4393926b8dcad841381527ef3fc808c2 Mon Sep 17 00:00:00 2001
+From: Jason Wu <jason.wu.misc@gmail.com>
+Date: Sun, 10 Apr 2016 13:16:06 +1000
+Subject: [PATCH 2/3] clk: Add driver for axi_dynclk IP Core
+
+Add support for the axi_dynclk IP Core available from Digilent. This IP
+core dynamically configures the clock resources inside a Xilinx FPGA to
+generate a clock with a software programmable frequency.
+
+Upstream-Status: Pending
+
+Signed-off-by: Sam Bobrowicz <sbobrowicz@digilentinc.com>
+Signed-off-by: Jason Wu <jason.wu.misc@gmail.com>
+---
+ drivers/clk/Kconfig            |   8 +
+ drivers/clk/Makefile           |   1 +
+ drivers/clk/clk-dglnt-dynclk.c | 547 +++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 556 insertions(+)
+ create mode 100644 drivers/clk/clk-dglnt-dynclk.c
+
+diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
+index dccb111100..7fe65a702b 100644
+--- a/drivers/clk/Kconfig
++++ b/drivers/clk/Kconfig
+@@ -148,6 +148,14 @@ config CLK_QORIQ
+          This adds the clock driver support for Freescale QorIQ platforms
+          using common clock framework.
+ 
++config COMMON_CLK_DGLNT_DYNCLK
++       tristate "Digilent axi_dynclk Driver"
++       depends on ARCH_ZYNQ || MICROBLAZE
++       help
++       ---help---
++         Support for the Digilent AXI Dynamic Clock core for Xilinx
++         FPGAs.
++
+ config COMMON_CLK_XGENE
+        bool "Clock driver for APM XGene SoC"
+        default y
+diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
+index 0760449dde..45ce97d053 100644
+--- a/drivers/clk/Makefile
++++ b/drivers/clk/Makefile
+@@ -24,6 +24,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE706)      += clk-cdce706.o
+ obj-$(CONFIG_COMMON_CLK_CDCE925)       += clk-cdce925.o
+ obj-$(CONFIG_ARCH_CLPS711X)            += clk-clps711x.o
+ obj-$(CONFIG_COMMON_CLK_CS2000_CP)     += clk-cs2000-cp.o
++obj-$(CONFIG_COMMON_CLK_DGLNT_DYNCLK)  += clk-dglnt-dynclk.o
+ obj-$(CONFIG_ARCH_EFM32)               += clk-efm32gg.o
+ obj-$(CONFIG_ARCH_HIGHBANK)            += clk-highbank.o
+ obj-$(CONFIG_COMMON_CLK_MAX77686)      += clk-max77686.o
+diff --git a/drivers/clk/clk-dglnt-dynclk.c b/drivers/clk/clk-dglnt-dynclk.c
+new file mode 100644
+index 0000000000..496ad5fc90
+--- /dev/null
++++ b/drivers/clk/clk-dglnt-dynclk.c
+@@ -0,0 +1,547 @@
++/*
++ * clk-dglnt-dynclk.c - Digilent AXI Dynamic Clock (axi_dynclk) Driver
++ *
++ * Copyright (C) 2015 Digilent
++ * Author: Sam Bobrowicz <sbobrowicz@digilentinc.com>
++ *
++ * Reused code from clk-axi-clkgen.c, Copyright (C) 2012-2013 Analog Devices Inc.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/platform_device.h>
++#include <linux/clk-provider.h>
++#include <linux/clk.h>
++#include <linux/slab.h>
++#include <linux/io.h>
++#include <linux/of.h>
++#include <linux/module.h>
++#include <linux/err.h>
++#include <linux/kernel.h>
++
++#define CLK_BIT_WEDGE 13
++#define CLK_BIT_NOCOUNT 12
++
++/* This value is used to signal an error */
++#define ERR_CLKCOUNTCALC 0xFFFFFFFF
++#define ERR_CLKDIVIDER (1 << CLK_BIT_WEDGE | 1 << CLK_BIT_NOCOUNT)
++
++#define DYNCLK_DIV_1_REGMASK 0x1041
++/* 25 MHz (125 KHz / 5) */
++#define DYNCLK_DEFAULT_FREQ 125000
++
++#define MMCM_FREQ_VCOMIN 600000
++#define MMCM_FREQ_VCOMAX 1200000
++#define MMCM_FREQ_PFDMIN 10000
++#define MMCM_FREQ_PFDMAX 450000
++#define MMCM_FREQ_OUTMIN 4000
++#define MMCM_FREQ_OUTMAX 800000
++#define MMCM_DIV_MAX 106
++#define MMCM_FB_MIN 2
++#define MMCM_FB_MAX 64
++#define MMCM_CLKDIV_MAX 128
++#define MMCM_CLKDIV_MIN 1
++
++#define OFST_DISPLAY_CTRL 0x0
++#define OFST_DISPLAY_STATUS 0x4
++#define OFST_DISPLAY_CLK_L 0x8
++#define OFST_DISPLAY_FB_L 0x0C
++#define OFST_DISPLAY_FB_H_CLK_H 0x10
++#define OFST_DISPLAY_DIV 0x14
++#define OFST_DISPLAY_LOCK_L 0x18
++#define OFST_DISPLAY_FLTR_LOCK_H 0x1C
++
++static const u64 lock_lookup[64] = {
++       0b0011000110111110100011111010010000000001,
++       0b0011000110111110100011111010010000000001,
++       0b0100001000111110100011111010010000000001,
++       0b0101101011111110100011111010010000000001,
++       0b0111001110111110100011111010010000000001,
++       0b1000110001111110100011111010010000000001,
++       0b1001110011111110100011111010010000000001,
++       0b1011010110111110100011111010010000000001,
++       0b1100111001111110100011111010010000000001,
++       0b1110011100111110100011111010010000000001,
++       0b1111111111111000010011111010010000000001,
++       0b1111111111110011100111111010010000000001,
++       0b1111111111101110111011111010010000000001,
++       0b1111111111101011110011111010010000000001,
++       0b1111111111101000101011111010010000000001,
++       0b1111111111100111000111111010010000000001,
++       0b1111111111100011111111111010010000000001,
++       0b1111111111100010011011111010010000000001,
++       0b1111111111100000110111111010010000000001,
++       0b1111111111011111010011111010010000000001,
++       0b1111111111011101101111111010010000000001,
++       0b1111111111011100001011111010010000000001,
++       0b1111111111011010100111111010010000000001,
++       0b1111111111011001000011111010010000000001,
++       0b1111111111011001000011111010010000000001,
++       0b1111111111010111011111111010010000000001,
++       0b1111111111010101111011111010010000000001,
++       0b1111111111010101111011111010010000000001,
++       0b1111111111010100010111111010010000000001,
++       0b1111111111010100010111111010010000000001,
++       0b1111111111010010110011111010010000000001,
++       0b1111111111010010110011111010010000000001,
++       0b1111111111010010110011111010010000000001,
++       0b1111111111010001001111111010010000000001,
++       0b1111111111010001001111111010010000000001,
++       0b1111111111010001001111111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001,
++       0b1111111111001111101011111010010000000001
++};
++
++static const u32 filter_lookup_low[64] = {
++       0b0001011111,
++       0b0001010111,
++       0b0001111011,
++       0b0001011011,
++       0b0001101011,
++       0b0001110011,
++       0b0001110011,
++       0b0001110011,
++       0b0001110011,
++       0b0001001011,
++       0b0001001011,
++       0b0001001011,
++       0b0010110011,
++       0b0001010011,
++       0b0001010011,
++       0b0001010011,
++       0b0001010011,
++       0b0001010011,
++       0b0001010011,
++       0b0001010011,
++       0b0001010011,
++       0b0001010011,
++       0b0001010011,
++       0b0001100011,
++       0b0001100011,
++       0b0001100011,
++       0b0001100011,
++       0b0001100011,
++       0b0001100011,
++       0b0001100011,
++       0b0001100011,
++       0b0001100011,
++       0b0001100011,
++       0b0001100011,
++       0b0001100011,
++       0b0001100011,
++       0b0001100011,
++       0b0010010011,
++       0b0010010011,
++       0b0010010011,
++       0b0010010011,
++       0b0010010011,
++       0b0010010011,
++       0b0010010011,
++       0b0010010011,
++       0b0010010011,
++       0b0010010011,
++       0b0010100011,
++       0b0010100011,
++       0b0010100011,
++       0b0010100011,
++       0b0010100011,
++       0b0010100011,
++       0b0010100011,
++       0b0010100011,
++       0b0010100011,
++       0b0010100011,
++       0b0010100011,
++       0b0010100011,
++       0b0010100011,
++       0b0010100011,
++       0b0010100011,
++       0b0010100011,
++       0b0010100011
++};
++
++struct dglnt_dynclk_reg;
++struct dglnt_dynclk_mode;
++struct dglnt_dynclk;
++
++struct dglnt_dynclk_reg {
++       u32 clk0L;
++       u32 clkFBL;
++       u32 clkFBH_clk0H;
++       u32 divclk;
++       u32 lockL;
++       u32 fltr_lockH;
++};
++
++struct dglnt_dynclk_mode {
++       u32 freq;
++       u32 fbmult;
++       u32 clkdiv;
++       u32 maindiv;
++};
++
++struct dglnt_dynclk {
++       void __iomem *base;
++       struct clk_hw clk_hw;
++       unsigned long freq;
++};
++
++u32 dglnt_dynclk_divider(u32 divide)
++{
++       u32 output = 0;
++       u32 highTime = 0;
++       u32 lowTime = 0;
++
++       if ((divide < 1) || (divide > 128))
++               return ERR_CLKDIVIDER;
++
++       if (divide == 1)
++               return DYNCLK_DIV_1_REGMASK;
++
++       highTime = divide / 2;
++       /* if divide is odd */
++       if (divide & 0x1) {
++               lowTime = highTime + 1;
++               output = 1 << CLK_BIT_WEDGE;
++       } else {
++               lowTime = highTime;
++       }
++
++       output |= 0x03F & lowTime;
++       output |= 0xFC0 & (highTime << 6);
++       return output;
++}
++
++u32 dglnt_dynclk_count_calc(u32 divide)
++{
++       u32 output = 0;
++       u32 divCalc = 0;
++
++       divCalc = dglnt_dynclk_divider(divide);
++       if (divCalc == ERR_CLKDIVIDER)
++               output = ERR_CLKCOUNTCALC;
++       else
++               output = (0xFFF & divCalc) | ((divCalc << 10) & 0x00C00000);
++       return output;
++}
++
++
++int dglnt_dynclk_find_reg(struct dglnt_dynclk_reg *regValues,
++                         struct dglnt_dynclk_mode *clkParams)
++{
++       if ((clkParams->fbmult < 2) || clkParams->fbmult > 64)
++               return -EINVAL;
++
++       regValues->clk0L = dglnt_dynclk_count_calc(clkParams->clkdiv);
++       if (regValues->clk0L == ERR_CLKCOUNTCALC)
++               return -EINVAL;
++
++       regValues->clkFBL = dglnt_dynclk_count_calc(clkParams->fbmult);
++       if (regValues->clkFBL == ERR_CLKCOUNTCALC)
++               return -EINVAL;
++
++       regValues->clkFBH_clk0H = 0;
++
++       regValues->divclk = dglnt_dynclk_divider(clkParams->maindiv);
++       if (regValues->divclk == ERR_CLKDIVIDER)
++               return -EINVAL;
++
++       regValues->lockL = (u32)(lock_lookup[clkParams->fbmult - 1] &
++                                0xFFFFFFFF);
++
++       regValues->fltr_lockH = (u32)((lock_lookup[clkParams->fbmult - 1] >>
++                                      32) & 0x000000FF);
++       regValues->fltr_lockH |= ((filter_lookup_low[clkParams->fbmult - 1] <<
++                                  16) & 0x03FF0000);
++
++       return 0;
++}
++
++void dglnt_dynclk_write_reg(struct dglnt_dynclk_reg *regValues,
++                           void __iomem *baseaddr)
++{
++       writel(regValues->clk0L, baseaddr + OFST_DISPLAY_CLK_L);
++       writel(regValues->clkFBL, baseaddr + OFST_DISPLAY_FB_L);
++       writel(regValues->clkFBH_clk0H, baseaddr + OFST_DISPLAY_FB_H_CLK_H);
++       writel(regValues->divclk, baseaddr + OFST_DISPLAY_DIV);
++       writel(regValues->lockL, baseaddr + OFST_DISPLAY_LOCK_L);
++       writel(regValues->fltr_lockH, baseaddr + OFST_DISPLAY_FLTR_LOCK_H);
++}
++
++u32 dglnt_dynclk_find_mode(u32 freq, u32 parentFreq,
++                          struct dglnt_dynclk_mode *bestPick)
++{
++       u32 bestError = MMCM_FREQ_OUTMAX;
++       u32 curError;
++       u32 curClkMult;
++       u32 curFreq;
++       u32 divVal;
++       u32 curFb, curClkDiv;
++       u32 minFb = 0;
++       u32 maxFb = 0;
++       u32 curDiv = 1;
++       u32 maxDiv;
++       bool freq_found = false;
++
++       bestPick->freq = 0;
++       if (parentFreq == 0)
++               return 0;
++
++       /* minimum frequency is actually dictated by VCOmin */
++       if (freq < MMCM_FREQ_OUTMIN)
++               freq = MMCM_FREQ_OUTMIN;
++       if (freq > MMCM_FREQ_OUTMAX)
++               freq = MMCM_FREQ_OUTMAX;
++
++       if (parentFreq > MMCM_FREQ_PFDMAX)
++               curDiv = 2;
++       maxDiv = parentFreq / MMCM_FREQ_PFDMIN;
++       if (maxDiv > MMCM_DIV_MAX)
++               maxDiv = MMCM_DIV_MAX;
++
++       while (curDiv <= maxDiv && !freq_found) {
++               minFb = curDiv * DIV_ROUND_UP(MMCM_FREQ_VCOMIN, parentFreq);
++               maxFb = curDiv * (MMCM_FREQ_VCOMAX / parentFreq);
++               if (maxFb > MMCM_FB_MAX)
++                       maxFb = MMCM_FB_MAX;
++               if (minFb < MMCM_FB_MIN)
++                       minFb = MMCM_FB_MIN;
++
++               divVal = curDiv * freq;
++               /*
++                * This multiplier is used to find the best clkDiv value for
++                * each FB value
++                */
++               curClkMult = ((parentFreq * 1000) + (divVal / 2)) / divVal;
++
++               curFb = minFb;
++               while (curFb <= maxFb && !freq_found) {
++                       curClkDiv = ((curClkMult * curFb) + 500) / 1000;
++                       if (curClkDiv > MMCM_CLKDIV_MAX)
++                               curClkDiv = MMCM_CLKDIV_MAX;
++                       if (curClkDiv < MMCM_CLKDIV_MIN)
++                               curClkDiv = MMCM_CLKDIV_MIN;
++                       curFreq = (((parentFreq * curFb) / curDiv) / curClkDiv);
++                       if (curFreq >= freq)
++                               curError = curFreq - freq;
++                       else
++                               curError = freq - curFreq;
++                       if (curError < bestError) {
++                               bestError = curError;
++                               bestPick->clkdiv = curClkDiv;
++                               bestPick->fbmult = curFb;
++                               bestPick->maindiv = curDiv;
++                               bestPick->freq = curFreq;
++                       }
++                       if (!curError)
++                               freq_found = true;
++                       curFb++;
++               }
++               curDiv++;
++       }
++       return bestPick->freq;
++}
++
++static struct dglnt_dynclk *clk_hw_to_dglnt_dynclk(struct clk_hw *clk_hw)
++{
++       return container_of(clk_hw, struct dglnt_dynclk, clk_hw);
++}
++
++
++static int dglnt_dynclk_enable(struct clk_hw *clk_hw)
++{
++       struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
++       unsigned int clock_state;
++
++       if (dglnt_dynclk->freq) {
++               writel(1, dglnt_dynclk->base + OFST_DISPLAY_CTRL);
++               do {
++                       clock_state = readl(dglnt_dynclk->base +
++                                           OFST_DISPLAY_STATUS);
++               } while (!clock_state);
++       }
++       return 0;
++}
++
++static void dglnt_dynclk_disable(struct clk_hw *clk_hw)
++{
++       struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
++
++       writel(0, dglnt_dynclk->base + OFST_DISPLAY_CTRL);
++}
++
++static int dglnt_dynclk_set_rate(struct clk_hw *clk_hw,
++       unsigned long rate, unsigned long parent_rate)
++{
++       struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
++       struct dglnt_dynclk_reg clkReg;
++       struct dglnt_dynclk_mode clkMode;
++
++       if (parent_rate == 0 || rate == 0)
++               return -EINVAL;
++       if (rate == dglnt_dynclk->freq)
++               return 0;
++
++       /*
++        * Convert from Hz to KHz, then multiply by five to account for
++        * BUFR division
++        */
++       rate = (rate + 100) / 200;
++       /* convert from Hz to KHz */
++       parent_rate = (parent_rate + 500) / 1000;
++       if (!dglnt_dynclk_find_mode(rate, parent_rate, &clkMode))
++               return -EINVAL;
++
++       /*
++        * Write to the PLL dynamic configuration registers to configure it
++        * with the calculated parameters.
++        */
++       dglnt_dynclk_find_reg(&clkReg, &clkMode);
++       dglnt_dynclk_write_reg(&clkReg, dglnt_dynclk->base);
++       dglnt_dynclk->freq = clkMode.freq * 200;
++       dglnt_dynclk_disable(clk_hw);
++       dglnt_dynclk_enable(clk_hw);
++
++       return 0;
++}
++
++static long dglnt_dynclk_round_rate(struct clk_hw *hw, unsigned long rate,
++       unsigned long *parent_rate)
++{
++       struct dglnt_dynclk_mode clkMode;
++
++       dglnt_dynclk_find_mode(((rate + 100) / 200),
++               ((*parent_rate) + 500) / 1000, &clkMode);
++
++       return (clkMode.freq * 200);
++}
++
++static unsigned long dglnt_dynclk_recalc_rate(struct clk_hw *clk_hw,
++       unsigned long parent_rate)
++{
++       struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
++
++       return dglnt_dynclk->freq;
++}
++
++
++static const struct clk_ops dglnt_dynclk_ops = {
++       .recalc_rate = dglnt_dynclk_recalc_rate,
++       .round_rate = dglnt_dynclk_round_rate,
++       .set_rate = dglnt_dynclk_set_rate,
++       .enable = dglnt_dynclk_enable,
++       .disable = dglnt_dynclk_disable,
++};
++
++static const struct of_device_id dglnt_dynclk_ids[] = {
++       { .compatible = "digilent,axi-dynclk", },
++       { },
++};
++MODULE_DEVICE_TABLE(of, dglnt_dynclk_ids);
++
++static int dglnt_dynclk_probe(struct platform_device *pdev)
++{
++       const struct of_device_id *id;
++       struct dglnt_dynclk *dglnt_dynclk;
++       struct clk_init_data init;
++       const char *parent_name;
++       const char *clk_name;
++       struct resource *mem;
++       struct clk *clk;
++
++       if (!pdev->dev.of_node)
++               return -ENODEV;
++
++       id = of_match_node(dglnt_dynclk_ids, pdev->dev.of_node);
++       if (!id)
++               return -ENODEV;
++
++       dglnt_dynclk = devm_kzalloc(&pdev->dev, sizeof(*dglnt_dynclk),
++                                   GFP_KERNEL);
++       if (!dglnt_dynclk)
++               return -ENOMEM;
++
++       mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++       dglnt_dynclk->base = devm_ioremap_resource(&pdev->dev, mem);
++       if (IS_ERR(dglnt_dynclk->base))
++               return PTR_ERR(dglnt_dynclk->base);
++
++       parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
++       if (!parent_name)
++               return -EINVAL;
++
++       clk_name = pdev->dev.of_node->name;
++       of_property_read_string(pdev->dev.of_node, "clock-output-names",
++               &clk_name);
++
++       init.name = clk_name;
++       init.ops = &dglnt_dynclk_ops;
++       init.flags = 0;
++       init.parent_names = &parent_name;
++       init.num_parents = 1;
++
++       dglnt_dynclk->freq = 0;
++       dglnt_dynclk_disable(&dglnt_dynclk->clk_hw);
++
++       dglnt_dynclk->clk_hw.init = &init;
++       clk = devm_clk_register(&pdev->dev, &dglnt_dynclk->clk_hw);
++       if (IS_ERR(clk))
++               return PTR_ERR(clk);
++
++       return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get,
++                                  clk);
++}
++
++static int dglnt_dynclk_remove(struct platform_device *pdev)
++{
++       of_clk_del_provider(pdev->dev.of_node);
++
++       return 0;
++}
++
++static struct platform_driver dglnt_dynclk_driver = {
++       .driver = {
++               .name = "dglnt-dynclk",
++               .owner = THIS_MODULE,
++               .of_match_table = dglnt_dynclk_ids,
++       },
++       .probe = dglnt_dynclk_probe,
++       .remove = dglnt_dynclk_remove,
++};
++module_platform_driver(dglnt_dynclk_driver);
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Sam Bobrowicz <sbobrowicz@digilentinc.com>");
++MODULE_DESCRIPTION("CCF Driver for Digilent axi_dynclk IP Core");
+-- 
+2.14.2
+
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch
new file mode 100644
index 00000000..a98d84c5
--- /dev/null
+++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch
@@ -0,0 +1,54 @@
+From 1a18e2b514ae9e75145597ac509a87f656c976ba Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan@nathanrossi.com>
+Date: Mon, 2 May 2016 23:46:42 +1000
+Subject: [PATCH 3/3] drm: xilinx: Fix DPMS transition to on
+
+Fix the issues where the VTC is reset (losing its timing config).
+
+Also fix the issue where the plane destroys its DMA descriptors and
+marks the DMA channels as inactive but never recreates the descriptors
+and never updates the active state when turning DPMS back on.
+
+Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
+Upstream-Status: Pending [This is a workaround]
+---
+ drivers/gpu/drm/xilinx/xilinx_drm_crtc.c  | 1 -
+ drivers/gpu/drm/xilinx/xilinx_drm_plane.c | 3 ++-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
+index 631d35b921..93dbd4b58a 100644
+--- a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
++++ b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
+@@ -88,7 +88,6 @@ static void xilinx_drm_crtc_dpms(struct drm_crtc *base_crtc, int dpms)
+        default:
+                if (crtc->vtc) {
+                        xilinx_vtc_disable(crtc->vtc);
+-                       xilinx_vtc_reset(crtc->vtc);
+                }
+                if (crtc->cresample) {
+                        xilinx_cresample_disable(crtc->cresample);
+diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
+index 6a248b72d4..d2518a4bdf 100644
+--- a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
++++ b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
+@@ -140,7 +140,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane)
+        for (i = 0; i < MAX_NUM_SUB_PLANES; i++) {
+                struct xilinx_drm_plane_dma *dma = &plane->dma[i];
+ 
+-               if (dma->chan && dma->is_active) {
++               if (dma->chan) {
+                        flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
+                        desc = dmaengine_prep_interleaved_dma(dma->chan,
+                                                              &dma->xt,
+@@ -153,6 +153,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane)
+                        dmaengine_submit(desc);
+ 
+                        dma_async_issue_pending(dma->chan);
++                       dma->is_active = true;
+                }
+        }
+ }
+-- 
+2.14.2
+
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0004-minized-wifi-bluetooth.cfg b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0004-minized-wifi-bluetooth.cfg
new file mode 100644
index 00000000..f71e53ab
--- /dev/null
+++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0004-minized-wifi-bluetooth.cfg
@@ -0,0 +1,33 @@
+#
+# Bluetooth config
+#
+CONFIG_BT=y
+CONFIG_BT_BREDR=y
+CONFIG_BT_HS=y
+CONFIG_BT_LE=y
+CONFIG_BT_BCM=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCM=y
+CONFIG_BT_HIDP=y
+CONFIG_CFG80211=y
+CONFIG_CFG80211_DEFAULT_PS=y
+CONFIG_CFG80211_CRDA_SUPPORT=y
+CONFIG_BRCMUTIL=y
+CONFIG_BRCMFMAC=y
+CONFIG_BRCMFMAC_PROTO_BCDC=y
+CONFIG_BRCMFMAC_SDIO=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_SHA256=y
+
+#
+# Regulator config
+#
+CONFIG_REGMAP_IRQ=y
+CONFIG_I2C_XILINX=y
+CONFIG_MFD_DA9062=y
+CONFIG_REGULATOR_DA9062=y
+
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2023.2.bbappend b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2023.2.bbappend
new file mode 100644
index 00000000..c789c7a9
--- /dev/null
+++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2023.2.bbappend
@@ -0,0 +1,12 @@
+FILESEXTRAPATHS:prepend := "${THISDIR}/linux-xlnx/v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}:"
+
+# Note: These patches are very old and doesn't apply on top of 5.x
+#       kernel. For more details refer README.md file.
+
+#SRC_URI:append:zybo-linux-bd-zynq7 = " \
+#       file://0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch \
+#       file://0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch \
+#       file://0003-drm-xilinx-Fix-DPMS-transition-to-on.patch \
+#       "
+
+SRC_URI:append:minized-zynq7 = " file://0004-minized-wifi-bluetooth.cfg"
diff --git a/meta-xilinx-core/conf/layer.conf b/meta-xilinx-core/conf/layer.conf
index 57a76049..19a5e1a1 100644
--- a/meta-xilinx-core/conf/layer.conf
+++ b/meta-xilinx-core/conf/layer.conf
@@ -41,33 +41,29 @@ SIGGEN_EXCLUDE_SAFE_RECIPE_DEPS += " \
   *->xserver-xorg \
 "
 
-XILINX_RELEASE_VERSION ??= "v2023.1"
+XILINX_RELEASE_VERSION ??= "v2023.2"
 
 BUILDCFG_VARS:append = " SOC_VARIANT XILINX_RELEASE_VERSION"
 
-XILINX_QEMU_VERSION[v2022.1] = "v6.1.0-xilinx-v2022.1%"
-XILINX_QEMU_VERSION[v2022.2] = "v6.1.0-xilinx-v2022.2%"
 XILINX_QEMU_VERSION[v2023.1] = "v7.1.0-xilinx-v2023.1%"
+XILINX_QEMU_VERSION[v2023.2] = "v7.1.0-xilinx-v2023.2%"
 PREFERRED_VERSION_qemu-xilinx ?= "${@d.getVarFlag('XILINX_QEMU_VERSION', d.getVar('XILINX_RELEASE_VERSION')) or 'undefined'}"
 PREFERRED_VERSION_qemu-xilinx-native ?= "${@d.getVarFlag('XILINX_QEMU_VERSION', d.getVar('XILINX_RELEASE_VERSION')) or 'undefined'}"
 PREFERRED_VERSION_qemu-xilinx-system-native ?= "${@d.getVarFlag('XILINX_QEMU_VERSION', d.getVar('XILINX_RELEASE_VERSION')) or 'undefined'}"
 PREFERRED_VERSION_qemu-devicetrees ?= "xilinx-${XILINX_RELEASE_VERSION}%"
 
-XILINX_ATF_VERSION[v2022.1] = "2.6-xilinx-v2022.1%"
-XILINX_ATF_VERSION[v2022.2] = "2.6-xilinx-v2022.2%"
 XILINX_ATF_VERSION[v2023.1] = "2.8-xilinx-v2023.1%"
+XILINX_ATF_VERSION[v2023.2] = "2.8-xilinx-v2023.2%"
 PREFERRED_VERSION_arm-trusted-firmware ?= "${@d.getVarFlag('XILINX_ATF_VERSION', d.getVar('XILINX_RELEASE_VERSION')) or 'undefined'}"
 
-XILINX_UBOOT_VERSION[v2022.1] = "v2021.01-xilinx-v2022.1%"
-XILINX_UBOOT_VERSION[v2022.2] = "v2021.01-xilinx-v2022.2%"
 XILINX_UBOOT_VERSION[v2023.1] = "v2023.01-xilinx-v2023.1%"
+XILINX_UBOOT_VERSION[v2023.2] = "v2023.01-xilinx-v2023.2%"
 
 PREFERRED_VERSION_u-boot-xlnx ?= "${@d.getVarFlag('XILINX_UBOOT_VERSION', d.getVar('XILINX_RELEASE_VERSION')) or 'undefined'}"
 PREFERRED_VERSION_u-boot-tools-xlnx ?= "${@d.getVarFlag('XILINX_UBOOT_VERSION', d.getVar('XILINX_RELEASE_VERSION')) or 'undefined'}"
 
-XILINX_LINUX_VERSION[v2022.1] = "5.15.19-xilinx-v2022.1%"
-XILINX_LINUX_VERSION[v2022.2] = "5.15.36-xilinx-v2022.2%"
 XILINX_LINUX_VERSION[v2023.1] = "6.1.5-xilinx-v2023.1%"
+XILINX_LINUX_VERSION[v2023.2] = "6.1.5-xilinx-v2023.2%"
 PREFERRED_VERSION_linux-xlnx ?= "${@d.getVarFlag('XILINX_LINUX_VERSION', d.getVar('XILINX_RELEASE_VERSION')) or 'undefined'}"
 
 # Add support to eSDK for gen-machine-conf if it exists
diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2023.2.bb b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2023.2.bb
new file mode 100644
index 00000000..057c1ef8
--- /dev/null
+++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2023.2.bb
@@ -0,0 +1,15 @@
+SRCBRANCH ?= "2023.2"
+SRCREV = "be635252271de342014a146825870b64bd41d6eb"
+BRANCH = "2023"
+LIC_FILES_CHKSUM ?= "file://LICENSE.md;md5=f4d5df0f12dcea1b1a0124219c0dbab4"
+PV = "${SRCBRANCH}+git${SRCPV}"
+
+REPO = "git://github.com/Xilinx/libmetal.git;protocol=https"
+
+include ${LAYER_PATH_openamp-layer}/recipes-openamp/libmetal/libmetal.inc
+
+RPROVIDES:${PN}-dbg += "libmetal-dbg"
+RPROVIDES:${PN}-dev += "libmetal-dev"
+RPROVIDES:${PN}-lic += "libmetal-lic"
+RPROVIDES:${PN}-src += "libmetal-src"
+RPROVIDES:${PN}-staticdev += "libmetal-staticdev"
diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2023.2.bb b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2023.2.bb
new file mode 100644
index 00000000..d655d9ac
--- /dev/null
+++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2023.2.bb
@@ -0,0 +1,16 @@
+SRCBRANCH ?= "2023.2"
+SRCREV = "c8aaf2f26d5493f492f0af09dd558d45908636da"
+BRANCH = "2023"
+LIC_FILES_CHKSUM ?= "file://LICENSE.md;md5=ab88daf995c0bd0071c2e1e55f3d3505"
+PV = "${SRCBRANCH}+git${SRCPV}"
+REPO = "git://github.com/Xilinx/open-amp.git;protocol=https"
+
+include ${LAYER_PATH_openamp-layer}/recipes-openamp/open-amp/open-amp.inc
+require ${LAYER_PATH_openamp-layer}/vendor/xilinx/recipes-openamp/open-amp/open-amp-xlnx.inc
+
+RPROVIDES:${PN}-dbg += "open-amp-dbg"
+RPROVIDES:${PN}-dev += "open-amp-dev"
+RPROVIDES:${PN}-lic += "open-amp-lic"
+RPROVIDES:${PN}-src += "open-amp-src"
+RPROVIDES:${PN}-staticdev += "open-amp-staticdev"
+
diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2023.2.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2023.2.bb
new file mode 100644
index 00000000..d9d8db7a
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2023.2.bb
@@ -0,0 +1,8 @@
+ATF_VERSION = "2.8"
+SRCREV = "9c3b04f7b996b21428ff4c64da01d12a4526a1b8"
+BRANCH = "xlnx_rebase_v2.8"
+LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031"
+
+
+include arm-trusted-firmware.inc
+
diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2023.2.bb b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2023.2.bb
new file mode 100644
index 00000000..a74670b7
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2023.2.bb
@@ -0,0 +1,72 @@
+SUMMARY  = "Xilinx dfx-mgr libraries"
+DESCRIPTION = "Xilinx Runtime User Space Libraries and Binaries"
+
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=d67bcef754e935bf77b6d7051bd62b5e"
+
+REPO ?= "git://github.com/Xilinx/dfx-mgr.git;protocol=https"
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+BRANCH = "master"
+SRCREV = "5918fb3406d828693cca484b77229ffd031b5dc4"
+SOMAJOR = "1"
+SOMINOR = "0"
+SOVERSION = "${SOMAJOR}.${SOMINOR}"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:zynqmp = "zynqmp"
+COMPATIBLE_MACHINE:versal = "versal"
+
+S = "${WORKDIR}/git"
+
+inherit cmake update-rc.d systemd
+
+DEPENDS += " libwebsockets inotify-tools libdfx zocl libdrm"
+RDEPENDS:${PN} += " freeipmi"
+EXTRA_OECMAKE += " \
+               -DCMAKE_SYSROOT:PATH=${RECIPE_SYSROOT} \
+                "
+
+INITSCRIPT_NAME = "dfx-mgr.sh"
+INITSCRIPT_PARAMS = "start 99 S ."
+
+SYSTEMD_PACKAGES="${PN}"
+SYSTEMD_SERVICE:${PN}="dfx-mgr.service"
+SYSTEMD_AUTO_ENABLE:${PN}="enable"
+
+
+do_install(){
+        install -d ${D}${bindir}
+        install -d ${D}${libdir}
+        install -d ${D}${includedir}
+        install -d ${D}${base_libdir}/firmware/xilinx
+        install -d ${D}${sysconfdir}/dfx-mgrd
+
+        cp ${B}/example/sys/linux/dfx-mgrd-static ${D}${bindir}/dfx-mgrd
+        cp ${B}/example/sys/linux/dfx-mgr-client-static ${D}${bindir}/dfx-mgr-client
+        chrpath -d ${D}${bindir}/dfx-mgrd
+        chrpath -d ${D}${bindir}/dfx-mgr-client
+        install -m 0644 ${S}/src/dfxmgr_client.h ${D}${includedir}
+
+        oe_soinstall ${B}/src/libdfx-mgr.so.${SOVERSION} ${D}${libdir}
+
+        install -m 0755 ${S}/src/daemon.conf ${D}${sysconfdir}/dfx-mgrd/
+
+        if ${@bb.utils.contains('DISTRO_FEATURES', 'sysvinit', 'true', 'false', d)}; then
+                install -d ${D}${sysconfdir}/init.d/
+                install -m 0755 ${S}/src/dfx-mgr.sh ${D}${sysconfdir}/init.d/
+        fi
+
+        install -m 0755 ${S}/src/dfx-mgr.sh ${D}${bindir}
+        install -m 0755 ${S}/src/scripts/xlnx-firmware-detect ${D}${bindir}
+
+        install -d ${D}${systemd_system_unitdir}
+        install -m 0644 ${S}/src/dfx-mgr.service ${D}${systemd_system_unitdir}
+}
+
+PACKAGES =+ "libdfx-mgr"
+
+FILES:${PN} += "${base_libdir}/firmware/xilinx"
+FILES:${PN} += "${@bb.utils.contains('DISTRO_FEATURES','sysvinit','${sysconfdir}/init.d/dfx-mgr.sh', '', d)} ${systemd_system_unitdir}"
+FILES:libdfx-mgr = "${libdir}/libdfx-mgr.so.${SOVERSION} ${libdir}/libdfx-mgr.so.${SOMAJOR}"
diff --git a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_2023.2.bb b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_2023.2.bb
new file mode 100644
index 00000000..11ad0268
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_2023.2.bb
@@ -0,0 +1,23 @@
+SUMMARY = "Xilinx libdfx library"
+DESCRIPTION = "Xilinx libdfx Library and headers"
+
+LICENSE = "MIT & GPL-2.0-or-later"
+LIC_FILES_CHKSUM = "file://LICENSE.md;md5=94aba86aec117f003b958a52f019f1a7"
+
+BRANCH ?= "master"
+REPO ?= "git://github.com/Xilinx/libdfx.git;protocol=https"
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+SRCREV = "52c1d83c72a2b2e85d256411a199ed1baed12ae1"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:zynqmp = "zynqmp"
+COMPATIBLE_MACHINE:versal = "versal"
+
+S = "${WORKDIR}/git"
+
+inherit cmake
+
+# Due to an update where the soname/version was defined, we need to use an RREPLACES
+# so updates will work properly.
+RREPLACES:${PN} = "libdfx"
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-tools-xlnx_2023.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-tools-xlnx_2023.2.bb
new file mode 100644
index 00000000..43fec635
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-tools-xlnx_2023.2.bb
@@ -0,0 +1,21 @@
+require u-boot-tools-xlnx.inc
+require u-boot-xlnx-2023.2.inc
+
+# MUST clear CONFIG_VIDEO to avoid a compilation failure trying to construct
+# bmp_logo.h
+SED_CONFIG_EFI:append = ' -e "s/CONFIG_VIDEO=.*/# CONFIG_VIDEO is not set/"'
+
+# Default do_compile fails with:
+# | error: object directory ../downloads/git2/github.com.Xilinx.u-boot-xlnx.git/objects does not exist; check .git/objects/info/alternates.
+# The regular workaround of calling 'git diff' seems to be problematic.
+do_compile () {
+        oe_runmake -C ${S} tools-only_defconfig O=${B}
+
+        # Disable CONFIG_CMD_LICENSE, license.h is not used by tools and
+        # generating it requires bin2header tool, which for target build
+        # is built with target tools and thus cannot be executed on host.
+        sed -i -e "s/CONFIG_CMD_LICENSE=.*/# CONFIG_CMD_LICENSE is not set/" ${SED_CONFIG_EFI} ${B}/.config
+
+        oe_runmake -C ${S} cross_tools NO_SDL=1 O=${B}
+}
+
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2023.2.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2023.2.inc
new file mode 100644
index 00000000..c2c54090
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2023.2.inc
@@ -0,0 +1,17 @@
+UBOOT_VERSION = "v2023.01"
+
+UBRANCH = "xlnx_rebase_v2023.01"
+
+SRCREV = "87298fde44b43e0552f0f77d7d3c1aaf4f7c9566"
+
+LICENSE = "GPL-2.0-or-later"
+LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897"
+
+# u-boot-xlnx has support for these
+HAS_PLATFORM_INIT ?= " \
+                xilinx_zynqmp_virt_config \
+                xilinx_zynq_virt_defconfig \
+                xilinx_versal_vc_p_a2197_revA_x_prc_01_revA \
+                "
+
+DEPENDS += "bc-native dtc-native python3-setuptools-native gnutls-native"
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2023.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2023.2.bb
new file mode 100644
index 00000000..22075424
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2023.2.bb
@@ -0,0 +1,4 @@
+
+require u-boot-xlnx.inc
+require u-boot-spl-zynq-init.inc
+require u-boot-xlnx-2023.2.inc
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2023.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2023.2.bb
new file mode 100644
index 00000000..9a5022aa
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2023.2.bb
@@ -0,0 +1,6 @@
+
+require qemu-devicetrees.inc
+
+BRANCH ?= "master"
+SRCREV ?= "1c45adcde1fc06432c01be250bf668c6477d8459"
+
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2023.2.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2023.2.inc
new file mode 100644
index 00000000..3309ce11
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2023.2.inc
@@ -0,0 +1,3 @@
+XILINX_QEMU_VERSION = "v7.1.0"
+BRANCH = "master"
+SRCREV = "21adc9f99e813fb24fb65421259b5b0614938376"
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native_2023.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native_2023.2.bb
new file mode 100644
index 00000000..ccfa9956
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native_2023.2.bb
@@ -0,0 +1,9 @@
+require qemu-xilinx-2023.2.inc
+require qemu-xilinx-native-7.1.inc
+require qemu-native-alt.inc
+
+BPN = "qemu-xilinx"
+
+EXTRA_OECONF:append = " --target-list=${@get_qemu_usermode_target_list(d)} --disable-tools --disable-blobs --disable-guest-agent"
+
+PACKAGECONFIG ??= "pie"
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2023.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2023.2.bb
new file mode 100644
index 00000000..21208f72
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2023.2.bb
@@ -0,0 +1,26 @@
+require qemu-system-native-alt.inc
+require qemu-xilinx-2023.2.inc
+require qemu-xilinx-native-7.1.inc
+
+PROVIDES = "qemu-system-native"
+
+EXTRA_OECONF:append = " --target-list=${@get_qemu_system_target_list(d)}"
+
+PACKAGECONFIG ??= "fdt alsa kvm gcrypt pie slirp"
+
+PACKAGECONFIG:remove = "${@'kvm' if not os.path.exists('/usr/include/linux/kvm.h') else ''}"
+
+DEPENDS += "pixman-native qemu-xilinx-native bison-native ninja-native meson-native"
+DEPENDS += "qemu-xilinx-multiarch-helper-native"
+
+do_install:append() {
+    # The following is also installed by qemu-native
+    rm -f ${D}${datadir}/qemu/trace-events-all
+    rm -rf ${D}${datadir}/qemu/keymaps
+    rm -rf ${D}${datadir}/icons
+    rm -rf ${D}${includedir}/qemu-plugin.h
+
+    # Install qmp.py to be used with testimage
+    install -d ${D}${libdir}/qemu-python/qmp/
+    install -D ${S}/python/qemu/qmp/* ${D}${libdir}/qemu-python/qmp/
+}
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx_2023.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx_2023.2.bb
new file mode 100644
index 00000000..1947de0f
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx_2023.2.bb
@@ -0,0 +1,24 @@
+require qemu-xilinx-2023.2.inc
+require recipes-devtools/qemu/qemu.inc
+require qemu-xilinx-7.1.inc
+require qemu-alt.inc
+
+# Links to libmali-xlnx, so it becomes MACHINE_ARCH specific
+DEFAULT_PACKAGE_ARCH := "${PACKAGE_ARCH}"
+MALI_PACKAGE_ARCH = "${@'${MACHINE_ARCH}' if d.getVar('PREFERRED_PROVIDER_virtual/libgles1') == 'libmali-xlnx' else '${DEFAULT_PACKAGE_ARCH}'}"
+PACKAGE_ARCH:class-target = "${@bb.utils.contains_any('DEPENDS', 'libepoxy virglrenderer', '${MALI_PACKAGE_ARCH}', '${DEFAULT_PACKAGE_ARCH}', d)}"
+
+BBCLASSEXTEND = "nativesdk"
+
+RDEPENDS:${PN}:class-target += "bash"
+
+PROVIDES:class-nativesdk = "nativesdk-qemu"
+RPROVIDES:${PN}:class-nativesdk = "nativesdk-qemu"
+
+EXTRA_OECONF:append:class-target = " --target-list=${@get_qemu_target_list(d)}"
+EXTRA_OECONF:append:class-nativesdk = " --target-list=${@get_qemu_target_list(d)}"
+EXTRA_OECONF:append:class-target:mipsarcho32 = "${@bb.utils.contains('BBEXTENDCURR', 'multilib', ' --disable-capstone', '', d)}"
+
+do_install:append:class-nativesdk() {
+    ${@bb.utils.contains('PACKAGECONFIG', 'gtk+', 'make_qemu_wrapper', '', d)}
+}
diff --git a/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2023.2.bb b/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2023.2.bb
new file mode 100644
index 00000000..7849cc93
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2023.2.bb
@@ -0,0 +1,24 @@
+SUMMARY = "Xilinx DisplayPort Linux Kernel module"
+DESCRIPTION = "Out-of-tree DisplayPort(DP) kernel modules provider for aarch64 devices"
+SECTION = "kernel/modules"
+LICENSE = "GPL-2.0-only"
+LIC_FILES_CHKSUM = "file://LICENSE.md;md5=eb723b61539feef013de476e68b5c50a"
+
+XLNX_DP_VERSION = "6.1.0"
+PV = "${XLNX_DP_VERSION}+xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}"
+
+S = "${WORKDIR}/git"
+
+BRANCH ?= "master"
+REPO   ?= "git://github.com/xilinx/dp-modules.git;protocol=https"
+SRCREV ?= "5b0969ac09f301c33bccc140c8f60e832f5cf222"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+inherit module
+
+EXTRA_OEMAKE += "O=${STAGING_KERNEL_BUILDDIR}"
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:zynqmp = "zynqmp"
+COMPATIBLE_MACHINE:versal = "versal"
diff --git a/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2023.2.bb b/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2023.2.bb
new file mode 100644
index 00000000..6e00b6fd
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2023.2.bb
@@ -0,0 +1,24 @@
+SUMMARY = "Xilinx HDMI Linux Kernel module"
+DESCRIPTION = "Out-of-tree HDMI kernel modules provider for MPSoC EG/EV devices"
+SECTION = "kernel/modules"
+LICENSE = "GPL-2.0-only"
+LIC_FILES_CHKSUM = "file://LICENSE.md;md5=b34277fe156508fd5a650609dc36d1fe"
+
+XLNX_HDMI_VERSION = "6.1"
+PV = "${XLNX_HDMI_VERSION}+xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}"
+
+S = "${WORKDIR}/git"
+
+BRANCH ?= "master"
+REPO   ?= "git://github.com/Xilinx/hdmi-modules.git;protocol=https"
+SRCREV = "1c6330f02fea68992e22400fdbc8c0d0e63e2958"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+inherit module
+
+EXTRA_OEMAKE += "O=${STAGING_KERNEL_BUILDDIR}"
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:zynqmp = "zynqmp"
+COMPATIBLE_MACHINE:versal = "versal"
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2023.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2023.2.bb
new file mode 100644
index 00000000..717696cf
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2023.2.bb
@@ -0,0 +1,11 @@
+LINUX_VERSION = "6.1.5"
+YOCTO_META ?= "git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-6.1;destsuffix=yocto-kmeta"
+KBRANCH="xlnx_rebase_v6.1_LTS"
+SRCREV = "943565167d57362181d853ade7ae551488036754"
+SRCREV_meta = "185bcfcbe480c742247d9117011794c69682914f"
+
+KCONF_AUDIT_LEVEL="0"
+
+include linux-xlnx.inc
+
+FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"
diff --git a/meta-xilinx-standalone-experimental/README.md b/meta-xilinx-standalone-experimental/README.md
index 5e246d5c..27528b14 100644
--- a/meta-xilinx-standalone-experimental/README.md
+++ b/meta-xilinx-standalone-experimental/README.md
@@ -34,7 +34,7 @@ $ bitbake meta-xilinx-setup
 ```
 3. Install the setup SDK:
 ```
-$ .${TMPDIR}/tmp/deploy/sdk/x86_64-xilinx-nativesdk-prestep-2023.1....sh -d prestep -y
+$ .${TMPDIR}/tmp/deploy/sdk/x86_64-xilinx-nativesdk-prestep-2023.2....sh -d prestep -y
 ```
 
 Then follow the instructions in the 'prestep/README-setup' file.
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
index 01940e12..afeecdbf 100644
--- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
+++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
@@ -4,9 +4,11 @@ ESW_VER ?= "${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or 'master'
 REPO ??= "git://github.com/Xilinx/embeddedsw.git;protocol=https"
 
 ESW_BRANCH[2023.1] = "xlnx_rel_v2023.1-next"
+ESW_BRANCH[2023.2] = "master-next"
 BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}"
 
 ESW_REV[2023.1] = "5d75b745952f39bc4f37189257f2f228d99089f3"
+ESW_REV[2023.2] = "675797f7a0a048cab241bf1f8004ab16d7ca9213"
 SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}"
 
 EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}"
@@ -14,6 +16,7 @@ EMBEDDEDSW_SRCURI ?= "${REPO};${EMBEDDEDSW_BRANCHARG}"
 
 LICENSE = "MIT"
 LIC_FILES_CHKSUM[xlnx_rel_v2023.1-next] = '15386ea7656d3b83815bce88c0bbe66d'
+LIC_FILES_CHKSUM[master-next] = '15386ea7656d3b83815bce88c0bbe66d'
 LIC_FILES_CHKSUM ??= "file://license.txt;md5=${@d.getVarFlag('LIC_FILES_CHKSUM', d.getVar('BRANCH')) or '0'}"
 
 SRC_URI = "${EMBEDDEDSW_SRCURI}"
diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware_2023.2.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware_2023.2.bb
new file mode 100644
index 00000000..8816dc4d
--- /dev/null
+++ b/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware_2023.2.bb
@@ -0,0 +1,11 @@
+require fsbl-firmware.inc
+
+FILESPATH .= ":${FILE_DIRNAME}/embeddedsw/2023.1:${FILE_DIRNAME}/embeddedsw"
+
+SRC_URI += " \
+            file://makefile-skip-copy_bsp.sh.patch \
+            file://fsbl-fixups.patch \
+           "
+
+# This version does not build for zynq
+COMPATIBLE_MACHINE:zynq = "none"
diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2023.2.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2023.2.bb
new file mode 100644
index 00000000..37861b75
--- /dev/null
+++ b/meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2023.2.bb
@@ -0,0 +1,29 @@
+require plm-firmware.inc
+
+# Separate build directories for versal and versal-net
+SOC_DIR = "versal"
+SOC_DIR:versal-net = "versal_net"
+B = "${S}/lib/sw_apps/versal_plm/src/${SOC_DIR}"
+
+BSP_DIR ?= "${B}/../../misc/versal_plm_bsp"
+
+FILESPATH .= ":${FILE_DIRNAME}/embeddedsw/2023.1:${FILE_DIRNAME}/embeddedsw"
+
+SRC_URI += " \
+            file://makefile-skip-copy_bsp.sh.patch \
+            file://0001-versal_fw-Fixup-core-makefiles.patch \
+           "
+
+EXTRA_COMPILER_FLAGS = "-g -ffunction-sections -fdata-sections -Wall -Wextra -Os -flto -ffat-lto-objects"
+
+do_configure() {
+    # manually do the copy_bsp step first, so as to be able to fix up use of
+    # mb-* commands
+    ${B}/../../misc/${SOC_DIR}/copy_bsp.sh
+}
+
+do_compile() {
+    oe_runmake
+
+    ${MB_OBJCOPY} -O binary ${B}/${ESW_COMPONENT} ${B}/${ESW_COMPONENT}.bin
+}
diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2023.2.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2023.2.bb
new file mode 100644
index 00000000..fe6deddc
--- /dev/null
+++ b/meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2023.2.bb
@@ -0,0 +1,16 @@
+require pmu-firmware.inc
+
+FILESPATH .= ":${FILE_DIRNAME}/embeddedsw/2023.1:${FILE_DIRNAME}/embeddedsw"
+
+SRC_URI += " \
+            file://makefile-skip-copy_bsp.sh.patch \
+            file://0001-zynqmp_pmufw-Fixup-core-makefiles.patch \
+           "
+
+EXTRA_COMPILER_FLAGS = "-ffunction-sections -fdata-sections -Wall -Wextra -Os -flto -ffat-lto-objects"
+
+do_compile() {
+    oe_runmake
+
+    ${MB_OBJCOPY} -O binary ${B}/${ESW_COMPONENT} ${B}/${ESW_COMPONENT}.bin
+}
diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/psm-firmware_2023.2.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/psm-firmware_2023.2.bb
new file mode 100644
index 00000000..569c5a46
--- /dev/null
+++ b/meta-xilinx-standalone/recipes-bsp/embeddedsw/psm-firmware_2023.2.bb
@@ -0,0 +1,34 @@
+require psm-firmware.inc
+
+# Separate build directories for versal and versal-net
+SOC_DIR = "versal"
+SOC_DIR:versal-net = "versal_net"
+B = "${S}/lib/sw_apps/versal_psmfw/src/${SOC_DIR}"
+
+BSP_DIR ?= "${B}/../../misc/versal_psmfw_bsp"
+
+FILESPATH .= ":${FILE_DIRNAME}/embeddedsw/2023.1:${FILE_DIRNAME}/embeddedsw"
+
+SRC_URI += " \
+            file://makefile-skip-copy_bsp.sh.patch \
+            file://0001-versal_fw-Fixup-core-makefiles.patch \
+           "
+
+EXTRA_COMPILER_FLAGS = "-g -ffunction-sections -fdata-sections -Wall -Wextra"
+
+# Override default since we're in a subdirectory deeper now...
+do_configure() {
+    # manually do the copy_bsp step first, so as to be able to fix up use of
+    # mb-* commands
+    if [ ${SOC_DIR} != "versal" ]; then
+        ${B}/../../misc/${SOC_DIR}/copy_bsp.sh
+    else
+        ${B}/../../misc/copy_bsp.sh
+    fi
+}
+
+do_compile() {
+    oe_runmake
+
+    ${MB_OBJCOPY} -O binary ${B}/${ESW_COMPONENT} ${B}/${ESW_COMPONENT}.bin
+}