diff options
author | Alistair Francis <alistair.francis@xilinx.com> | 2016-05-12 10:07:00 -0700 |
---|---|---|
committer | Nathan Rossi <nathan@nathanrossi.com> | 2016-05-15 17:24:32 +1000 |
commit | 8bb409cfd91292f13c4eeae070ad7d049b134440 (patch) | |
tree | 1fc2b6eac0b42f023529d19d945e7ca1c5cac8d2 | |
parent | 60d646aeff4e47ee8441d8e600548aab846f5fb8 (diff) | |
download | meta-xilinx-8bb409cfd91292f13c4eeae070ad7d049b134440.tar.gz |
recipes-zynqmp: qemu: Update the backported patches
The meta layer has updated QEMU to version 2.5.1 which includes a patch
that touches some of the target-arm code. This causes the backported
QEMU patch included in meta-xilinx to not apply.
This patch updates the patch to apply to QEMU 2.5.1.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
-rw-r--r-- | recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch b/recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch index a8b4ffe7..50a17c48 100644 --- a/recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch +++ b/recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch | |||
@@ -1,4 +1,4 @@ | |||
1 | From 4054bfa9e7986c9b7d2bf70f9e10af9647e376fc Mon Sep 17 00:00:00 2001 | 1 | From 9b3c2f321954251e3eb0c908786d0b6953fe9f79 Mon Sep 17 00:00:00 2001 |
2 | From: Alistair Francis <alistair.francis@xilinx.com> | 2 | From: Alistair Francis <alistair.francis@xilinx.com> |
3 | Date: Thu, 18 Feb 2016 14:16:17 +0000 | 3 | Date: Thu, 18 Feb 2016 14:16:17 +0000 |
4 | Subject: [PATCH] target-arm: Add the pmceid0 and pmceid1 registers | 4 | Subject: [PATCH] target-arm: Add the pmceid0 and pmceid1 registers |
@@ -62,10 +62,10 @@ diff --git a/target-arm/helper.c b/target-arm/helper.c | |||
62 | index a420a2a..6a4ec01 100644 | 62 | index a420a2a..6a4ec01 100644 |
63 | --- a/target-arm/helper.c | 63 | --- a/target-arm/helper.c |
64 | +++ b/target-arm/helper.c | 64 | +++ b/target-arm/helper.c |
65 | @@ -4380,6 +4380,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) | 65 | @@ -4324,6 +4324,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) |
66 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | 66 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, |
67 | .access = PL1_R, .type = ARM_CP_CONST, | 67 | .access = PL1_R, .type = ARM_CP_CONST, |
68 | .resetvalue = cpu->mvfr2 }, | 68 | .resetvalue = 0 }, |
69 | + { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, | 69 | + { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, |
70 | + .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | 70 | + .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, |
71 | + .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | 71 | + .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, |