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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-04-15 06:18:29 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-04-15 11:57:10 +0530 |
| commit | 9451b262ab17ffd1a42260fe51ae4d38a62d7d6c (patch) | |
| tree | cf28d912567a8aa873c8b71c3cbfb2fcc58d5b58 | |
| parent | 6db7ce3f5fa5eac54a6ff563cd69b1293c701491 (diff) | |
| download | meta-xilinx-9451b262ab17ffd1a42260fe51ae4d38a62d7d6c.tar.gz | |
linux-xlnx : Updated SRCREV for 2024.1_8411
microblaze: Change TLB mapping and free space allocation
arm64: versal-net Add dcc node and dcc in aliases for versal-net-ipp-rev1.9.dts
arm64: zynqmp: Disable Tri-state for SDIO
arm64: dts: zynqmp: make hw-ecc as the default ecc mode
mailbox: zynqmp: Enable Bufferless IPI usage on Versal-based SOCs
mailbox: zynqmp: Move buffered IPI setup to of_match selected routine
mailbox: zynqmp: Move of_match structure closer to usage
phy: xilinx-xhdmiphy: Configure retimer at FRL training linerate
video/hdmi: Add support for version 3 AVI Infoframe
phy: xilinx-xhdmiphy: Configure HDMIPHY in TMDS mode
drm: xlnx: hdmi: Set wait event flag for TMDS mode
drm: xlnx: hdmi: Fix TMDS clock calculation for RGB YUV422 YUV444 formats
phy: xilinx-xhdmiphy: Add pll-selection allowed range of values for GTYP/GTYE5
drm: xlnx: hdmi: Fix overwriting the max_frl_rate variable
drm: xlnx: hdmi: Downgrade the FRL rate when sink requests
drm: xlnx: hdmi: Fix lts2 state machine
drm: xlnx: hdmi: Implement xlnx_hdmi_frl_config function
drm: xlnx: hdmi: Implement streamdown callback function
drm: xlnx: hdmi: Add support for all FRL line rates
drm: xlnx: hdmi: Implement streamup callback function
drm: xlnx: hdmi: Implement connect callback function
drm: xlnx: hdmi: Set wait event flag in ltsp state
drm: xlnx: hdmi: Fix FRL link and video clock values
drm: xlnx: hdmi: Fix VTC macros as per the IP specification
phy: xilinx-xhdmiphy: Fix MMCM parameter values for GTYE5/GTYP
drm: xlnx: hdmi: Optimize phy configuration function calls
firmware: xilinx: Dont send linux address to get fpga config get status
| -rw-r--r-- | meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb index 6042293b..3008a572 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | LINUX_VERSION = "6.6.10" | 1 | LINUX_VERSION = "6.6.10" |
| 2 | YOCTO_META ?= "git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-6.6;destsuffix=yocto-kmeta" | 2 | YOCTO_META ?= "git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-6.6;destsuffix=yocto-kmeta" |
| 3 | KBRANCH="xlnx_rebase_v6.6_LTS" | 3 | KBRANCH="xlnx_rebase_v6.6_LTS" |
| 4 | SRCREV = "847d102ca8f60e9f5cd17c685ecb525e6373ca6b" | 4 | SRCREV = "73608e3d7f39dc2b44a1d3c135dec85bcb1b67f0" |
| 5 | SRCREV_meta = "5d0809d0d939c7738cb6e5391126c73fd0e4e865" | 5 | SRCREV_meta = "5d0809d0d939c7738cb6e5391126c73fd0e4e865" |
| 6 | 6 | ||
| 7 | KCONF_AUDIT_LEVEL="0" | 7 | KCONF_AUDIT_LEVEL="0" |