meta-microblaze: binutils: Add local patches, including 64-bit support

Signed-off-by: Mark Hatle <mark.hatle@amd.com>

55 files changed, 13693 insertions, 16 deletions

diff --git a/meta-microblaze/recipes-devtools/binutils/binutils-microblaze.inc b/meta-microblaze/recipes-devtools/binutils/binutils-microblaze.inc
index 3701d245..014729a5 100644
--- a/meta-microblaze/recipes-devtools/binutils/binutils-microblaze.inc
+++ b/meta-microblaze/recipes-devtools/binutils/binutils-microblaze.inc
@@ -2,3 +2,62 @@ FILESEXTRAPATHS:append := ":${THISDIR}/binutils"
 
 LDGOLD_ALTS:microblaze = ""
 USE_ALTERNATIVES_FOR:remove:microblaze = "gprof"
+
+# Our changes are all local, no real patch-status
+ERROR_QA:remove = "patch-status"
+
+SRC_URI += " \
+    file://0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch \
+    file://0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch \
+    file://0003-Initial-port-of-core-reading-support-Added-support-f.patch \
+    file://0004-Fix-debug-message-when-register-is-unavailable.patch \
+    file://0005-MicroBlaze-native-gdb-port.patch \
+    file://0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch \
+    file://0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch \
+    file://0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch \
+    file://0009-Depth-Total-number-of-inline-functions-refer-inline-.patch \
+    file://0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch \
+    file://0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch \
+    file://0012-Add-mlittle-endian-and-mbig-endian-flags.patch \
+    file://0013-Disable-the-warning-message-for-eh_frame_hdr.patch \
+    file://0014-Fix-relaxation-of-assembler-resolved-references-Fixu.patch \
+    file://0015-upstream-change-to-garbage-collection-sweep-causes-m.patch \
+    file://0016-Add-new-bit-field-instructions.patch \
+    file://0017-fixed-bug-in-GCC-so-that-It-will-support-.long-0U-an.patch \
+    file://0018-Compiler-will-give-error-messages-in-more-detail-for.patch \
+    file://0019-initial-support-for-MicroBlaze-64-bit-m64.patch \
+    file://0020-initial-support-for-MicroBlaze-64-bit-m64.patch \
+    file://0021-Added-relocations-for-MB-X.patch \
+    file://0022-initial-support-for-MicroBlaze-64-bit-m64.patch \
+    file://0023-Added-relocations-for-MB-X.patch \
+    file://0024-Fixed-MB-x-relocation-issues-Added-imml-for-required.patch \
+    file://0025-Fixed-address-computation-issues-with-64bit-address-.patch \
+    file://0026-Patch-MicroBlaze-Adding-new-relocation-to-support-64.patch \
+    file://0027-Revert-ld-Remove-unused-expression-state-defsym-symb.patch \
+    file://0028-fixing-the-long-long-long-mingw-toolchain-issue.patch \
+    file://0029-Added-support-to-new-arithmetic-single-register-inst.patch \
+    file://0030-double-imml-generation-for-64-bit-values.patch \
+    file://0031-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch \
+    file://0032-This-patch-will-remove-imml-0-and-imml-1-instruction.patch \
+    file://0033-Changing-the-long-to-long-long-as-in-Windows-long-is.patch \
+    file://0034-gas-revert-moving-of-md_pseudo_table-from-const.patch \
+    file://0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch \
+    file://0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch \
+    file://0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch \
+    file://0038-MB-binutils-Upstream-port-issues.patch \
+    file://0039-Initial-port-of-core-reading-support-Added-support-f.patch \
+    file://0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch \
+    file://0041-disable-truncated-register-warning-gdb-remote.c.patch \
+    file://0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch \
+    file://0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch \
+    file://0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch \
+    file://0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch \
+    file://0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch \
+    file://0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch \
+    file://0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch \
+    file://0049-When-unwinding-pc-value-adjust-return-pc-value.patch \
+    file://0050-info-reg-pc-does-not-print-symbolic-value.patch \
+    file://0051-Wrong-target-description-accepted-by-microblaze-arch.patch \
+    file://0052-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch \
+    file://0053-Roll-back-an-improvement-which-inlines-target_gdbarc.patch \
+"
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch
new file mode 100644
index 00000000..fd8a96c9
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch
@@ -0,0 +1,42 @@
+From add4545f804219232f16f96e3a83af2fadf41463 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 10 Oct 2022 15:07:22 +0530
+Subject: [PATCH 01/53] Add initial port of linux gdbserver add
+ gdb_proc_service_h to gdbserver microblaze-linux
+
+gdbserver needs to initialise the microblaze registers
+
+other archs use this step to run a *_arch_setup() to carry out all
+architecture specific setup - may need to add in future
+
+ * add linux-ptrace.o to gdbserver configure
+ * Update breakpoint opcode
+ * fix segfault on connecting gdbserver
+ * add microblaze_linux_memory_remove_breakpoint
+ * add set_solib_svr4_fetch_link_map_offsets
+ * add set_gdbarch_fetch_tls_load_module_address
+ * Force reading of r0 as 0, prevent stores
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdbserver/Makefile.in | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gdbserver/Makefile.in b/gdbserver/Makefile.in
+index d12f8746611..ee606908bae 100644
+--- a/gdbserver/Makefile.in
++++ b/gdbserver/Makefile.in
+@@ -180,6 +180,7 @@ SFILES = \
+        $(srcdir)/linux-loongarch-low.cc \
+        $(srcdir)/linux-low.cc \
+        $(srcdir)/linux-m68k-low.cc \
++        $(srcdir)/linux-microblaze-low.cc \
+        $(srcdir)/linux-mips-low.cc \
+        $(srcdir)/linux-nios2-low.cc \
+        $(srcdir)/linux-or1k-low.cc \
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch
new file mode 100644
index 00000000..ea6689fe
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch
@@ -0,0 +1,639 @@
+From aebe2fdb45467fe4a07874cc310e441a38c23f84 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 10 Oct 2022 15:07:22 +0530
+Subject: [PATCH 02/53] Add initial port of linux gdbserver add
+ gdb_proc_service_h to gdbserver microblaze-linux
+
+gdbserver needs to initialise the microblaze registers
+
+other archs use this step to run a *_arch_setup() to carry out all
+architecture specific setup - may need to add in future
+
+ * add linux-ptrace.o to gdbserver configure
+ * Update breakpoint opcode
+ * fix segfault on connecting gdbserver
+ * add microblaze_linux_memory_remove_breakpoint
+ * add set_solib_svr4_fetch_link_map_offsets
+ * add set_gdbarch_fetch_tls_load_module_address
+ * Force reading of r0 as 0, prevent stores
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/configure.host                  |   2 +
+ gdb/features/Makefile               |   1 +
+ gdb/features/microblaze-linux.xml   |  13 ++
+ gdb/microblaze-linux-tdep.c         |  29 ++-
+ gdb/microblaze-tdep.c               |  35 +++-
+ gdb/microblaze-tdep.h               |   4 +-
+ gdb/regformats/microblaze-linux.dat |  64 +++++++
+ gdb/regformats/reg-microblaze.dat   |  41 +++++
+ gdbserver/configure.srv             |  10 ++
+ gdbserver/linux-microblaze-low.cc   | 269 ++++++++++++++++++++++++++++
+ 10 files changed, 465 insertions(+), 3 deletions(-)
+ create mode 100644 gdb/features/microblaze-linux.xml
+ create mode 100644 gdb/regformats/microblaze-linux.dat
+ create mode 100644 gdb/regformats/reg-microblaze.dat
+ create mode 100644 gdbserver/linux-microblaze-low.cc
+
+diff --git a/gdb/configure.host b/gdb/configure.host
+index da71675b201..877537d06ef 100644
+--- a/gdb/configure.host
++++ b/gdb/configure.host
+@@ -61,6 +61,7 @@ i[34567]86*)          gdb_host_cpu=i386 ;;
+ loongarch*)            gdb_host_cpu=loongarch ;;
+ m68*)                  gdb_host_cpu=m68k ;;
+ mips*)                 gdb_host_cpu=mips ;;
++microblaze*)           gdb_host_cpu=microblaze ;;
+ powerpc* | rs6000)     gdb_host_cpu=powerpc ;;
+ sparcv9 | sparc64)     gdb_host_cpu=sparc ;;
+ s390*)                 gdb_host_cpu=s390 ;;
+@@ -127,6 +128,7 @@ m68*-*-openbsd*)    gdb_host=obsd ;;
+ 
+ m88*-*-openbsd*)       gdb_host=obsd ;;
+ 
++microblaze*-*linux*)   gdb_host=linux ;;
+ mips*-*-linux*)                gdb_host=linux ;;
+ mips*-*-netbsdaout* | mips*-*-knetbsd*-gnu)
+                        gdb_host=nbsd ;;
+diff --git a/gdb/features/Makefile b/gdb/features/Makefile
+index cda6a49d563..8ac30d8cea3 100644
+--- a/gdb/features/Makefile
++++ b/gdb/features/Makefile
+@@ -46,6 +46,7 @@
+ # List of .dat files to create in ../regformats/
+ WHICH = mips-linux mips-dsp-linux \
+        mips64-linux mips64-dsp-linux \
++       microblaze-linux \
+        nios2-linux \
+        or1k-linux \
+        rs6000/powerpc-32 \
+diff --git a/gdb/features/microblaze-linux.xml b/gdb/features/microblaze-linux.xml
+new file mode 100644
+index 00000000000..688a3f83d1e
+--- /dev/null
++++ b/gdb/features/microblaze-linux.xml
+@@ -0,0 +1,13 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++  <architecture>microblaze</architecture>
++  <osabi>GNU/Linux</osabi>
++  <xi:include href="microblaze-core.xml"/>
++</target>
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 7d620a3688b..d25100ef867 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -37,6 +37,22 @@
+ #include "tramp-frame.h"
+ #include "linux-tdep.h"
+ 
++static int microblaze_debug_flag = 0;
++
++static void
++microblaze_debug (const char *fmt, ...)
++{
++  if (microblaze_debug_flag)
++    {
++       va_list args;
++
++       va_start (args, fmt);
++       printf_unfiltered ("MICROBLAZE LINUX: ");
++       vprintf_unfiltered (fmt, args);
++       va_end (args);
++    }
++}
++
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, 
+                                           struct bp_target_info *bp_tgt)
+@@ -50,13 +66,20 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+   /* Determine appropriate breakpoint contents and size for this address.  */
+   bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
+ 
++  /* Make sure we see the memory breakpoints.  */
++  scoped_restore restore_memory
++    = make_scoped_restore_show_memory_breakpoints (1);
++
+   val = target_read_memory (addr, old_contents, bplen);
+ 
+   /* If our breakpoint is no longer at the address, this means that the
+      program modified the code on us, so it is wrong to put back the
+      old value.  */
+   if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
+-    val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++  {
++      val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++      microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
++  }
+ 
+   return val;
+ }
+@@ -129,6 +152,10 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+   /* Trampolines.  */
+   tramp_frame_prepend_unwinder (gdbarch,
+                                &microblaze_linux_sighandler_tramp_frame);
++
++  /* Enable TLS support.  */
++  set_gdbarch_fetch_tls_load_module_address (gdbarch,
++                                             svr4_fetch_objfile_link_map);
+ }
+ 
+ void _initialize_microblaze_linux_tdep ();
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index fc83634d1e6..3ff7ec644b6 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -128,7 +128,38 @@ microblaze_fetch_instruction (CORE_ADDR pc)
+ constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
+ 
+ typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
+-
++static int
++microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
++                                   struct bp_target_info *bp_tgt)
++{
++  CORE_ADDR addr = bp_tgt->placed_address;
++  const unsigned char *bp;
++  int val;
++  int bplen;
++  gdb_byte old_contents[BREAKPOINT_MAX];
++
++  /* Determine appropriate breakpoint contents and size for this address.  */
++  bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
++  if (bp == NULL)
++    error (_("Software breakpoints not implemented for this target."));
++
++  /* Make sure we see the memory breakpoints.  */
++  scoped_restore restore_memory
++    = make_scoped_restore_show_memory_breakpoints (1);
++
++  val = target_read_memory (addr, old_contents, bplen);
++
++  /* If our breakpoint is no longer at the address, this means that the
++     program modified the code on us, so it is wrong to put back the
++     old value.  */
++  if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
++  {
++    val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++    microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
++  }
++
++  return val;
++}
+ 
+ /* Allocate and initialize a frame cache.  */
+ 
+@@ -714,6 +745,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+                                       microblaze_breakpoint::kind_from_pc);
+   set_gdbarch_sw_breakpoint_from_kind (gdbarch,
+                                       microblaze_breakpoint::bp_from_kind);
++  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
+ 
+   set_gdbarch_frame_args_skip (gdbarch, 8);
+ 
+@@ -754,4 +786,5 @@ When non-zero, microblaze specific debugging is enabled."),
+                             NULL,
+                             &setdebuglist, &showdebuglist);
+ 
++
+ }
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 0b4a5a3f472..56736b9b0c9 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -118,6 +118,8 @@ struct microblaze_frame_cache
+ 
+ /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
+    Only used for native debugging.  */
+-#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60}
++#define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
++#define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
++
+ 
+ #endif /* microblaze-tdep.h */
+diff --git a/gdb/regformats/microblaze-linux.dat b/gdb/regformats/microblaze-linux.dat
+new file mode 100644
+index 00000000000..b5b49f485cd
+--- /dev/null
++++ b/gdb/regformats/microblaze-linux.dat
+@@ -0,0 +1,64 @@
++# THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi :set ro:
++# Generated from: microblaze-linux.xml
++name:microblaze_linux
++xmltarget:microblaze-linux.xml
++expedite:r1,rpc
++32:r0
++32:r1
++32:r2
++32:r3
++32:r4
++32:r5
++32:r6
++32:r7
++32:r8
++32:r9
++32:r10
++32:r11
++32:r12
++32:r13
++32:r14
++32:r15
++32:r16
++32:r17
++32:r18
++32:r19
++32:r20
++32:r21
++32:r22
++32:r23
++32:r24
++32:r25
++32:r26
++32:r27
++32:r28
++32:r29
++32:r30
++32:r31
++32:rpc
++32:rmsr
++32:rear
++32:resr
++32:rfsr
++32:rbtr
++32:rpvr0
++32:rpvr1
++32:rpvr2
++32:rpvr3
++32:rpvr4
++32:rpvr5
++32:rpvr6
++32:rpvr7
++32:rpvr8
++32:rpvr9
++32:rpvr10
++32:rpvr11
++32:redr
++32:rpid
++32:rzpr
++32:rtlbx
++32:rtlbsx
++32:rtlblo
++32:rtlbhi
++32:slr
++32:shr
+diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat
+new file mode 100644
+index 00000000000..bd8a4384424
+--- /dev/null
++++ b/gdb/regformats/reg-microblaze.dat
+@@ -0,0 +1,41 @@
++name:microblaze
++expedite:r1,pc
++32:r0
++32:r1
++32:r2
++32:r3
++32:r4
++32:r5
++32:r6
++32:r7
++32:r8
++32:r9
++32:r10
++32:r11
++32:r12
++32:r13
++32:r14
++32:r15
++32:r16
++32:r17
++32:r18
++32:r19
++32:r20
++32:r21
++32:r22
++32:r23
++32:r24
++32:r25
++32:r26
++32:r27
++32:r28
++32:r29
++32:r30
++32:r31
++32:pc
++32:msr
++32:ear
++32:esr
++32:fsr
++32:slr
++32:shr
+diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv
+index 9e861a75088..11ce617e72f 100644
+--- a/gdbserver/configure.srv
++++ b/gdbserver/configure.srv
+@@ -159,6 +159,16 @@ case "${gdbserver_host}" in
+                        srv_linux_regsets=yes
+                        srv_linux_thread_db=yes
+                        ;;
++
++microblaze*-*-linux*)  srv_regobj="microblaze-linux.o"
++                       srv_tgtobj="$srv_linux_obj linux-microblaze-low.o"      
++                       srv_xmlfiles="microblaze-linux.xml"
++                       srv_xmlfiles="${srv_xmlfiles} microblaze-core.xml"
++                       srv_linux_usrregs=yes
++                       srv_linux_regsets=yes
++                       srv_linux_thread_db=yes
++                       ;;
++
+   mips*-*-linux*)      srv_regobj="mips-linux.o"
+                        srv_regobj="${srv_regobj} mips-dsp-linux.o"
+                        srv_regobj="${srv_regobj} mips64-linux.o"
+diff --git a/gdbserver/linux-microblaze-low.cc b/gdbserver/linux-microblaze-low.cc
+new file mode 100644
+index 00000000000..bf9eecc41ab
+--- /dev/null
++++ b/gdbserver/linux-microblaze-low.cc
+@@ -0,0 +1,269 @@
++/* GNU/Linux/Microblaze specific low level interface, for the remote server for
++   GDB.
++   Copyright (C) 1995-2013 Free Software Foundation, Inc.
++
++   This file is part of GDB.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
++
++#include "server.h"
++#include "linux-low.h"
++
++#include "elf/common.h"
++#include "nat/gdb_ptrace.h"
++#include <endian.h>
++
++#include <asm/ptrace.h>
++#include <sys/procfs.h>
++#include <sys/ptrace.h>
++
++#include "gdb_proc_service.h"
++
++
++static int microblaze_regmap[] =
++ {PT_GPR(0),     PT_GPR(1),     PT_GPR(2),     PT_GPR(3),
++  PT_GPR(4),     PT_GPR(5),     PT_GPR(6),     PT_GPR(7),
++  PT_GPR(8),     PT_GPR(9),     PT_GPR(10),    PT_GPR(11),
++  PT_GPR(12),    PT_GPR(13),    PT_GPR(14),    PT_GPR(15),
++  PT_GPR(16),    PT_GPR(17),    PT_GPR(18),    PT_GPR(19),
++  PT_GPR(20),    PT_GPR(21),    PT_GPR(22),    PT_GPR(23),
++  PT_GPR(24),    PT_GPR(25),    PT_GPR(26),    PT_GPR(27),
++  PT_GPR(28),    PT_GPR(29),    PT_GPR(30),    PT_GPR(31),
++  PT_PC,         PT_MSR,        PT_EAR,        PT_ESR,
++  PT_FSR
++  };
++
++
++
++class microblaze_target : public linux_process_target
++{
++public:
++
++  const regs_info *get_regs_info () override;
++
++  const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
++ // CORE_ADDR microblaze_reinsert_addr (regcache *regcache);
++
++protected:
++
++  void low_arch_setup () override;
++
++  bool low_cannot_fetch_register (int regno) override;
++
++  bool low_cannot_store_register (int regno) override;
++
++ // bool low_supports_breakpoints () override;
++
++  CORE_ADDR low_get_pc (regcache *regcache) override;
++
++  void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
++
++  bool low_breakpoint_at (CORE_ADDR pc) override;
++};
++
++/* The singleton target ops object.  */
++
++static microblaze_target the_microblaze_target;
++
++#define microblaze_num_regs (sizeof (microblaze_regmap) / sizeof (microblaze_regmap[0]))
++
++/* Defined in auto-generated file microblaze-linux.c.  */
++void init_registers_microblaze_linux (void);
++extern const struct target_desc *tdesc_microblaze_linux;
++
++bool
++microblaze_target::low_cannot_store_register (int regno)
++{
++  if (microblaze_regmap[regno] == -1 || regno == 0)
++    return 1;
++
++  return 0;
++}
++
++bool
++microblaze_target::low_cannot_fetch_register (int regno)
++{
++  return 0;
++}
++
++CORE_ADDR
++microblaze_target::low_get_pc (struct regcache *regcache)
++{
++  unsigned long pc;
++
++  collect_register_by_name (regcache, "pc", &pc);
++  return (CORE_ADDR) pc;
++}
++
++void
++microblaze_target::low_set_pc (struct regcache *regcache, CORE_ADDR pc)
++{
++  unsigned long newpc = pc;
++
++  supply_register_by_name (regcache, "pc", &newpc);
++}
++
++/* dbtrap insn */
++/* brki r16, 0x18; */
++static const unsigned long microblaze_breakpoint = 0xba0c0018;
++#define microblaze_breakpoint_len 4
++
++/* Implementation of linux_target_ops method "sw_breakpoint_from_kind".  */
++
++const gdb_byte *
++microblaze_target::sw_breakpoint_from_kind (int kind, int *size)
++{
++  *size = microblaze_breakpoint_len;
++  return (const gdb_byte *) &microblaze_breakpoint;
++}
++
++bool
++microblaze_target::low_breakpoint_at (CORE_ADDR where)
++{
++  unsigned long insn;
++
++  read_memory (where, (unsigned char *) &insn, 4);
++  if (insn == microblaze_breakpoint)
++    return 1;
++  /* If necessary, recognize more trap instructions here.  GDB only uses the
++     one.  */
++  return 0;
++}
++#if 0
++CORE_ADDR
++microblaze_target::microblaze_reinsert_addr (struct regcache *regcache)
++{
++  unsigned long pc;
++  collect_register_by_name (regcache, "r15", &pc);
++  return pc;
++}
++#endif
++#if 0
++#ifdef HAVE_PTRACE_GETREGS
++
++static void
++microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
++{
++  int size = register_size (regcache->tdesc, regno);
++
++  memset (buf, 0, sizeof (long));
++
++  if (size < sizeof (long))
++    collect_register (regcache, regno, buf + sizeof (long) - size);
++  else
++    collect_register (regcache, regno, buf);
++}
++
++static void
++microblaze_supply_ptrace_register (struct regcache *regcache,
++                           int regno, const char *buf)
++{
++  int size = register_size (regcache->tdesc, regno);
++
++  if (regno == 0) {
++    unsigned long regbuf_0 = 0;
++    /* clobbering r0 so that it is always 0 as enforced by hardware */
++    supply_register (regcache, regno, (const char*)&regbuf_0);
++  } else {
++      if (size < sizeof (long))
++        supply_register (regcache, regno, buf + sizeof (long) - size);
++      else
++        supply_register (regcache, regno, buf);
++  }
++}
++
++/* Provide only a fill function for the general register set.  ps_lgetregs
++   will use this for NPTL support.  */
++
++static void microblaze_fill_gregset (struct regcache *regcache, void *buf)
++{
++  int i;
++
++  for (i = 0; i < 32; i++)
++    microblaze_collect_ptrace_register (regcache, i, (char *) buf + microblaze_regmap[i]);
++}
++
++static void
++microblaze_store_gregset (struct regcache *regcache, const void *buf)
++{
++  int i;
++
++  for (i = 0; i < 32; i++)
++    supply_register (regcache, i, (char *) buf + microblaze_regmap[i]);
++}
++
++#endif /* HAVE_PTRACE_GETREGS */
++#endif
++
++static struct regset_info microblaze_regsets[] = {
++#if 0
++#ifdef HAVE_PTRACE_GETREGS
++  { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
++  { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL },
++#endif /* HAVE_PTRACE_GETREGS */
++#endif
++  { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL },
++  NULL_REGSET
++};
++
++static struct usrregs_info microblaze_usrregs_info =
++  {
++    microblaze_num_regs,
++    microblaze_regmap,
++  };
++
++static struct regsets_info microblaze_regsets_info =
++  {
++    microblaze_regsets, /* regsets */
++    0, /* num_regsets */
++    NULL, /* disabled_regsets */
++  };
++
++static struct regs_info microblaze_regs_info =
++  {
++    NULL, /* regset_bitmap */
++    &microblaze_usrregs_info,
++    &microblaze_regsets_info
++  };
++
++const regs_info *
++microblaze_target::get_regs_info (void)
++{
++  return &microblaze_regs_info;
++}
++
++/* Support for hardware single step.  */
++
++static int
++microblaze_supports_hardware_single_step (void)
++{
++  return 1;
++}
++
++
++void
++microblaze_target::low_arch_setup (void)
++{
++  current_process ()->tdesc = tdesc_microblaze_linux;
++}
++
++linux_process_target *the_linux_target = &the_microblaze_target;
++
++void
++initialize_low_arch (void)
++{
++  init_registers_microblaze_linux ();
++  initialize_regsets_info (&microblaze_regsets_info);
++}
++
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0003-Initial-port-of-core-reading-support-Added-support-f.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0003-Initial-port-of-core-reading-support-Added-support-f.patch
new file mode 100644
index 00000000..c0515aa6
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0003-Initial-port-of-core-reading-support-Added-support-f.patch
@@ -0,0 +1,301 @@
+From 67943e124abc6b1228d84399fbde5b129015ac7f Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 10 Oct 2022 16:37:53 +0530
+Subject: [PATCH 03/53] Initial port of core reading support Added support for
+ reading notes in linux core dumps Support for reading of PRSTATUS and PSINFO
+ information for rebuilding ".reg" sections of core dumps at run time.
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elf32-microblaze.c      | 84 +++++++++++++++++++++++++++++++++++++
+ gdb/configure.tgt           |  2 +-
+ gdb/microblaze-linux-tdep.c | 17 +++++++-
+ gdb/microblaze-tdep.c       | 48 +++++++++++++++++++++
+ gdb/microblaze-tdep.h       | 28 +++++++++++++
+ 5 files changed, 177 insertions(+), 2 deletions(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 64198b8f1a6..022ce365c59 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -772,6 +772,87 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
+   return _bfd_elf_is_local_label_name (abfd, name);
+ }
+ 
++/* Support for core dump NOTE sections.  */
++static bool
++microblaze_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
++{
++  int offset;
++  unsigned int size;
++
++  switch (note->descsz)
++    {
++      default:
++        return false;
++
++      case 228:         /* Linux/MicroBlaze */
++        /* pr_cursig */
++        elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
++
++        /* pr_pid */
++        elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24);
++
++        /* pr_reg */
++        offset = 72;
++        size = 50 * 4;
++
++        break;
++    }
++
++  /* Make a ".reg/999" section.  */
++  return _bfd_elfcore_make_pseudosection (abfd, ".reg",
++                                          size, note->descpos + offset);
++}
++
++static bool
++microblaze_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
++{
++  switch (note->descsz)
++    {
++      default:
++        return false;
++
++      case 128:         /* Linux/MicroBlaze elf_prpsinfo */
++        elf_tdata (abfd)->core->program
++         = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16);
++        elf_tdata (abfd)->core->command
++         = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80);
++    }
++
++  /* Note that for some reason, a spurious space is tacked
++     onto the end of the args in some (at least one anyway)
++     implementations, so strip it off if it exists.  */
++
++  {
++    char *command = elf_tdata (abfd)->core->command;
++    int n = strlen (command);
++
++    if (0 < n && command[n - 1] == ' ')
++      command[n - 1] = '\0';
++  }
++
++  return true;
++}
++
++/* The microblaze linker (like many others) needs to keep track of
++   the number of relocs that it decides to copy as dynamic relocs in
++   check_relocs for each symbol. This is so that it can later discard
++   them if they are found to be unnecessary.  We store the information
++   in a field extending the regular ELF linker hash table.  */
++
++struct elf32_mb_dyn_relocs
++{
++  struct elf32_mb_dyn_relocs *next;
++
++  /* The input section of the reloc.  */
++  asection *sec;
++
++  /* Total number of relocs copied for the input section.  */
++  bfd_size_type count;
++
++  /* Number of pc-relative relocs copied for the input section.  */
++  bfd_size_type pc_count;
++};
++
+ /* ELF linker hash entry.  */
+ 
+ struct elf32_mb_link_hash_entry
+@@ -3500,4 +3581,7 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
+ #define elf_backend_size_dynamic_sections      microblaze_elf_size_dynamic_sections
+ #define elf_backend_add_symbol_hook            microblaze_elf_add_symbol_hook
+ 
++#define elf_backend_grok_prstatus               microblaze_elf_grok_prstatus
++#define elf_backend_grok_psinfo                 microblaze_elf_grok_psinfo
++
+ #include "elf32-target.h"
+diff --git a/gdb/configure.tgt b/gdb/configure.tgt
+index 47a674201f9..d0673abd2b8 100644
+--- a/gdb/configure.tgt
++++ b/gdb/configure.tgt
+@@ -415,7 +415,7 @@ mep-*-*)
+ 
+ microblaze*-linux-*|microblaze*-*-linux*)
+        # Target: Xilinx MicroBlaze running Linux
+-       gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o \
++       gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o glibc-tdep.o \
+                        symfile-mem.o linux-tdep.o"
+        ;;
+ microblaze*-*-*)
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index d25100ef867..eef09bacec0 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -36,6 +36,7 @@
+ #include "frame-unwind.h"
+ #include "tramp-frame.h"
+ #include "linux-tdep.h"
++#include "glibc-tdep.h"
+ 
+ static int microblaze_debug_flag = 0;
+ 
+@@ -135,11 +136,14 @@ static struct tramp_frame microblaze_linux_sighandler_tramp_frame =
+   microblaze_linux_sighandler_cache_init
+ };
+ 
+-
+ static void
+ microblaze_linux_init_abi (struct gdbarch_info info,
+                           struct gdbarch *gdbarch)
+ {
++  struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *)  gdbarch_tdep (gdbarch);
++
++  tdep->sizeof_gregset = 200;
++
+   linux_init_abi (info, gdbarch, 0);
+ 
+   set_gdbarch_memory_remove_breakpoint (gdbarch,
+@@ -153,6 +157,17 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+   tramp_frame_prepend_unwinder (gdbarch,
+                                &microblaze_linux_sighandler_tramp_frame);
+ 
++  /* BFD target for core files.  */
++  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++  else
++    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++
++
++  /* Shared library handling.  */
++  set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
++  set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
++
+   /* Enable TLS support.  */
+   set_gdbarch_fetch_tls_load_module_address (gdbarch,
+                                              svr4_fetch_objfile_link_map);
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 3ff7ec644b6..7c98331f8a9 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -665,6 +665,43 @@ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
+                                  tdesc_microblaze_with_stack_protect);
+ }
+ 
++void
++microblaze_supply_gregset (const struct regset *regset,
++                        struct regcache *regcache,
++                        int regnum, const void *gregs)
++{
++  const unsigned int *regs = (const unsigned int *)gregs;
++  if (regnum >= 0)
++    regcache->raw_supply (regnum, regs + regnum);
++
++  if (regnum == -1) {
++    int i;
++
++    for (i = 0; i < 50; i++) {
++      regcache->raw_supply (i, regs + i);
++    }
++  }
++}
++
++
++/* Return the appropriate register set for the core section identified
++   by SECT_NAME and SECT_SIZE.  */
++
++static void
++microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
++                                     iterate_over_regset_sections_cb *cb,
++                                     void *cb_data,
++                                     const struct regcache *regcache)
++{
++  struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch);
++
++  cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data);
++
++  cb(".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
++}
++
++
++
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ {
+@@ -716,6 +753,10 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   gdbarch *gdbarch
+     = gdbarch_alloc (&info, gdbarch_tdep_up (new microblaze_gdbarch_tdep));
+ 
++  tdep->gregset = NULL;
++  tdep->sizeof_gregset = 0;
++  tdep->fpregset = NULL;
++  tdep->sizeof_fpregset = 0;
+   set_gdbarch_long_double_bit (gdbarch, 128);
+ 
+   set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS);
+@@ -764,6 +805,13 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
+   if (tdesc_data != NULL)
+     tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data));
++  //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer);
++
++  /* If we have register sets, enable the generic core file support.  */
++  if (tdep->gregset) {
++    set_gdbarch_iterate_over_regset_sections (gdbarch,
++                                          microblaze_iterate_over_regset_sections);
++  }
+ 
+   return gdbarch;
+ }
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 56736b9b0c9..07a160a463c 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -23,8 +23,23 @@
+ #include "gdbarch.h"
+ 
+ /* Microblaze architecture-specific information.  */
++struct microblaze_gregset
++{
++   microblaze_gregset() {}
++   unsigned int gregs[32];
++   unsigned int fpregs[32];
++   unsigned int pregs[16];
++};
++
+ struct microblaze_gdbarch_tdep : gdbarch_tdep_base
+ {
++  int dummy;           // declare something.
++
++  /* Register sets.  */
++  struct regset *gregset;
++  size_t sizeof_gregset;
++  struct regset *fpregset;
++  size_t sizeof_fpregset;
+ };
+ 
+ /* Register numbers.  */
+@@ -121,5 +136,18 @@ struct microblaze_frame_cache
+ #define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
+ #define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
+ 
++extern void microblaze_supply_gregset (const struct regset *regset,
++                                    struct regcache *regcache,
++                                    int regnum, const void *gregs);
++extern void microblaze_collect_gregset (const struct regset *regset,
++                                     const struct regcache *regcache,
++                                     int regnum, void *gregs);
++extern void microblaze_supply_fpregset (struct regcache *regcache,
++                                     int regnum, const void *fpregs);
++extern void microblaze_collect_fpregset (const struct regcache *regcache,
++                                      int regnum, void *fpregs);
++
++extern const struct regset * microblaze_regset_from_core_section (struct gdbarch *gdbarch,
++                                     const char *sect_name, size_t sect_size);
+ 
+ #endif /* microblaze-tdep.h */
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0004-Fix-debug-message-when-register-is-unavailable.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0004-Fix-debug-message-when-register-is-unavailable.patch
new file mode 100644
index 00000000..1383efd8
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0004-Fix-debug-message-when-register-is-unavailable.patch
@@ -0,0 +1,45 @@
+From 087f77ebdbdf5b9b5d199ba92b31c6503cb66b37 Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan.rossi@petalogix.com>
+Date: Tue, 8 May 2012 18:11:17 +1000
+Subject: [PATCH 04/53] Fix debug message when register is unavailable
+
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+
+Conflicts:
+        gdb/frame.c
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/frame.c | 14 +++++++++++---
+ 1 file changed, 11 insertions(+), 3 deletions(-)
+
+diff --git a/gdb/frame.c b/gdb/frame.c
+index d95d63eb0f6..859e1a6553d 100644
+--- a/gdb/frame.c
++++ b/gdb/frame.c
+@@ -1317,12 +1317,20 @@ frame_unwind_register_value (frame_info_ptr next_frame, int regnum)
+          else
+            {
+              int i;
+-             gdb::array_view<const gdb_byte> buf = value->contents ();
++
++             const gdb_byte *buf = NULL;
++             if (value_entirely_available(value)) {
++               gdb::array_view<const gdb_byte> buf = value->contents ();
++             }
+ 
+              gdb_printf (&debug_file, " bytes=");
+              gdb_printf (&debug_file, "[");
+-             for (i = 0; i < register_size (gdbarch, regnum); i++)
+-               gdb_printf (&debug_file, "%02x", buf[i]);
++             if (buf != NULL) {
++               for (i = 0; i < register_size (gdbarch, regnum); i++)
++                 gdb_printf (&debug_file, "%02x", buf[i]);
++             } else {
++               gdb_printf (&debug_file, "unavailable");
++             }
+              gdb_printf (&debug_file, "]");
+            }
+        }
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0005-MicroBlaze-native-gdb-port.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0005-MicroBlaze-native-gdb-port.patch
new file mode 100644
index 00000000..75c06b62
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0005-MicroBlaze-native-gdb-port.patch
@@ -0,0 +1,834 @@
+From 5b633480eb0b45dc15b6416c54535c54c062d23c Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 10 Oct 2022 18:53:46 +0530
+Subject: [PATCH 05/53] MicroBlaze native gdb port.
+
+signed-off-by : Mahesh Bodapati <mbodapat@amd.com>
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/Makefile.in                 |   2 +
+ gdb/configure.nat               |   4 +
+ gdb/features/microblaze-linux.c |  79 +++++++
+ gdb/microblaze-linux-nat.c      | 366 ++++++++++++++++++++++++++++++++
+ gdb/microblaze-linux-tdep.c     |   2 +
+ gdb/microblaze-linux-tdep.h     |  24 +++
+ gdb/microblaze-tdep.c           | 151 ++++++++++++-
+ gdb/microblaze-tdep.h           |  15 +-
+ 8 files changed, 629 insertions(+), 14 deletions(-)
+ create mode 100755 gdb/features/microblaze-linux.c
+ create mode 100755 gdb/microblaze-linux-nat.c
+ create mode 100644 gdb/microblaze-linux-tdep.h
+
+diff --git a/gdb/Makefile.in b/gdb/Makefile.in
+index 0e0f19c40c9..056588d88d0 100644
+--- a/gdb/Makefile.in
++++ b/gdb/Makefile.in
+@@ -1409,6 +1409,7 @@ HFILES_NO_SRCDIR = \
+        memory-map.h \
+        memrange.h \
+        microblaze-tdep.h \
++       microblaze-linux-tdep.h \
+        mips-linux-tdep.h \
+        mips-netbsd-tdep.h \
+        mips-tdep.h \
+@@ -1757,6 +1758,7 @@ ALLDEPFILES = \
+        m68k-linux-nat.c \
+        m68k-linux-tdep.c \
+        m68k-tdep.c \
++       microblaze-linux-nat.c \
+        microblaze-linux-tdep.c \
+        microblaze-tdep.c \
+        mingw-hdep.c \
+diff --git a/gdb/configure.nat b/gdb/configure.nat
+index 8b98511cef7..c9f0fb25010 100644
+--- a/gdb/configure.nat
++++ b/gdb/configure.nat
+@@ -274,6 +274,10 @@ case ${gdb_host} in
+                # Host: Motorola m68k running GNU/Linux.
+                NATDEPFILES="${NATDEPFILES} m68k-linux-nat.o"
+                ;;
++           microblaze)
++               # Host: Microblaze running GNU/Linux.
++               NATDEPFILES="${NATDEPFILES} microblaze-linux-nat.o"
++               ;;
+            mips)
+                # Host: Linux/MIPS
+                NATDEPFILES="${NATDEPFILES} linux-nat-trad.o \
+diff --git a/gdb/features/microblaze-linux.c b/gdb/features/microblaze-linux.c
+new file mode 100755
+index 00000000000..267e12f6d59
+--- /dev/null
++++ b/gdb/features/microblaze-linux.c
+@@ -0,0 +1,79 @@
++/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
++  Original: microblaze.xml */
++
++#include "defs.h"
++#include "osabi.h"
++#include "target-descriptions.h"
++
++struct target_desc *tdesc_microblaze_linux;
++static void
++initialize_tdesc_microblaze_linux (void)
++{
++  target_desc_up result = allocate_target_description ();
++  struct tdesc_feature *feature;
++  set_tdesc_architecture (result.get(), bfd_scan_arch ("microblaze"));
++  set_tdesc_osabi (result.get(), osabi_from_tdesc_string ("GNU/Linux"));
++
++  feature = tdesc_create_feature (result.get(), "org.gnu.gdb.microblaze.core");
++  tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r13", 13, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r14", 14, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r15", 15, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r16", 16, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r17", 17, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r18", 18, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r19", 19, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r20", 20, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r21", 21, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r22", 22, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r23", 23, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r24", 24, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r25", 25, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r26", 26, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r27", 27, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r28", 28, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++
++  tdesc_microblaze_linux = result.release();
++}
+diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c
+new file mode 100755
+index 00000000000..a348001a3e2
+--- /dev/null
++++ b/gdb/microblaze-linux-nat.c
+@@ -0,0 +1,366 @@
++/* Native-dependent code for GNU/Linux MicroBlaze.
++   Copyright (C) 2021 Free Software Foundation, Inc.
++
++   This file is part of GDB.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
++
++#include "defs.h"
++#include "arch-utils.h"
++#include "dis-asm.h"
++#include "frame.h"
++#include "trad-frame.h"
++#include "symtab.h"
++#include "value.h"
++#include "gdbcmd.h"
++#include "breakpoint.h"
++#include "inferior.h"
++#include "gdbthread.h"
++#include "gdbcore.h"
++#include "regcache.h"
++#include "regset.h"
++#include "target.h"
++#include "frame.h"
++#include "frame-base.h"
++#include "frame-unwind.h"
++#include "osabi.h"
++#include "gdbsupport/gdb_assert.h"
++#include <string.h>
++#include "target-descriptions.h"
++#include "opcodes/microblaze-opcm.h"
++#include "opcodes/microblaze-dis.h"
++#include "gregset.h"
++
++#include "linux-nat.h"
++#include "linux-tdep.h"
++#include "target-descriptions.h"
++
++#include <sys/user.h>
++#include <sys/ioctl.h>
++#include <sys/uio.h>
++#include "gdbsupport/gdb_wait.h"
++#include <fcntl.h>
++#include <sys/procfs.h>
++#include "nat/gdb_ptrace.h"
++#include "nat/linux-ptrace.h"
++#include "inf-ptrace.h"
++#include <algorithm>
++#include <unordered_map>
++#include <list>
++#include <sys/ptrace.h>
++
++/* Prototypes for supply_gregset etc. */
++#include "gregset.h"
++
++#include "microblaze-tdep.h"
++#include "microblaze-linux-tdep.h"
++#include "inferior.h"
++
++#include "elf/common.h"
++
++#include "auxv.h"
++#include "linux-tdep.h"
++
++#include <sys/ptrace.h>
++
++
++//int have_ptrace_getsetregs=1;
++
++/* MicroBlaze Linux native additions to the default linux support.  */
++
++class microblaze_linux_nat_target final : public linux_nat_target
++{
++public:
++  /* Add our register access methods.  */
++  void fetch_registers (struct regcache *regcache, int regnum) override;
++  void store_registers (struct regcache *regcache, int regnum) override;
++
++  /* Read suitable target description.  */
++  const struct target_desc *read_description () override;
++};
++
++static microblaze_linux_nat_target the_microblaze_linux_nat_target;
++
++static int
++microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
++{
++  int u_addr = -1;
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
++ *      interface, and not the wordsize of the program's ABI.  */
++  int wordsize = sizeof (long);
++
++  /* General purpose registers occupy 1 slot each in the buffer.  */
++  if (regno >= MICROBLAZE_R0_REGNUM
++      && regno <= MICROBLAZE_FSR_REGNUM)
++    u_addr = ((regno - MICROBLAZE_R0_REGNUM)* wordsize);
++
++  return u_addr;
++}
++
++/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1)
++   from regset GREGS into REGCACHE.  */
++
++static void
++supply_gregset_regnum (struct regcache *regcache, const prgregset_t *gregs,
++                      int regnum)
++{
++  int i;
++  const elf_greg_t *regp = *gregs;
++  /* Access all registers */
++  if (regnum == -1)
++    {
++      /* We fill the general purpose registers.  */
++      for (i = MICROBLAZE_R0_REGNUM + 1; i < MICROBLAZE_FSR_REGNUM; i++)
++       regcache->raw_supply (i, regp + i);
++
++      /* Supply MICROBLAZE_PC_REGNUM from index 32.  */
++      regcache->raw_supply (MICROBLAZE_PC_REGNUM, regp + 32);
++
++      /* Fill the inaccessible zero register with zero.  */
++      regcache->raw_supply_zeroed (0);
++    }
++  else if (regnum == MICROBLAZE_R0_REGNUM)
++    regcache->raw_supply_zeroed (0);
++  else if (regnum == MICROBLAZE_PC_REGNUM)
++    regcache->raw_supply (MICROBLAZE_PC_REGNUM, regp + 32);
++  else if (regnum > MICROBLAZE_R0_REGNUM && regnum < MICROBLAZE_FSR_REGNUM)
++    regcache->raw_supply (regnum, regp + regnum);
++}
++
++/* Copy all general purpose registers from regset GREGS into REGCACHE.  */
++
++void
++supply_gregset (struct regcache *regcache, const prgregset_t *gregs)
++{
++  supply_gregset_regnum (regcache, gregs, -1);
++}
++
++/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1)
++   from REGCACHE into regset GREGS.  */
++
++void
++fill_gregset (const struct regcache *regcache, prgregset_t *gregs, int regnum)
++{
++  elf_greg_t *regp = *gregs;
++  if (regnum == -1)
++    {
++      /* We fill the general purpose registers.  */
++      for (int i = MICROBLAZE_R0_REGNUM + 1; i < MICROBLAZE_FSR_REGNUM; i++)
++       regcache->raw_collect (i, regp + i);
++
++      regcache->raw_collect (MICROBLAZE_PC_REGNUM, regp + 32);
++    }
++  else if (regnum == MICROBLAZE_R0_REGNUM)
++    /* Nothing to do here.  */
++    ;
++  else if (regnum > MICROBLAZE_R0_REGNUM && regnum < MICROBLAZE_FSR_REGNUM)
++    regcache->raw_collect (regnum, regp + regnum);
++  else if (regnum == MICROBLAZE_PC_REGNUM)
++    regcache->raw_collect (MICROBLAZE_PC_REGNUM, regp + 32);
++}
++
++/* Transfering floating-point registers between GDB, inferiors and cores.
++   Since MicroBlaze floating-point registers are the same as GPRs these do
++   nothing.  */
++
++void
++supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregs)
++{
++}
++
++void
++fill_fpregset (const struct regcache *regcache,
++              gdb_fpregset_t *fpregs, int regno)
++{
++}
++
++
++static void
++fetch_register (struct regcache *regcache, int tid, int regno)
++{
++  struct gdbarch *gdbarch = regcache->arch ();
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  /* This isn't really an address.  But ptrace thinks of it as one.  */
++  CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
++  int bytes_transferred;
++  char buf[MICROBLAZE_MAX_REGISTER_SIZE];
++
++  if (regaddr == -1)
++  {
++    memset (buf, '\0', register_size (gdbarch, regno));   /* Supply zeroes */
++    regcache->raw_supply (regno, buf);
++    return;
++  }
++
++  /* Read the raw register using sizeof(long) sized chunks.  On a
++ *      32-bit platform, 64-bit floating-point registers will require two
++ *           transfers.  */
++  for (bytes_transferred = 0;
++       bytes_transferred < register_size (gdbarch, regno);
++       bytes_transferred += sizeof (long))
++  {
++    long l;
++
++    errno = 0;
++    l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
++    if (errno == EIO)
++    {
++      printf("ptrace io error\n");
++    }
++    regaddr += sizeof (long);
++    if (errno != 0)
++    {
++      char message[128];
++      sprintf (message, "reading register %s (#%d)",
++               gdbarch_register_name (gdbarch, regno), regno);
++      perror_with_name (message);
++    }
++    memcpy (&buf[bytes_transferred], &l, sizeof (l));
++  }
++
++  /* Now supply the register.  Keep in mind that the regcache's idea
++ *      of the register's size may not be a multiple of sizeof
++ *           (long).  */
++  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
++  {
++    /* Little-endian values are always found at the left end of the
++ *        bytes transferred.  */
++    regcache->raw_supply (regno, buf);
++  }
++  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++  {
++    /* Big-endian values are found at the right end of the bytes
++ *        transferred.  */
++    size_t padding = (bytes_transferred - register_size (gdbarch, regno));
++    regcache->raw_supply (regno, buf + padding);
++  }
++  else
++    internal_error (__FILE__, __LINE__,
++                    _("fetch_register: unexpected byte order: %d"),
++                    gdbarch_byte_order (gdbarch));
++}
++
++
++/* This is a wrapper for the fetch_all_gp_regs function.  It is
++ * responsible for verifying if this target has the ptrace request
++ * that can be used to fetch all general-purpose registers at one
++ * shot.  If it doesn't, then we should fetch them using the
++ * old-fashioned way, which is to iterate over the registers and
++ * request them one by one.  */
++static void
++fetch_gp_regs (struct regcache *regcache, int tid)
++{
++  int i;
++/* If we've hit this point, it doesn't really matter which
++   architecture we are using.  We just need to read the
++   registers in the "old-fashioned way".  */
++  for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
++    fetch_register (regcache, tid, i);
++}
++
++/* Return a target description for the current target.  */
++
++const struct target_desc *
++microblaze_linux_nat_target::read_description ()
++{
++  return tdesc_microblaze_linux;
++}
++
++/* Fetch REGNUM (or all registers if REGNUM == -1) from the target
++   into REGCACHE using PTRACE_GETREGSET.  */
++
++void
++microblaze_linux_nat_target::fetch_registers (struct regcache * regcache,
++                                              int regno)
++{
++  /* Get the thread id for the ptrace call.  */
++  int tid = regcache->ptid ().lwp ();
++//int tid = get_ptrace_pid (regcache->ptid());
++#if 1 
++  if (regno == -1)
++#endif
++    fetch_gp_regs (regcache, tid);
++#if 1
++  else
++    fetch_register (regcache, tid, regno);
++#endif
++}
++
++
++/* Store REGNUM (or all registers if REGNUM == -1) to the target
++   from REGCACHE using PTRACE_SETREGSET.  */
++
++void
++microblaze_linux_nat_target::store_registers (struct regcache *regcache, int regno)
++{
++  int tid;
++
++  tid = get_ptrace_pid (regcache->ptid ());
++
++ struct gdbarch *gdbarch = regcache->arch ();
++  /* This isn't really an address.  But ptrace thinks of it as one.  */
++  CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
++  int i;
++  size_t bytes_to_transfer;
++  char buf[MICROBLAZE_MAX_REGISTER_SIZE];
++
++  if (regaddr == -1)
++    return;
++
++  /* First collect the register.  Keep in mind that the regcache's
++ *      idea of the register's size may not be a multiple of sizeof
++ *           (long).  */
++  memset (buf, 0, sizeof buf);
++  bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
++  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
++  {
++    /* Little-endian values always sit at the left end of the buffer.  */
++    regcache->raw_collect (regno, buf);
++  }
++  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++  {
++    /* Big-endian values sit at the right end of the buffer.  */
++    size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
++    regcache->raw_collect (regno, buf + padding);
++  }
++
++ for (i = 0; i < bytes_to_transfer; i += sizeof (long))
++  { 
++    long l;
++
++    memcpy (&l, &buf[i], sizeof (l));
++    errno = 0;
++    ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
++    regaddr += sizeof (long);
++
++    if (errno != 0)
++    { 
++      char message[128];
++      sprintf (message, "writing register %s (#%d)",
++               gdbarch_register_name (gdbarch, regno), regno);
++      perror_with_name (message);
++    }
++  }
++}
++
++void _initialize_microblaze_linux_nat (void);
++
++void
++_initialize_microblaze_linux_nat (void)
++{
++  /* Register the target.  */
++  linux_target = &the_microblaze_linux_nat_target;
++  add_inf_child_target (linux_target);
++}
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index eef09bacec0..d086debc4f8 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -37,6 +37,7 @@
+ #include "tramp-frame.h"
+ #include "linux-tdep.h"
+ #include "glibc-tdep.h"
++#include "features/microblaze-linux.c"
+ 
+ static int microblaze_debug_flag = 0;
+ 
+@@ -179,4 +180,5 @@ _initialize_microblaze_linux_tdep ()
+ {
+   gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX, 
+                          microblaze_linux_init_abi);
++  initialize_tdesc_microblaze_linux ();
+ }
+diff --git a/gdb/microblaze-linux-tdep.h b/gdb/microblaze-linux-tdep.h
+new file mode 100644
+index 00000000000..a2c744e2961
+--- /dev/null
++++ b/gdb/microblaze-linux-tdep.h
+@@ -0,0 +1,24 @@
++/* Target-dependent code for GNU/Linux on OpenRISC.
++
++   Copyright (C) 2021 Free Software Foundation, Inc.
++
++   This file is part of GDB.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
++#ifndef MICROBLAZE_LINUX_TDEP_H
++#define MICROBLAZE_LINUX_TDEP_H
++ /* Target descriptions.  */
++ extern struct target_desc *tdesc_microblaze_linux;
++ 
++#endif /* MICROBLAZE_LINUX_TDEP_H */
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 7c98331f8a9..b0b4c1b2614 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -285,6 +285,7 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+          cache->frameless_p = 0; /* Frame found.  */
+          save_hidden_pointer_found = 0;
+          non_stack_instruction_found = 0;
++          cache->register_offsets[rd] = -imm;
+          continue;
+        }
+       else if (IS_SPILL_SP(op, rd, ra))
+@@ -431,15 +432,17 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
+   if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
+     {
+       sal = find_pc_line (func_start, 0);
+-
+-      if (sal.end < func_end
+-         && start_pc <= sal.end)
++ 
++      if (sal.line !=0 && sal.end <= func_end  && start_pc <= sal.end) {
+        start_pc = sal.end;
++    microblaze_debug("start_pc is %d\t sal.end is %d\t func_end is %d\t",start_pc,sal.end,func_end);
++    }
+     }
+ 
+   ostart_pc = microblaze_analyze_prologue (gdbarch, func_start, 0xffffffffUL, 
+                                           &cache);
+ 
++
+   if (ostart_pc > start_pc)
+     return ostart_pc;
+   return start_pc;
+@@ -453,6 +456,7 @@ microblaze_frame_cache (frame_info_ptr next_frame, void **this_cache)
+   struct microblaze_frame_cache *cache;
+   struct gdbarch *gdbarch = get_frame_arch (next_frame);
+   int rn;
++  CORE_ADDR current_pc;
+ 
+   if (*this_cache)
+     return (struct microblaze_frame_cache *) *this_cache;
+@@ -466,10 +470,17 @@ microblaze_frame_cache (frame_info_ptr next_frame, void **this_cache)
+     cache->register_offsets[rn] = -1;
+ 
+   /* Call for side effects.  */
+-  get_frame_func (next_frame);
+-
+-  cache->pc = get_frame_address_in_block (next_frame);
+-
++  cache->pc = get_frame_func (next_frame);
++
++//  cache->pc = get_frame_address_in_block (next_frame);
++  current_pc = get_frame_pc (next_frame);
++  if (cache->pc)
++     microblaze_analyze_prologue (gdbarch, cache->pc, current_pc, cache);
++  
++  cache->saved_sp = cache->base + cache->framesize;
++  cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM] = cache->base;
++  cache->register_offsets[MICROBLAZE_SP_REGNUM] = cache->saved_sp;
++  
+   return cache;
+ }
+ 
+@@ -494,6 +505,25 @@ microblaze_frame_prev_register (frame_info_ptr this_frame,
+   struct microblaze_frame_cache *cache =
+     microblaze_frame_cache (this_frame, this_cache);
+ 
++if ((regnum == MICROBLAZE_SP_REGNUM &&
++      cache->register_offsets[MICROBLAZE_SP_REGNUM])
++      || (regnum == MICROBLAZE_FP_REGNUM &&
++      cache->register_offsets[MICROBLAZE_SP_REGNUM]))
++
++     return frame_unwind_got_constant (this_frame, regnum,
++                                       cache->register_offsets[MICROBLAZE_SP_REGNUM]);
++
++if (regnum == MICROBLAZE_PC_REGNUM)
++{
++      regnum = 15;
++      return frame_unwind_got_memory (this_frame, regnum,
++                                      cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM]);
++
++}
++if (regnum == MICROBLAZE_SP_REGNUM)
++        regnum = 1;
++#if 0
++
+   if (cache->frameless_p)
+     {
+       if (regnum == MICROBLAZE_PC_REGNUM)
+@@ -506,7 +536,9 @@ microblaze_frame_prev_register (frame_info_ptr this_frame,
+   else
+     return trad_frame_get_prev_register (this_frame, cache->saved_regs,
+                                         regnum);
+-
++#endif
++  return trad_frame_get_prev_register (this_frame, cache->saved_regs,
++                                       regnum); 
+ }
+ 
+ static const struct frame_unwind microblaze_frame_unwind =
+@@ -621,7 +653,106 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
+   return (type->length () == 16);
+ }
+ 
+-
++#if 1 
++static std::vector<CORE_ADDR>
++microblaze_software_single_step (struct regcache *regcache)
++{
++  struct gdbarch *arch = regcache->arch ();
++  //struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
++  static int le_breakp[] = MICROBLAZE_BREAKPOINT_LE;
++  static int be_breakp[] = MICROBLAZE_BREAKPOINT;
++  enum bfd_endian byte_order = gdbarch_byte_order (arch);
++  int *breakp = byte_order == BFD_ENDIAN_BIG ? be_breakp : le_breakp;
++//  std::vector<CORE_ADDR> ret = NULL;
++
++ /* Save the address and the values of the next_pc and the target */
++  static struct sstep_breaks
++  {
++    CORE_ADDR address;
++    bfd_boolean valid;
++    /* Shadow contents.  */
++    char data[INST_WORD_SIZE];
++  } stepbreaks[2];
++ int ii;
++
++      CORE_ADDR pc;
++      std::vector<CORE_ADDR> next_pcs;
++      long insn;
++      enum microblaze_instr minstr;
++      bfd_boolean isunsignednum;
++      enum microblaze_instr_type insn_type;
++      short delay_slots;
++      int imm;
++      bfd_boolean immfound = FALSE;
++
++     /* Set a breakpoint at the next instruction */
++      /* If the current instruction is an imm, set it at the inst after */
++      /* If the instruction has a delay slot, skip the delay slot */
++      pc = regcache_read_pc (regcache);
++      insn = microblaze_fetch_instruction (pc);
++      minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
++      if (insn_type == immediate_inst)
++       {
++         int rd, ra, rb;
++         immfound = TRUE;
++         minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
++         pc = pc + INST_WORD_SIZE;
++         insn = microblaze_fetch_instruction (pc);
++         minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
++       }
++      stepbreaks[0].address = pc + (delay_slots * INST_WORD_SIZE) + INST_WORD_SIZE;
++      if (insn_type != return_inst) {
++       stepbreaks[0].valid = TRUE;
++      } else {
++       stepbreaks[0].valid = FALSE;
++      }
++
++      microblaze_debug ("single-step insn_type=%x insn=%x\n", insn_type, insn);
++      /* Now check for branch or return instructions */
++      if (insn_type == branch_inst || insn_type == return_inst) {
++       int limm;
++       int lrd, lra, lrb;
++       int ra, rb;
++       bfd_boolean targetvalid;
++       bfd_boolean unconditionalbranch;
++       microblaze_decode_insn(insn, &lrd, &lra, &lrb, &limm);
++       if (lra >= 0 && lra < MICROBLAZE_NUM_REGS)
++         ra = regcache_raw_get_unsigned(regcache, lra);
++       else
++         ra = 0;
++       if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS)
++         rb = regcache_raw_get_unsigned(regcache, lrb);
++       else
++         rb = 0;
++       stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch);
++        microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address);
++       if (unconditionalbranch)
++         stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */
++       if (targetvalid && (stepbreaks[0].valid == FALSE ||
++                           (stepbreaks[0].address != stepbreaks[1].address))
++                       && (stepbreaks[1].address != pc)) {
++         stepbreaks[1].valid = TRUE;
++       } else {
++         stepbreaks[1].valid = FALSE;
++       }
++      } else {
++       stepbreaks[1].valid = FALSE;
++      }
++
++      /* Insert the breakpoints */
++      for (ii = 0; ii < 2; ++ii)
++        {
++
++          /* ignore invalid breakpoint. */
++          if (stepbreaks[ii].valid) {
++           // VEC_safe_push (CORE_ADDR, next_pcs, stepbreaks[ii].address);;
++            next_pcs.push_back (stepbreaks[ii].address);
++         }
++       }
++    return next_pcs;
++}
++#endif
++
+ static int dwarf2_to_reg_map[78] =
+ { 0  /* r0  */,   1  /* r1  */,   2  /* r2  */,   3  /* r3  */,  /*  0- 3 */
+   4  /* r4  */,   5  /* r5  */,   6  /* r6  */,   7  /* r7  */,  /*  4- 7 */
+@@ -788,6 +919,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+                                       microblaze_breakpoint::bp_from_kind);
+   set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
+ 
++  set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
++
+   set_gdbarch_frame_args_skip (gdbarch, 8);
+ 
+   set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc);
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 07a160a463c..c4c8098308f 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -60,11 +60,11 @@ enum microblaze_regnum
+   MICROBLAZE_R12_REGNUM,
+   MICROBLAZE_R13_REGNUM,
+   MICROBLAZE_R14_REGNUM,
+-  MICROBLAZE_R15_REGNUM,
++  MICROBLAZE_R15_REGNUM,MICROBLAZE_PREV_PC_REGNUM = MICROBLAZE_R15_REGNUM,
+   MICROBLAZE_R16_REGNUM,
+   MICROBLAZE_R17_REGNUM,
+   MICROBLAZE_R18_REGNUM,
+-  MICROBLAZE_R19_REGNUM,
++  MICROBLAZE_R19_REGNUM,MICROBLAZE_FP_REGNUM = MICROBLAZE_R19_REGNUM,
+   MICROBLAZE_R20_REGNUM,
+   MICROBLAZE_R21_REGNUM,
+   MICROBLAZE_R22_REGNUM,
+@@ -77,7 +77,8 @@ enum microblaze_regnum
+   MICROBLAZE_R29_REGNUM,
+   MICROBLAZE_R30_REGNUM,
+   MICROBLAZE_R31_REGNUM,
+-  MICROBLAZE_PC_REGNUM,
++  MICROBLAZE_MAX_GPR_REGS,
++  MICROBLAZE_PC_REGNUM=32,
+   MICROBLAZE_MSR_REGNUM,
+   MICROBLAZE_EAR_REGNUM,
+   MICROBLAZE_ESR_REGNUM,
+@@ -102,17 +103,21 @@ enum microblaze_regnum
+   MICROBLAZE_RTLBSX_REGNUM,
+   MICROBLAZE_RTLBLO_REGNUM,
+   MICROBLAZE_RTLBHI_REGNUM,
+-  MICROBLAZE_SLR_REGNUM, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_SLR_REGNUM,
++  MICROBLAZE_SLR_REGNUM,
+   MICROBLAZE_SHR_REGNUM,
+-  MICROBLAZE_NUM_REGS
++  MICROBLAZE_NUM_REGS, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_NUM_REGS
+ };
+ 
++/* Big enough to hold the size of the largest register in bytes.  */
++#define MICROBLAZE_MAX_REGISTER_SIZE   64
++
+ struct microblaze_frame_cache
+ {
+   /* Base address.  */
+   CORE_ADDR base;
+   CORE_ADDR pc;
+ 
++  CORE_ADDR saved_sp;
+   /* Do we have a frame?  */
+   int frameless_p;
+ 
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch
new file mode 100644
index 00000000..a61c17d9
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch
@@ -0,0 +1,1841 @@
+From ff4596845becf48fa17f06ea30a59658e9722e06 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 31 Jan 2019 14:36:00 +0530
+Subject: [PATCH 06/53] Adding 64 bit MB support Added new architecture to
+ Microblaze 64-bit support to GDB Signed-off-by :Nagaraju Mekala
+ <nmekala@xilix.com> Signed-off-by :Mahesh Bodapati <mbodapat@xilinx.com>
+
+Conflicts:
+        gdb/Makefile.in
+
+Conflicts:
+        bfd/cpu-microblaze.c
+        gdb/microblaze-tdep.c
+        ld/Makefile.am
+        ld/Makefile.in
+        opcodes/microblaze-dis.c
+
+Conflicts:
+        bfd/configure
+        gas/config/tc-microblaze.c
+        ld/Makefile.in
+        opcodes/microblaze-opcm.h
+
+Conflicts:
+        gdb/microblaze-tdep.c
+
+Conflicts:
+        bfd/elf32-microblaze.c
+        gas/config/tc-microblaze.c
+        gdb/features/Makefile
+        gdb/features/microblaze-with-stack-protect.c
+        gdb/microblaze-tdep.c
+        gdb/regformats/microblaze-with-stack-protect.dat
+        gdbserver/linux-microblaze-low.c
+        include/elf/common.h
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/Makefile.am                               |   2 +
+ bfd/Makefile.in                               |   3 +
+ bfd/archures.c                                |   2 +
+ bfd/bfd-in2.h                                 |  41 ++++-
+ bfd/config.bfd                                |   4 +
+ bfd/configure                                 |   2 +
+ bfd/cpu-microblaze.c                          |  55 +++++-
+ bfd/elf32-microblaze.c                        | 133 ++++++++++++--
+ bfd/libbfd.h                                  |   2 +
+ bfd/reloc.c                                   |  20 +++
+ bfd/targets.c                                 |   6 +
+ gdb/features/Makefile                         |   2 +
+ gdb/features/microblaze-core.xml              |   6 +-
+ gdb/features/microblaze-stack-protect.xml     |   4 +-
+ gdb/features/microblaze-with-stack-protect.c  |   8 +-
+ gdb/features/microblaze.c                     |   6 +-
+ gdb/features/microblaze64-core.xml            |  69 ++++++++
+ gdb/features/microblaze64-stack-protect.xml   |  12 ++
+ .../microblaze64-with-stack-protect.c         |  79 +++++++++
+ .../microblaze64-with-stack-protect.xml       |  12 ++
+ gdb/features/microblaze64.c                   |  77 +++++++++
+ gdb/features/microblaze64.xml                 |  11 ++
+ gdb/microblaze-linux-tdep.c                   |  36 +++-
+ gdb/microblaze-tdep.c                         | 125 ++++++++++----
+ gdb/microblaze-tdep.h                         |   4 +-
+ include/elf/common.h                          |   1 +
+ include/elf/microblaze.h                      |   2 +
+ opcodes/microblaze-dis.c                      |  52 +++---
+ opcodes/microblaze-opc.h                      | 162 ++++++++++++++++--
+ opcodes/microblaze-opcm.h                     |  24 ++-
+ 30 files changed, 853 insertions(+), 109 deletions(-)
+ create mode 100644 gdb/features/microblaze64-core.xml
+ create mode 100644 gdb/features/microblaze64-stack-protect.xml
+ create mode 100644 gdb/features/microblaze64-with-stack-protect.c
+ create mode 100644 gdb/features/microblaze64-with-stack-protect.xml
+ create mode 100644 gdb/features/microblaze64.c
+ create mode 100644 gdb/features/microblaze64.xml
+
+diff --git a/bfd/Makefile.am b/bfd/Makefile.am
+index 4f67b59585d..510f96439b7 100644
+--- a/bfd/Makefile.am
++++ b/bfd/Makefile.am
+@@ -568,6 +568,7 @@ BFD64_BACKENDS = \
+        elf64-ppc.lo \
+        elf64-riscv.lo \
+        elf64-s390.lo \
++       elf64-microblaze.lo \
+        elf64-sparc.lo \
+        elf64-tilegx.lo \
+        elf64-x86-64.lo \
+@@ -617,6 +618,7 @@ BFD64_BACKENDS_CFILES = \
+        elf64-nfp.c \
+        elf64-ppc.c \
+        elf64-s390.c \
++       elf64-microblaze.c \
+        elf64-sparc.c \
+        elf64-tilegx.c \
+        elf64-x86-64.c \
+diff --git a/bfd/Makefile.in b/bfd/Makefile.in
+index faaa0c424b8..71982d9f729 100644
+--- a/bfd/Makefile.in
++++ b/bfd/Makefile.in
+@@ -1036,6 +1036,7 @@ BFD64_BACKENDS = \
+        elf64-ppc.lo \
+        elf64-riscv.lo \
+        elf64-s390.lo \
++       elf64-microblaze.lo \
+        elf64-sparc.lo \
+        elf64-tilegx.lo \
+        elf64-x86-64.lo \
+@@ -1085,6 +1086,7 @@ BFD64_BACKENDS_CFILES = \
+        elf64-nfp.c \
+        elf64-ppc.c \
+        elf64-s390.c \
++       elf64-microblaze.c \
+        elf64-sparc.c \
+        elf64-tilegx.c \
+        elf64-x86-64.c \
+@@ -1661,6 +1663,7 @@ distclean-compile:
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ppc.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-riscv.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-s390.Plo@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-microblaze.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sparc.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-tilegx.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-x86-64.Plo@am__quote@
+diff --git a/bfd/archures.c b/bfd/archures.c
+index 94118b8d2cf..b9db26627ea 100644
+--- a/bfd/archures.c
++++ b/bfd/archures.c
+@@ -515,6 +515,8 @@ DESCRIPTION
+ .  bfd_arch_lm32,      {* Lattice Mico32.  *}
+ .#define bfd_mach_lm32         1
+ .  bfd_arch_microblaze,{* Xilinx MicroBlaze.  *}
++.#define bfd_mach_microblaze   1
++.#define bfd_mach_microblaze64 2
+ .  bfd_arch_kvx,        {* Kalray VLIW core of the MPPA processor family *}
+ .#define bfd_mach_kv3_unknown       0
+ .#define bfd_mach_kv3_1             1
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 581d8fe0b3e..7ccc155394d 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -1771,6 +1771,8 @@ enum bfd_architecture
+   bfd_arch_lm32,      /* Lattice Mico32.  */
+ #define bfd_mach_lm32          1
+   bfd_arch_microblaze,/* Xilinx MicroBlaze.  */
++#define bfd_mach_microblaze    1
++#define bfd_mach_microblaze64  2
+   bfd_arch_kvx,        /* Kalray VLIW core of the MPPA processor family */
+ #define bfd_mach_kv3_unknown       0
+ #define bfd_mach_kv3_1             1
+@@ -6444,23 +6446,44 @@ enum bfd_reloc_code_real
+      the form "Symbol Op Symbol".  */
+   BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
+ 
+-  /* This is a 32 bit reloc that stores the 32 bit pc relative value in
+-     two words (with an imm instruction).  No relocation is done here -
+-     only used for relaxing.  */
++/* This is a 32 bit reloc that stores the 32 bit pc relative
++value in two words (with an imm instruction).  No relocation is
++done here - only used for relaxing  */
+   BFD_RELOC_MICROBLAZE_32_NONE,
+ 
+-  /* This is a 64 bit reloc that stores the 32 bit pc relative value in
+-     two words (with an imm instruction).  No relocation is done here -
+-     only used for relaxing.  */
+-  BFD_RELOC_MICROBLAZE_64_NONE,
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++ *  +value in two words (with an imml instruction).  No relocation is
++ *   +done here - only used for relaxing  */
++    BFD_RELOC_MICROBLAZE_64_PCREL,
++
++/* This is a 64 bit reloc that stores the 32 bit relative
++ *  +value in two words (with an imml instruction).  No relocation is
++ *   +done here - only used for relaxing  */
++    BFD_RELOC_MICROBLAZE_64,
++
++/* This is a 64 bit reloc that stores the 32 bit relative
++ *  +value in two words (with an imml instruction).  No relocation is
++ *   +done here - only used for relaxing  */
++    BFD_RELOC_MICROBLAZE_EA64,
++
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++ *  +value in two words (with an imm instruction).  No relocation is
++ *   +done here - only used for relaxing  */
++    BFD_RELOC_MICROBLAZE_64_NONE,
+ 
+   /* This is a 64 bit reloc that stores the 32 bit pc relative value in
+      two words (with an imm instruction).  The relocation is PC-relative
+      GOT offset.  */
+   BFD_RELOC_MICROBLAZE_64_GOTPC,
+ 
+-  /* This is a 64 bit reloc that stores the 32 bit pc relative value in
+-     two words (with an imm instruction).  The relocation is GOT offset.  */
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++value in two words (with an imml instruction).  The relocation is
++PC-relative GOT offset  */
++  BFD_RELOC_MICROBLAZE_64_GPC,
++
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++value in two words (with an imm instruction).  The relocation is
++GOT offset  */
+   BFD_RELOC_MICROBLAZE_64_GOT,
+ 
+   /* This is a 64 bit reloc that stores the 32 bit pc relative value in
+diff --git a/bfd/config.bfd b/bfd/config.bfd
+index bbf12447517..cbba305354f 100644
+--- a/bfd/config.bfd
++++ b/bfd/config.bfd
+@@ -884,11 +884,15 @@ case "${targ}" in
+   microblazeel*-*)
+     targ_defvec=microblaze_elf32_le_vec
+     targ_selvecs=microblaze_elf32_vec
++    targ64_selvecs=microblaze_elf64_vec
++    targ64_selvecs=microblaze_elf64_le_vec
+     ;;
+ 
+   microblaze*-*)
+     targ_defvec=microblaze_elf32_vec
+     targ_selvecs=microblaze_elf32_le_vec
++    targ64_selvecs=microblaze_elf64_vec
++    targ64_selvecs=microblaze_elf64_le_vec
+     ;;
+ 
+ #ifdef BFD64
+diff --git a/bfd/configure b/bfd/configure
+index 5618c5d3217..3c5b58c33b4 100755
+--- a/bfd/configure
++++ b/bfd/configure
+@@ -16016,6 +16016,8 @@ do
+     rx_elf32_linux_le_vec)      tb="$tb elf32-rx.lo elf32.lo $elf" ;;
+     s390_elf32_vec)             tb="$tb elf32-s390.lo elf32.lo $elf" ;;
+     s390_elf64_vec)             tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;;
++    microblaze_elf64_vec)       tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
++    microblaze_elf64_le_vec)    tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
+     score_elf32_be_vec)                 tb="$tb elf32-score.lo elf32-score7.lo elf32.lo elf64.lo $elf"; want64=true; target_size=64 ;;
+     score_elf32_le_vec)                 tb="$tb elf32-score.lo elf32-score7.lo elf32.lo elf64.lo $elf"; want64=true; target_size=64 ;;
+     sh_coff_vec)                tb="$tb coff-sh.lo $coff" ;;
+diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c
+index a7af3a17237..caf4fb66826 100644
+--- a/bfd/cpu-microblaze.c
++++ b/bfd/cpu-microblaze.c
+@@ -23,13 +23,30 @@
+ #include "bfd.h"
+ #include "libbfd.h"
+ 
+-const bfd_arch_info_type bfd_microblaze_arch =
++const bfd_arch_info_type bfd_microblaze_arch[] =
++{
++#if BFD_DEFAULT_TARGET_SIZE == 64
++{
++  64,                          /* 32 bits in a word.  */
++  64,                          /* 32 bits in an address.  */
++  8,                           /* 8 bits in a byte.  */
++  bfd_arch_microblaze,         /* Architecture.  */
++  bfd_mach_microblaze64,       /* 64 bit Machine */
++  "microblaze",                        /* Architecture name.  */
++  "MicroBlaze",                        /* Printable name.  */
++  3,                           /* Section align power.  */
++  false,                               /* Is this the default architecture ?  */
++  bfd_default_compatible,      /* Architecture comparison function.  */
++  bfd_default_scan,            /* String to architecture conversion.  */
++  bfd_arch_default_fill,       /* Default fill.  */
++  &bfd_microblaze_arch[1]      /* Next in list.  */
++},
+ {
+   32,                          /* Bits in a word.  */
+   32,                          /* Bits in an address.  */
+   8,                           /* Bits in a byte.  */
+   bfd_arch_microblaze,         /* Architecture number.  */
+-  0,                           /* Machine number - 0 for now.  */
++  bfd_mach_microblaze,         /* Machine number - 0 for now.  */
+   "microblaze",                        /* Architecture name.  */
+   "MicroBlaze",                        /* Printable name.  */
+   3,                           /* Section align power.  */
+@@ -39,4 +56,38 @@ const bfd_arch_info_type bfd_microblaze_arch =
+   bfd_arch_default_fill,       /* Default fill.  */
+   NULL,                                /* Next in list.  */
+   0 /* Maximum offset of a reloc from the start of an insn.  */
++}
++#else
++{
++  32,                          /* 32 bits in a word.  */
++  32,                          /* 32 bits in an address.  */
++  8,                           /* 8 bits in a byte.  */
++  bfd_arch_microblaze,                 /* Architecture.  */
++  bfd_mach_microblaze,         /* 32 bit Machine */
++  "microblaze",                        /* Architecture name.  */
++  "MicroBlaze",                        /* Printable name.  */
++  3,                           /* Section align power.  */
++  true,                                /* Is this the default architecture ?  */
++  bfd_default_compatible,      /* Architecture comparison function.  */
++  bfd_default_scan,            /* String to architecture conversion.  */
++  bfd_arch_default_fill,       /* Default fill.  */
++  &bfd_microblaze_arch[1]      /* Next in list.  */
++},
++{
++  64,                          /* 32 bits in a word.  */
++  64,                          /* 32 bits in an address.  */
++  8,                           /* 8 bits in a byte.  */
++  bfd_arch_microblaze,         /* Architecture.  */
++  bfd_mach_microblaze64,       /* 64 bit Machine */
++  "microblaze",                        /* Architecture name.  */
++  "MicroBlaze",                        /* Printable name.  */
++  3,                           /* Section align power.  */
++  false,                               /* Is this the default architecture ?  */
++  bfd_default_compatible,      /* Architecture comparison function.  */
++  bfd_default_scan,            /* String to architecture conversion.  */
++  bfd_arch_default_fill,       /* Default fill.  */
++  NULL,                                /* Next in list.  */
++  0
++}
++#endif
+ };
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 022ce365c59..7e7c4bf471d 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -114,6 +114,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+          0x0000ffff,           /* Dest Mask.  */
+          true),                /* PC relative offset?  */
+ 
++   HOWTO (R_MICROBLAZE_IMML_64,        /* Type.  */
++          0,                   /* Rightshift.  */
++          2,                   /* Size (0 = byte, 1 = short, 2 = long).  */
++          16,                  /* Bitsize.  */
++          true,                /* PC_relative.  */
++          0,                   /* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_IMML_64",      /* Name.  */
++          false,               /* Partial Inplace.  */
++          0,                   /* Source Mask.  */
++          0x0000ffff,          /* Dest Mask.  */
++          false),              /* PC relative offset?  */
++
+    /* A 64 bit relocation.  Table entry not really used.  */
+    HOWTO (R_MICROBLAZE_64,     /* Type.  */
+          0,                    /* Rightshift.  */
+@@ -279,6 +293,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+          0x0000ffff,           /* Dest Mask.  */
+          true),                /* PC relative offset?  */
+ 
++   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GPC_64,         /* Type.  */
++          0,                   /* Rightshift.  */
++          2,                   /* Size (0 = byte, 1 = short, 2 = long).  */
++          16,                  /* Bitsize.  */
++          true,                        /* PC_relative.  */
++          0,                   /* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,       /* Special Function.  */
++          "R_MICROBLAZE_GPC_64",       /* Name.  */
++          false,               /* Partial Inplace.  */
++          0,                   /* Source Mask.  */
++          0x0000ffff,          /* Dest Mask.  */
++          true),               /* PC relative offset?  */
++
+    /* A 64 bit GOT relocation.  Table-entry not really used.  */
+    HOWTO (R_MICROBLAZE_GOT_64,  /* Type.  */
+          0,                    /* Rightshift.  */
+@@ -618,9 +647,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+     case BFD_RELOC_VTABLE_ENTRY:
+       microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
+       break;
++    case BFD_RELOC_MICROBLAZE_64:
++      microblaze_reloc = R_MICROBLAZE_IMML_64;
++      break;
+     case BFD_RELOC_MICROBLAZE_64_GOTPC:
+       microblaze_reloc = R_MICROBLAZE_GOTPC_64;
+       break;
++    case BFD_RELOC_MICROBLAZE_64_GPC:
++      microblaze_reloc = R_MICROBLAZE_GPC_64;
++      break;
+     case BFD_RELOC_MICROBLAZE_64_GOT:
+       microblaze_reloc = R_MICROBLAZE_GOT_64;
+       break;
+@@ -1582,7 +1617,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+                if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0)
+                  {
+                    relocation += addend;
+-                   if (r_type == R_MICROBLAZE_32)
++                   if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64)
+                      bfd_put_32 (input_bfd, relocation, contents + offset);
+                    else
+                      {
+@@ -1987,8 +2022,7 @@ microblaze_elf_relax_section (bfd *abfd,
+       else
+        symval += irel->r_addend;
+ 
+-      if ((symval & 0xffff8000) == 0
+-         || (symval & 0xffff8000) == 0xffff8000)
++      if ((symval & 0xffff8000) == 0)
+        {
+          /* We can delete this instruction.  */
+          sdata->relax[sdata->relax_count].addr = irel->r_offset;
+@@ -2052,16 +2086,45 @@ microblaze_elf_relax_section (bfd *abfd,
+                    irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
+                }
+              break;
++           case R_MICROBLAZE_IMML_64:
++             {
++               /* This was a PC-relative instruction that was
++                  completely resolved.  */
++               int sfix, efix;
++            unsigned int val;
++               bfd_vma target_address;
++               target_address = irel->r_addend + irel->r_offset;
++               sfix = calc_fixup (irel->r_offset, 0, sec);
++               efix = calc_fixup (target_address, 0, sec);
++
++            /* Validate the in-band val.  */
++            val = bfd_get_32 (abfd, contents + irel->r_offset);
++            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++            }
++               irel->r_addend -= (efix - sfix);
++               /* Should use HOWTO.  */
++               microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
++                                                  irel->r_addend);
++             }
++             break;
+            case R_MICROBLAZE_NONE:
+            case R_MICROBLAZE_32_NONE:
+              {
+                /* This was a PC-relative instruction that was
+                   completely resolved.  */
+                size_t sfix, efix;
++               unsigned int val;
+                bfd_vma target_address;
+                target_address = irel->r_addend + irel->r_offset;
+                sfix = calc_fixup (irel->r_offset, 0, sec);
+                efix = calc_fixup (target_address, 0, sec);
++
++               /* Validate the in-band val.  */
++               val = bfd_get_32 (abfd, contents + irel->r_offset);
++               if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++                      fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++               }
+                irel->r_addend -= (efix - sfix);
+                /* Should use HOWTO.  */
+                microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
+@@ -2078,8 +2141,8 @@ microblaze_elf_relax_section (bfd *abfd,
+                sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec);
+                efix = calc_fixup (target_address, 0, sec);
+                irel->r_addend -= (efix - sfix);
+-    microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset
+-                                      + INST_WORD_SIZE, irel->r_addend);
++    microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
++                                       irel->r_addend);
+              }
+              break;
+            }
+@@ -2109,10 +2172,50 @@ microblaze_elf_relax_section (bfd *abfd,
+          irelscanend = irelocs + o->reloc_count;
+          for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+            {
+-             if ((ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+-                 || (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE))
+-               {
+-                 isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++             if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
++                {
++                  unsigned int val;
++
++                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++
++                  /* hax: We only do the following fixup for debug location lists.  */
++                  if (strcmp(".debug_loc", o->name))
++                    continue;
++
++                  /* This was a PC-relative instruction that was completely resolved.  */
++                  if (ocontents == NULL)
++                    {
++                      if (elf_section_data (o)->this_hdr.contents != NULL)
++                          ocontents = elf_section_data (o)->this_hdr.contents;
++                      else
++                        {
++                          /* We always cache the section contents.
++                             Perhaps, if info->keep_memory is FALSE, we
++                             should free them, if we are permitted to.  */
++
++                          if (o->rawsize == 0)
++                              o->rawsize = o->size;
++                          ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++                          if (ocontents == NULL)
++                              goto error_return;
++                          if (!bfd_get_section_contents (abfd, o, ocontents,
++                                                         (file_ptr) 0,
++                                                         o->rawsize))
++                              goto error_return;
++                         elf_section_data (o)->this_hdr.contents = ocontents;
++                       }
++                   }
++                  val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++                  if (val != irelscan->r_addend) {
++                    fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
++                  }
++                  irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
++                  microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++                                                     irelscan->r_addend);
++              }
++              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)// || ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64)
++                {
++                 isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+                  /* Look at the reloc only if the value has been resolved.  */
+                  if (isym->st_shndx == shndx
+@@ -3510,6 +3613,14 @@ microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
+   return true;
+ }
+ 
++
++static bool
++elf_microblaze_object_p (bfd *abfd)
++{
++  /* Set the right machine number for an s390 elf32 file.  */
++  return bfd_default_set_arch_mach (abfd, bfd_arch_microblaze, bfd_mach_microblaze);
++}
++
+ /* Hook called by the linker routine which adds symbols from an object
+    file.  We use it to put .comm items in .sbss, and not .bss.  */
+ 
+@@ -3580,8 +3691,6 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
+ #define elf_backend_finish_dynamic_symbol      microblaze_elf_finish_dynamic_symbol
+ #define elf_backend_size_dynamic_sections      microblaze_elf_size_dynamic_sections
+ #define elf_backend_add_symbol_hook            microblaze_elf_add_symbol_hook
+-
+-#define elf_backend_grok_prstatus               microblaze_elf_grok_prstatus
+-#define elf_backend_grok_psinfo                 microblaze_elf_grok_psinfo
++#define elf_backend_object_p                   elf_microblaze_object_p
+ 
+ #include "elf32-target.h"
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index ebd4f24149b..7a3e558d70a 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -3011,6 +3011,8 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
+   "BFD_RELOC_MICROBLAZE_32_GOTOFF",
+   "BFD_RELOC_MICROBLAZE_COPY",
++  "BFD_RELOC_MICROBLAZE_64",
++  "BFD_RELOC_MICROBLAZE_64_PCREL",
+   "BFD_RELOC_MICROBLAZE_64_TLS",
+   "BFD_RELOC_MICROBLAZE_64_TLSGD",
+   "BFD_RELOC_MICROBLAZE_64_TLSLD",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index e74cbd75e96..fda67e5ffda 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6665,6 +6665,12 @@ ENUMDOC
+   This is a 32 bit reloc that stores the 32 bit pc relative value in
+   two words (with an imm instruction).  No relocation is done here -
+   only used for relaxing.
++ENUM
++  BFD_RELOC_MICROBLAZE_32_NONE
++ENUMDOC
++  This is a 32 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imm instruction).  No relocation is
++  done here - only used for relaxing
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
+@@ -7886,6 +7892,20 @@ ENUMX
+ ENUMDOC
+   Tilera TILE-Gx Relocations.
+ 
++  This is a 64 bit reloc that stores 64-bit thread pointer relative offset
++  to two words (uses imml instruction).
++ENUM
++BFD_RELOC_MICROBLAZE_64,
++ENUMDOC
++ This is a 64 bit reloc that stores the 64 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
++ENUM
++BFD_RELOC_MICROBLAZE_64_PCREL,
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
+ ENUM
+   BFD_RELOC_BPF_64
+ ENUMX
+diff --git a/bfd/targets.c b/bfd/targets.c
+index 3addf2fe373..a9a9b975c82 100644
+--- a/bfd/targets.c
++++ b/bfd/targets.c
+@@ -799,6 +799,8 @@ extern const bfd_target mep_elf32_le_vec;
+ extern const bfd_target metag_elf32_vec;
+ extern const bfd_target microblaze_elf32_vec;
+ extern const bfd_target microblaze_elf32_le_vec;
++extern const bfd_target microblaze_elf64_vec;
++extern const bfd_target microblaze_elf64_le_vec;
+ extern const bfd_target mips_ecoff_be_vec;
+ extern const bfd_target mips_ecoff_le_vec;
+ extern const bfd_target mips_ecoff_bele_vec;
+@@ -1167,6 +1169,10 @@ static const bfd_target * const _bfd_target_vector[] =
+ 
+        &metag_elf32_vec,
+ 
++#ifdef BFD64
++       &microblaze_elf64_vec,
++       &microblaze_elf64_le_vec,
++#endif
+        &microblaze_elf32_vec,
+ 
+        &mips_ecoff_be_vec,
+diff --git a/gdb/features/Makefile b/gdb/features/Makefile
+index 8ac30d8cea3..690f1e94570 100644
+--- a/gdb/features/Makefile
++++ b/gdb/features/Makefile
+@@ -102,7 +102,9 @@ OUTPUTS = $(patsubst %,$(outdir)/%.dat,$(WHICH))
+ # to make on the command line.
+ XMLTOC = \
+        microblaze-with-stack-protect.xml \
++       microblaze64-with-stack-protect.xml \
+        microblaze.xml \
++       microblaze64.xml \
+        mips-dsp-linux.xml \
+        mips-linux.xml \
+        mips64-dsp-linux.xml \
+diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml
+index d1d7d538461..4d77d9d898f 100644
+--- a/gdb/features/microblaze-core.xml
++++ b/gdb/features/microblaze-core.xml
+@@ -8,7 +8,7 @@
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze.core">
+   <reg name="r0" bitsize="32" regnum="0"/>
+-  <reg name="r1" bitsize="32" type="data_ptr"/>
++  <reg name="r1" bitsize="32"/>
+   <reg name="r2" bitsize="32"/>
+   <reg name="r3" bitsize="32"/>
+   <reg name="r4" bitsize="32"/>
+@@ -39,7 +39,7 @@
+   <reg name="r29" bitsize="32"/>
+   <reg name="r30" bitsize="32"/>
+   <reg name="r31" bitsize="32"/>
+-  <reg name="rpc" bitsize="32" type="code_ptr"/>
++  <reg name="rpc" bitsize="32"/>
+   <reg name="rmsr" bitsize="32"/>
+   <reg name="rear" bitsize="32"/>
+   <reg name="resr" bitsize="32"/>
+@@ -64,4 +64,6 @@
+   <reg name="rtlbsx" bitsize="32"/>
+   <reg name="rtlblo" bitsize="32"/>
+   <reg name="rtlbhi" bitsize="32"/>
++  <reg name="slr" bitsize="32"/>
++  <reg name="shr" bitsize="32"/>
+ </feature>
+diff --git a/gdb/features/microblaze-stack-protect.xml b/gdb/features/microblaze-stack-protect.xml
+index b5f68403bd5..013240ce798 100644
+--- a/gdb/features/microblaze-stack-protect.xml
++++ b/gdb/features/microblaze-stack-protect.xml
+@@ -7,6 +7,6 @@
+ 
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze.stack-protect">
+-  <reg name="rslr" bitsize="32"/>
+-  <reg name="rshr" bitsize="32"/>
++  <reg name="slr" bitsize="32"/>
++  <reg name="shr" bitsize="32"/>
+ </feature>
+diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c
+index 574dc02db67..8ab9565a047 100644
+--- a/gdb/features/microblaze-with-stack-protect.c
++++ b/gdb/features/microblaze-with-stack-protect.c
+@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+ 
+   feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core");
+   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
+@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
+@@ -72,8 +72,8 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+ 
+   feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.stack-protect");
+-  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int");
+ 
+   tdesc_microblaze_with_stack_protect = result.release ();
+ }
+diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c
+index 8f1fb0a142f..ed12e5bcfd2 100644
+--- a/gdb/features/microblaze.c
++++ b/gdb/features/microblaze.c
+@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void)
+ 
+   feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core");
+   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
+@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void)
+   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
+@@ -70,6 +70,8 @@ initialize_tdesc_microblaze (void)
+   tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
+ 
+   tdesc_microblaze = result.release ();
+ }
+diff --git a/gdb/features/microblaze64-core.xml b/gdb/features/microblaze64-core.xml
+new file mode 100644
+index 00000000000..96e99e2fb24
+--- /dev/null
++++ b/gdb/features/microblaze64-core.xml
+@@ -0,0 +1,69 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.microblaze64.core">
++  <reg name="r0" bitsize="64" regnum="0"/>
++  <reg name="r1" bitsize="64"/>
++  <reg name="r2" bitsize="64"/>
++  <reg name="r3" bitsize="64"/>
++  <reg name="r4" bitsize="64"/>
++  <reg name="r5" bitsize="64"/>
++  <reg name="r6" bitsize="64"/>
++  <reg name="r7" bitsize="64"/>
++  <reg name="r8" bitsize="64"/>
++  <reg name="r9" bitsize="64"/>
++  <reg name="r10" bitsize="64"/>
++  <reg name="r11" bitsize="64"/>
++  <reg name="r12" bitsize="64"/>
++  <reg name="r13" bitsize="64"/>
++  <reg name="r14" bitsize="64"/>
++  <reg name="r15" bitsize="64"/>
++  <reg name="r16" bitsize="64"/>
++  <reg name="r17" bitsize="64"/>
++  <reg name="r18" bitsize="64"/>
++  <reg name="r19" bitsize="64"/>
++  <reg name="r20" bitsize="64"/>
++  <reg name="r21" bitsize="64"/>
++  <reg name="r22" bitsize="64"/>
++  <reg name="r23" bitsize="64"/>
++  <reg name="r24" bitsize="64"/>
++  <reg name="r25" bitsize="64"/>
++  <reg name="r26" bitsize="64"/>
++  <reg name="r27" bitsize="64"/>
++  <reg name="r28" bitsize="64"/>
++  <reg name="r29" bitsize="64"/>
++  <reg name="r30" bitsize="64"/>
++  <reg name="r31" bitsize="64"/>
++  <reg name="rpc" bitsize="64"/>
++  <reg name="rmsr" bitsize="32"/>
++  <reg name="rear" bitsize="64"/>
++  <reg name="resr" bitsize="32"/>
++  <reg name="rfsr" bitsize="32"/>
++  <reg name="rbtr" bitsize="64"/>
++  <reg name="rpvr0" bitsize="32"/>
++  <reg name="rpvr1" bitsize="32"/>
++  <reg name="rpvr2" bitsize="32"/>
++  <reg name="rpvr3" bitsize="32"/>
++  <reg name="rpvr4" bitsize="32"/>
++  <reg name="rpvr5" bitsize="32"/>
++  <reg name="rpvr6" bitsize="32"/>
++  <reg name="rpvr7" bitsize="32"/>
++  <reg name="rpvr8" bitsize="64"/>
++  <reg name="rpvr9" bitsize="64"/>
++  <reg name="rpvr10" bitsize="32"/>
++  <reg name="rpvr11" bitsize="32"/>
++  <reg name="redr" bitsize="32"/>
++  <reg name="rpid" bitsize="32"/>
++  <reg name="rzpr" bitsize="32"/>
++  <reg name="rtlbx" bitsize="32"/>
++  <reg name="rtlbsx" bitsize="32"/>
++  <reg name="rtlblo" bitsize="32"/>
++  <reg name="rtlbhi" bitsize="32"/>
++  <reg name="slr" bitsize="64"/>
++  <reg name="shr" bitsize="64"/>
++</feature>
+diff --git a/gdb/features/microblaze64-stack-protect.xml b/gdb/features/microblaze64-stack-protect.xml
+new file mode 100644
+index 00000000000..1bbf5fc3cea
+--- /dev/null
++++ b/gdb/features/microblaze64-stack-protect.xml
+@@ -0,0 +1,12 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.microblaze64.stack-protect">
++  <reg name="slr" bitsize="64"/>
++  <reg name="shr" bitsize="64"/>
++</feature>
+diff --git a/gdb/features/microblaze64-with-stack-protect.c b/gdb/features/microblaze64-with-stack-protect.c
+new file mode 100644
+index 00000000000..a4de4666c76
+--- /dev/null
++++ b/gdb/features/microblaze64-with-stack-protect.c
+@@ -0,0 +1,79 @@
++/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
++  Original: microblaze-with-stack-protect.xml */
++
++#include "defs.h"
++#include "osabi.h"
++#include "target-descriptions.h"
++
++struct target_desc *tdesc_microblaze64_with_stack_protect;
++static void
++initialize_tdesc_microblaze64_with_stack_protect (void)
++{
++  target_desc_up result = allocate_target_description ();
++  struct tdesc_feature *feature;
++
++  feature = tdesc_create_feature (result.get() , "org.gnu.gdb.microblaze64.core");
++  tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "int");
++  tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++
++  feature = tdesc_create_feature (result.get(), "org.gnu.gdb.microblaze64.stack-protect");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++
++  tdesc_microblaze64_with_stack_protect = result.release();
++}
+diff --git a/gdb/features/microblaze64-with-stack-protect.xml b/gdb/features/microblaze64-with-stack-protect.xml
+new file mode 100644
+index 00000000000..0e9f01611f3
+--- /dev/null
++++ b/gdb/features/microblaze64-with-stack-protect.xml
+@@ -0,0 +1,12 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++  <xi:include href="microblaze64-core.xml"/>
++  <xi:include href="microblaze64-stack-protect.xml"/>
++</target>
+diff --git a/gdb/features/microblaze64.c b/gdb/features/microblaze64.c
+new file mode 100644
+index 00000000000..8ab7a90dd95
+--- /dev/null
++++ b/gdb/features/microblaze64.c
+@@ -0,0 +1,77 @@
++/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
++  Original: microblaze.xml */
++
++#include "defs.h"
++#include "osabi.h"
++#include "target-descriptions.h"
++
++struct target_desc *tdesc_microblaze64;
++static void
++initialize_tdesc_microblaze64 (void)
++{
++  target_desc_up result = allocate_target_description ();
++  struct tdesc_feature *feature;
++
++  feature = tdesc_create_feature (result.get(), "org.gnu.gdb.microblaze64.core");
++  tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++
++  tdesc_microblaze64 = result.release();
++}
+diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml
+new file mode 100644
+index 00000000000..515d18e65cf
+--- /dev/null
++++ b/gdb/features/microblaze64.xml
+@@ -0,0 +1,11 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++  <xi:include href="microblaze64-core.xml"/>
++</target>
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index d086debc4f8..f34b0fa9fd4 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -40,6 +40,7 @@
+ #include "features/microblaze-linux.c"
+ 
+ static int microblaze_debug_flag = 0;
++int MICROBLAZE_REGISTER_SIZE=4;
+ 
+ static void
+ microblaze_debug (const char *fmt, ...)
+@@ -55,6 +56,7 @@ microblaze_debug (const char *fmt, ...)
+     }
+ }
+ 
++#if 0
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, 
+                                           struct bp_target_info *bp_tgt)
+@@ -86,6 +88,8 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+   return val;
+ }
+ 
++#endif
++
+ static void
+ microblaze_linux_sigtramp_cache (frame_info_ptr next_frame,
+                                 struct trad_frame_cache *this_cache,
+@@ -147,8 +151,8 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ 
+   linux_init_abi (info, gdbarch, 0);
+ 
+-  set_gdbarch_memory_remove_breakpoint (gdbarch,
+-                                       microblaze_linux_memory_remove_breakpoint);
++ // set_gdbarch_memory_remove_breakpoint (gdbarch,
++ //                                    microblaze_linux_memory_remove_breakpoint);
+ 
+   /* Shared library handling.  */
+   set_solib_svr4_fetch_link_map_offsets (gdbarch,
+@@ -160,10 +164,30 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ 
+   /* BFD target for core files.  */
+   if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+-    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++    {
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
++          set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblaze");
++          MICROBLAZE_REGISTER_SIZE=8;
++        }
++      else
++        set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++    }
+   else
+-    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++    {
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
++          set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblazeel");
++          MICROBLAZE_REGISTER_SIZE=8;
++        }
++      else
++        set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++    }
+ 
++    switch (info.bfd_arch_info->mach)
++    {
++    case bfd_mach_microblaze64:
++      set_gdbarch_ptr_bit (gdbarch, 64);
++    break;
++    }
+ 
+   /* Shared library handling.  */
+   set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
+@@ -178,7 +202,9 @@ void _initialize_microblaze_linux_tdep ();
+ void
+ _initialize_microblaze_linux_tdep ()
+ {
+-  gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX, 
++  gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze, GDB_OSABI_LINUX, 
++                         microblaze_linux_init_abi);
++  gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze64, GDB_OSABI_LINUX, 
+                          microblaze_linux_init_abi);
+   initialize_tdesc_microblaze_linux ();
+ }
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index b0b4c1b2614..7cbbc8986a1 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -40,7 +40,9 @@
+ #include "remote.h"
+ 
+ #include "features/microblaze-with-stack-protect.c"
++#include "features/microblaze64-with-stack-protect.c"
+ #include "features/microblaze.c"
++#include "features/microblaze64.c"
+ 
+ /* Instruction macros used for analyzing the prologue.  */
+ /* This set of instruction macros need to be changed whenever the
+@@ -75,12 +77,13 @@ static const char * const microblaze_register_names[] =
+   "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6",
+   "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11",
+   "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi",
+-  "rslr", "rshr"
++  "slr", "shr"
+ };
+ 
+ #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
+ 
+ static unsigned int microblaze_debug_flag = 0;
++int reg_size = 4;
+ 
+ #define microblaze_debug(fmt, ...) \
+   debug_prefixed_printf_cond_nofunc (microblaze_debug_flag, "MICROBLAZE", \
+@@ -128,6 +131,15 @@ microblaze_fetch_instruction (CORE_ADDR pc)
+ constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
+ 
+ typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
++static CORE_ADDR
++microblaze_store_arguments (struct regcache *regcache, int nargs,
++                           struct value **args, CORE_ADDR sp,
++                           int struct_return, CORE_ADDR struct_addr)
++{
++  error (_("store_arguments not implemented"));
++  return sp;
++}
++#if 0
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+                                    struct bp_target_info *bp_tgt)
+@@ -146,7 +158,6 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+   /* Make sure we see the memory breakpoints.  */
+   scoped_restore restore_memory
+     = make_scoped_restore_show_memory_breakpoints (1);
+-
+   val = target_read_memory (addr, old_contents, bplen);
+ 
+   /* If our breakpoint is no longer at the address, this means that the
+@@ -161,6 +172,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+   return val;
+ }
+ 
++#endif
+ /* Allocate and initialize a frame cache.  */
+ 
+ static struct microblaze_frame_cache *
+@@ -583,11 +595,11 @@ microblaze_extract_return_value (struct type *type, struct regcache *regcache,
+     {
+       case 1:  /* return last byte in the register.  */
+        regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf);
+-       memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 1, 1);
++       memcpy(valbuf, buf + reg_size - 1, 1);
+        return;
+       case 2:  /* return last 2 bytes in register.  */
+        regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf);
+-       memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 2, 2);
++       memcpy(valbuf, buf + reg_size - 2, 2);
+        return;
+       case 4:  /* for sizes 4 or 8, copy the required length.  */
+       case 8:
+@@ -753,6 +765,12 @@ microblaze_software_single_step (struct regcache *regcache)
+ }
+ #endif
+ 
++static void
++microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc)
++{
++  regcache_cooked_write_unsigned (regcache, MICROBLAZE_PC_REGNUM, pc);
++}
++
+ static int dwarf2_to_reg_map[78] =
+ { 0  /* r0  */,   1  /* r1  */,   2  /* r2  */,   3  /* r3  */,  /*  0- 3 */
+   4  /* r4  */,   5  /* r5  */,   6  /* r6  */,   7  /* r7  */,  /*  4- 7 */
+@@ -787,13 +805,14 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
+ static void
+ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
+ {
++
+   register_remote_g_packet_guess (gdbarch,
+                                  4 * MICROBLAZE_NUM_CORE_REGS,
+-                                 tdesc_microblaze);
++                                 tdesc_microblaze64);
+ 
+   register_remote_g_packet_guess (gdbarch,
+                                  4 * MICROBLAZE_NUM_REGS,
+-                                 tdesc_microblaze_with_stack_protect);
++                                 tdesc_microblaze64_with_stack_protect);
+ }
+ 
+ void
+@@ -801,7 +820,7 @@ microblaze_supply_gregset (const struct regset *regset,
+                         struct regcache *regcache,
+                         int regnum, const void *gregs)
+ {
+-  const unsigned int *regs = (const unsigned int *)gregs;
++  const gdb_byte *regs = (const gdb_byte *) gregs;
+   if (regnum >= 0)
+     regcache->raw_supply (regnum, regs + regnum);
+ 
+@@ -809,7 +828,7 @@ microblaze_supply_gregset (const struct regset *regset,
+     int i;
+ 
+     for (i = 0; i < 50; i++) {
+-      regcache->raw_supply (i, regs + i);
++      regcache->raw_supply (regnum, regs + i);
+     }
+   }
+ }
+@@ -832,6 +851,17 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
+ }
+ 
+ 
++static void
++make_regs (struct gdbarch *arch)
++{
++  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
++  int mach = gdbarch_bfd_arch_info (arch)->mach;
++  
++  if (mach == bfd_mach_microblaze64)
++    {
++      set_gdbarch_ptr_bit (arch, 64);
++    }
++}
+ 
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+@@ -844,8 +874,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   if (arches != NULL)
+     return arches->gdbarch;
+   if (tdesc == NULL)
+-    tdesc = tdesc_microblaze;
+-
++    {
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) 
++        {
++         tdesc = tdesc_microblaze64;
++          reg_size = 8;
++       }
++      else
++       tdesc = tdesc_microblaze;
++    }
+   /* Check any target description for validity.  */
+   if (tdesc_has_registers (tdesc))
+     {
+@@ -853,31 +890,42 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+       int valid_p;
+       int i;
+ 
+-      feature = tdesc_find_feature (tdesc,
+-                                   "org.gnu.gdb.microblaze.core");
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++        feature = tdesc_find_feature (tdesc,
++                                    "org.gnu.gdb.microblaze64.core");
++      else
++        feature = tdesc_find_feature (tdesc,
++                                    "org.gnu.gdb.microblaze.core");
+       if (feature == NULL)
+        return NULL;
+       tdesc_data = tdesc_data_alloc ();
+ 
+       valid_p = 1;
+-      for (i = 0; i < MICROBLAZE_NUM_CORE_REGS; i++)
+-       valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i,
+-                                           microblaze_register_names[i]);
+-      feature = tdesc_find_feature (tdesc,
+-                                   "org.gnu.gdb.microblaze.stack-protect");
++      for (i = 0; i < MICROBLAZE_NUM_REGS; i++)
++        valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), i,
++                                            microblaze_register_names[i]);
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++        feature = tdesc_find_feature (tdesc,
++                                    "org.gnu.gdb.microblaze64.stack-protect");
++      else
++        feature = tdesc_find_feature (tdesc,
++                                    "org.gnu.gdb.microblaze.stack-protect");
+       if (feature != NULL)
+-       {
+-         valid_p = 1;
+-         valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+-                                             MICROBLAZE_SLR_REGNUM,
+-                                             "rslr");
+-         valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+-                                             MICROBLAZE_SHR_REGNUM,
+-                                             "rshr");
+-       }
++        {
++          valid_p = 1;
++          valid_p &= tdesc_numbered_register (feature, tdesc_data.get(),
++                                              MICROBLAZE_SLR_REGNUM,
++                                              "slr");
++          valid_p &= tdesc_numbered_register (feature, tdesc_data.get(),
++                                              MICROBLAZE_SHR_REGNUM,
++                                              "shr");
++        }
+ 
+       if (!valid_p)
+-       return NULL;
++        {
++         // tdesc_data_cleanup (tdesc_data.get ());
++          return NULL;
++        }
+     }
+ 
+   /* Allocate space for the new architecture.  */
+@@ -897,7 +945,17 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   /* Register numbers of various important registers.  */
+   set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM); 
+   set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM); 
++  
++  /* Register set.  
++  make_regs (gdbarch); */
++  switch (info.bfd_arch_info->mach)
++    {
++    case bfd_mach_microblaze64:
++      set_gdbarch_ptr_bit (gdbarch, 64);
++    break;
++    }
+ 
++  
+   /* Map Dwarf2 registers to GDB registers.  */
+   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum);
+ 
+@@ -917,7 +975,9 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+                                       microblaze_breakpoint::kind_from_pc);
+   set_gdbarch_sw_breakpoint_from_kind (gdbarch,
+                                       microblaze_breakpoint::bp_from_kind);
+-  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
++//  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
++
++//  set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+ 
+   set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+ 
+@@ -925,7 +985,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ 
+   set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc);
+ 
+-  microblaze_register_g_packet_guesses (gdbarch);
++  //microblaze_register_g_packet_guesses (gdbarch);
+ 
+   frame_base_set_default (gdbarch, &microblaze_frame_base);
+ 
+@@ -940,12 +1000,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+     tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data));
+   //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer);
+ 
+-  /* If we have register sets, enable the generic core file support.  */
++  /* If we have register sets, enable the generic core file support.  
+   if (tdep->gregset) {
+     set_gdbarch_iterate_over_regset_sections (gdbarch,
+                                           microblaze_iterate_over_regset_sections);
+-  }
+-
++  }*/
+   return gdbarch;
+ }
+ 
+@@ -957,6 +1016,8 @@ _initialize_microblaze_tdep ()
+ 
+   initialize_tdesc_microblaze_with_stack_protect ();
+   initialize_tdesc_microblaze ();
++  initialize_tdesc_microblaze64_with_stack_protect ();
++  initialize_tdesc_microblaze64 ();
+   /* Debug this files internals.  */
+   add_setshow_zuinteger_cmd ("microblaze", class_maintenance,
+                             &microblaze_debug_flag, _("\
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index c4c8098308f..81f7f30cb8e 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -28,7 +28,7 @@ struct microblaze_gregset
+    microblaze_gregset() {}
+    unsigned int gregs[32];
+    unsigned int fpregs[32];
+-   unsigned int pregs[16];
++   unsigned int pregs[18];
+ };
+ 
+ struct microblaze_gdbarch_tdep : gdbarch_tdep_base
+@@ -134,7 +134,7 @@ struct microblaze_frame_cache
+   struct trad_frame_saved_reg *saved_regs;
+ };
+ /* All registers are 32 bits.  */
+-#define MICROBLAZE_REGISTER_SIZE 4
++//#define MICROBLAZE_REGISTER_SIZE 8
+ 
+ /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
+    Only used for native debugging.  */
+diff --git a/include/elf/common.h b/include/elf/common.h
+index 6a66456cd22..11f5d1a3cc9 100644
+--- a/include/elf/common.h
++++ b/include/elf/common.h
+@@ -360,6 +360,7 @@
+ #define EM_U16_U8CORE  260     /* LAPIS nX-U16/U8 */
+ #define EM_TACHYUM     261     /* Tachyum */
+ #define EM_56800EF     262     /* NXP 56800EF Digital Signal Controller (DSC) */
++#define EM_MB_64       263     /* Xilinx MicroBlaze 32-bit RISC soft processor core */
+ 
+ /* If it is necessary to assign new unofficial EM_* values, please pick large
+    random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision
+diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
+index a48b1358efd..c515f15bfb8 100644
+--- a/include/elf/microblaze.h
++++ b/include/elf/microblaze.h
+@@ -62,6 +62,8 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
+   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31)    /* TEXT Entry offset 64-bit.  */
+   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit.  */
+   RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
++  RELOC_NUMBER (R_MICROBLAZE_IMML_64, 34)
++  RELOC_NUMBER (R_MICROBLAZE_GPC_64, 35)    /* GOT entry offset.  */
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+ 
+ /* Global base address names.  */
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 3d696325803..ee447cecc3f 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -33,6 +33,7 @@
+ #define get_field_r1(buf, instr)   get_field (buf, instr, RA_MASK, RA_LOW)
+ #define get_field_r2(buf, instr)   get_field (buf, instr, RB_MASK, RB_LOW)
+ #define get_int_field_imm(instr)   ((instr & IMM_MASK) >> IMM_LOW)
++#define get_int_field_imml(instr)  ((instr & IMML_MASK) >> IMM_LOW)
+ #define get_int_field_r1(instr)    ((instr & RA_MASK) >> RA_LOW)
+ 
+ #define NUM_STRBUFS 4
+@@ -73,11 +74,20 @@ get_field_imm (struct string_buf *buf, long instr)
+ }
+ 
+ static char *
+-get_field_imm5 (struct string_buf *buf, long instr)
++get_field_imml (struct string_buf *buf, long instr)
+ {
+   char *p = strbuf (buf);
+ 
+-  sprintf (p, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
++  sprintf (p, "%d", (int)((instr & IMML_MASK) >> IMM_LOW));
++  return p;
++}
++
++static char *
++get_field_imms (struct string_buf *buf, long instr)
++{
++  char *p = strbuf (buf);
++
++  sprintf (p, "%d", (short)((instr & IMM6_MASK) >> IMM_LOW));
+   return p;
+ }
+ 
+@@ -96,12 +106,9 @@ get_field_immw (struct string_buf *buf, long instr)
+   char *p = strbuf (buf);
+ 
+   if (instr & 0x00004000)
+-    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK)
+-                               >> IMM_WIDTH_LOW))); /* bsefi */
+-  else
+-    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >>
+-                               IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >>
+-                               IMM_LOW) + 1)); /* bsifi */
++    sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
++ else
++    sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM6_MASK) >> IMM_LOW) + 1)); /* bsifi */
+   return p;
+ }
+ 
+@@ -311,9 +318,14 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+                }
+            }
+          break;
+-       case INST_TYPE_RD_R1_IMM5:
++       case INST_TYPE_RD_R1_IMML:
++         print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
++                  get_field_r1(&buf, inst), get_field_imm (&buf, inst));
++          /* TODO: Also print symbol */
++          break;
++       case INST_TYPE_RD_R1_IMMS:
+          print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
+-                     get_field_r1 (&buf, inst), get_field_imm5 (&buf, inst));
++                  get_field_r1(&buf, inst), get_field_imms (&buf, inst));
+          break;
+        case INST_TYPE_RD_RFSL:
+          print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
+@@ -417,9 +429,12 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+                }
+            }
+          break;
+-       case INST_TYPE_RD_R2:
+-         print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
+-                     get_field_r2 (&buf, inst));
++        case INST_TYPE_IMML:
++         print_func (stream, "\t%s", get_field_imml (&buf, inst));
++          /* TODO: Also print symbol */
++         break;
++        case INST_TYPE_RD_R2:
++         print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_r2 (&buf, inst));
+          break;
+        case INST_TYPE_R2:
+          print_func (stream, "\t%s", get_field_r2 (&buf, inst));
+@@ -442,15 +457,12 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+          /* For mbar 16 or sleep insn.  */
+        case INST_TYPE_NONE:
+          break;
+-         /* For bit field insns.  */
++        /* For bit field insns.  */
+        case INST_TYPE_RD_R1_IMMW_IMMS:
+-         print_func (stream, "\t%s, %s, %s, %s",
+-                     get_field_rd (&buf, inst),
+-                     get_field_r1 (&buf, inst),
+-                     get_field_immw (&buf, inst),
+-                     get_field_imm5 (&buf, inst));
++         print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst),
++                  get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+          break;
+-         /* For tuqula instruction */
++       /* For tuqula instruction */
+        case INST_TYPE_RD:
+          print_func (stream, "\t%s", get_field_rd (&buf, inst));
+          break;
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index fe23b0af56a..afc1220e357 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -40,7 +40,7 @@
+ #define INST_TYPE_RD_SPECIAL 11
+ #define INST_TYPE_R1 12
+ /* New instn type for barrel shift imms.  */
+-#define INST_TYPE_RD_R1_IMM5  13
++#define INST_TYPE_RD_R1_IMMS  13
+ #define INST_TYPE_RD_RFSL    14
+ #define INST_TYPE_R1_RFSL    15
+ 
+@@ -62,6 +62,11 @@
+ /* For bsefi and bsifi */
+ #define INST_TYPE_RD_R1_IMMW_IMMS  21
+ 
++/* For 64-bit instructions */
++#define INST_TYPE_IMML 22
++#define INST_TYPE_RD_R1_IMML 23
++#define INST_TYPE_R1_IMML 24
++
+ #define INST_TYPE_NONE 25
+ 
+ 
+@@ -91,15 +96,14 @@
+ #define OPCODE_MASK_H24   0xFC1F07FF /* High 6, bits 20-16 and low 11 bits.  */
+ #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits.  */
+ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
+-#define OPCODE_MASK_H3    0xFC000600 /* High 6 bits and bits 21, 22.  */
+-#define OPCODE_MASK_H3B   0xFC00F9E0 /* High 6 bits and bits 16:20 and
+-                                       bits 23:26. */
++#define OPCODE_MASK_H3    0xFC000700 /* High 6 bits and bits 21, 22, 23.  */
++#define OPCODE_MASK_H3B   0xFC00E600 /* High 6 bits and bits 16, 17, 18, 21, 22.  */
+ #define OPCODE_MASK_H32   0xFC00FC00 /* High 6 bits and bit 16-21.  */
+-#define OPCODE_MASK_H32B  0xFC00F820 /* High 6 bits and bits 16:20 and
+-                                       bit 26 */
++#define OPCODE_MASK_H32B  0xFC00E000 /* High 6 bits and bit 16, 17, 18.  */
+ #define OPCODE_MASK_H34B  0xFC0000FF /* High 6 bits and low 8 bits.  */
+ #define OPCODE_MASK_H35B  0xFC0004FF /* High 6 bits and low 9 bits.  */
+ #define OPCODE_MASK_H34C  0xFC0007E0 /* High 6 bits and bits 21-26.  */
++#define OPCODE_MASK_H8    0xFF000000 /* High 8 bits only.  */
+ 
+ /* New Mask for msrset, msrclr insns.  */
+ #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16.  */
+@@ -109,7 +113,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 291
++#define MAX_OPCODES 412
+ 
+ const struct op_code_struct
+ {
+@@ -127,6 +131,7 @@ const struct op_code_struct
+   /* More info about output format here.  */
+ } microblaze_opcodes[MAX_OPCODES] =
+ {
++  /* 32-bit instructions */
+   {"add",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
+   {"rsub",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
+   {"addc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
+@@ -163,9 +168,9 @@ const struct op_code_struct
+   {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
+   {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
+   {"muli",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
+-  {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst },
+-  {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst },
+-  {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst },
++  {"bslli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst },
++  {"bsrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst },
++  {"bsrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst },
+   {"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
+   {"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+   {"or",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
+@@ -269,9 +274,7 @@ const struct op_code_struct
+   {"la",    INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik.  */
+   {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42.  */
+   {"not",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1.  */
+-  {"neg",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0.  */
+   {"rtb",   INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4.  */
+-  {"sub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra.  */
+   {"lmi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },
+   {"smi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
+   {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
+@@ -427,7 +430,131 @@ const struct op_code_struct
+   {"suspend",   INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 24.  */
+   {"swapb",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4,   swapb,     arithmetic_inst },
+   {"swaph",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4,   swaph,     arithmetic_inst },
+-  {NULL, 0, 0, 0, 0, 0, 0, 0, 0},
++  /* 64-bit instructions */
++  {"addl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000100, OPCODE_MASK_H4, addl, arithmetic_inst },
++  {"rsubl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000100, OPCODE_MASK_H4, rsubl, arithmetic_inst },
++  {"addlc",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000100, OPCODE_MASK_H4, addlc, arithmetic_inst },
++  {"rsublc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000100, OPCODE_MASK_H4, rsublc, arithmetic_inst },
++  {"addlk",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000100, OPCODE_MASK_H4, addlk, arithmetic_inst },
++  {"rsublk",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000100, OPCODE_MASK_H4, rsublk, arithmetic_inst },
++  {"addlkc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000100, OPCODE_MASK_H4, addlkc, arithmetic_inst },
++  {"rsublkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000100, OPCODE_MASK_H4, rsublkc, arithmetic_inst },
++  {"cmpl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
++  {"cmplu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
++  {"addli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsubli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlic",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlik",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },  /* Identical to 32-bit */
++  {"mull",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
++  {"bslll",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
++  {"bslra",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
++  {"bslrl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000100, OPCODE_MASK_H3, bslrl, barrel_shift_inst },
++  {"bsllli",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002400, OPCODE_MASK_H3B, bsllli, barrel_shift_inst },
++  {"bslrai",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002200, OPCODE_MASK_H3B, bslrai, barrel_shift_inst },
++  {"bslrli",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002000, OPCODE_MASK_H3B, bslrli, barrel_shift_inst },
++  {"bslefi",  INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64006000, OPCODE_MASK_H32B, bslefi, barrel_shift_inst },
++  {"bslifi",  INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6400a000, OPCODE_MASK_H32B, bslifi, barrel_shift_inst },
++  {"orl",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000100, OPCODE_MASK_H4, orl, logical_inst },
++  {"andl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000100, OPCODE_MASK_H4, andl, logical_inst },
++  {"xorl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000100, OPCODE_MASK_H4, xorl, logical_inst },
++  {"andnl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000100, OPCODE_MASK_H4, andnl, logical_inst },
++  {"pcmplbf", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000500, OPCODE_MASK_H4, pcmplbf, logical_inst },
++  {"pcmpleq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000500, OPCODE_MASK_H4, pcmpleq, logical_inst },
++  {"pcmplne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000500, OPCODE_MASK_H4, pcmplne, logical_inst },
++  {"srla",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000101, OPCODE_MASK_H34, srla, logical_inst },
++  {"srlc",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000121, OPCODE_MASK_H34, srlc, logical_inst },
++  {"srll",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000141, OPCODE_MASK_H34, srll, logical_inst },
++  {"sextl8",  INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000160, OPCODE_MASK_H34, sextl8, logical_inst },
++  {"sextl16", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000161, OPCODE_MASK_H34, sextl16, logical_inst },
++  {"sextl32", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000162, OPCODE_MASK_H34, sextl32, logical_inst },
++  {"brea",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98010000, OPCODE_MASK_H124, brea, branch_inst },
++  {"bread",   INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98110000, OPCODE_MASK_H124, bread, branch_inst },
++  {"breald",  INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98150000, OPCODE_MASK_H24, breald, branch_inst },
++  {"beaeq",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000000, OPCODE_MASK_H14, beaeq, branch_inst },
++  {"bealeq",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000100, OPCODE_MASK_H14, bealeq, branch_inst },
++  {"beaeqd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000000, OPCODE_MASK_H14, beaeqd, branch_inst },
++  {"bealeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000100, OPCODE_MASK_H14, bealeqd, branch_inst },
++  {"beane",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200000, OPCODE_MASK_H14, beane, branch_inst },
++  {"bealne",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200100, OPCODE_MASK_H14, bealne, branch_inst },
++  {"beaned",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200000, OPCODE_MASK_H14, beaned, branch_inst },
++  {"bealned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200100, OPCODE_MASK_H14, bealned, branch_inst },
++  {"bealt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400000, OPCODE_MASK_H14, bealt, branch_inst },
++  {"beallt",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400100, OPCODE_MASK_H14, beallt, branch_inst },
++  {"bealtd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400000, OPCODE_MASK_H14, bealtd, branch_inst },
++  {"bealltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400100, OPCODE_MASK_H14, bealltd, branch_inst },
++  {"beale",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600000, OPCODE_MASK_H14, beale, branch_inst },
++  {"bealle",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600100, OPCODE_MASK_H14, bealle, branch_inst },
++  {"bealed",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600000, OPCODE_MASK_H14, bealed, branch_inst },
++  {"bealled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600100, OPCODE_MASK_H14, bealled, branch_inst },
++  {"beagt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800000, OPCODE_MASK_H14, beagt, branch_inst },
++  {"bealgt",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800100, OPCODE_MASK_H14, bealgt, branch_inst },
++  {"beagtd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800000, OPCODE_MASK_H14, beagtd, branch_inst },
++  {"bealgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800100, OPCODE_MASK_H14, bealgtd, branch_inst },
++  {"beage",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00000, OPCODE_MASK_H14, beage, branch_inst },
++  {"bealge",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00100, OPCODE_MASK_H14, bealge, branch_inst },
++  {"beaged",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
++  {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
++  {"orli",    INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"andli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"xorli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"andnli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"imml",    INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
++  {"breai",   INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
++  {"breaid",  INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
++  {"brealid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8150000, OPCODE_MASK_H2, brealid, branch_inst },
++  {"beaeqi",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, beaeqi, branch_inst },
++  {"bealeqi", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqi */
++  {"beaeqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, beaeqid, branch_inst },
++  {"bealeqid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beaeqid */
++  {"beanei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, beanei, branch_inst },
++  {"bealnei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beanei */
++  {"beaneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, beaneid, branch_inst },
++  {"bealneid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beaneid */
++  {"bealti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, bealti, branch_inst },
++  {"beallti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealti */
++  {"bealtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, bealtid, branch_inst },
++  {"bealltid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to bealtid */
++  {"bealei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, bealei, branch_inst },
++  {"beallei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealei */
++  {"bealeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, bealeid, branch_inst },
++  {"bealleid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to bealeid */
++  {"beagti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, beagti, branch_inst },
++  {"bealgti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagti */
++  {"beagtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, beagtid, branch_inst },
++  {"bealgtid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beagtid */
++  {"beagei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, beagei, branch_inst },
++  {"bealgei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagei */
++  {"beageid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, beageid, branch_inst },
++  {"bealgeid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beageid */
++  {"ll",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000100, OPCODE_MASK_H4, ll, memory_load_inst },
++  {"llr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst },
++  {"sl",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst },
++  {"slr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst },
++  {"lli",     INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xEC000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },  /* Identical to 32-bit */
++  {"sli",     INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xFC000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
++  {"lla",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* lla translates to addlik */
++  {"dadd",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst },
++  {"drsub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst },
++  {"dmul",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000500, OPCODE_MASK_H4, dmul, arithmetic_inst },
++  {"ddiv",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000580, OPCODE_MASK_H4, ddiv, arithmetic_inst },
++  {"dcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000610, OPCODE_MASK_H4, dcmp_lt, arithmetic_inst },
++  {"dcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000620, OPCODE_MASK_H4, dcmp_eq, arithmetic_inst },
++  {"dcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000630, OPCODE_MASK_H4, dcmp_le, arithmetic_inst },
++  {"dcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000640, OPCODE_MASK_H4, dcmp_gt, arithmetic_inst },
++  {"dcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000650, OPCODE_MASK_H4, dcmp_ne, arithmetic_inst },
++  {"dcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000660, OPCODE_MASK_H4, dcmp_ge, arithmetic_inst },
++  {"dcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000600, OPCODE_MASK_H4, dcmp_un, arithmetic_inst },
++  {"dbl",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl,   arithmetic_inst },
++  {"dlong",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst },
++  {"dsqrt",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst },
++  {"neg",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0.  */
++  {"sub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra.  */
++
++  {"", 0, 0, 0, 0, 0, 0, 0, 0},
+ };
+ 
+ /* Prefix for register names.  */
+@@ -447,8 +574,17 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM5  ((int) 0x00000000)
+ #define MAX_IMM5  ((int) 0x0000001f)
+ 
++#define MIN_IMM6  ((int) 0x00000000)
++#define MAX_IMM6  ((int) 0x0000003f)
++
+ #define MIN_IMM_WIDTH  ((int) 0x00000001)
+ #define MAX_IMM_WIDTH  ((int) 0x00000020)
+ 
++#define MIN_IMM6_WIDTH  ((int) 0x00000001)
++#define MAX_IMM6_WIDTH  ((int) 0x00000040)
++
++#define MIN_IMML  ((long) 0xffffff8000000000L)
++#define MAX_IMML  ((long) 0x0000007fffffffffL)
++
+ #endif /* MICROBLAZE_OPC */
+ 
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index cb8d3a59949..08ed44352ee 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -25,6 +25,7 @@
+ 
+ enum microblaze_instr
+ {
++  /* 32-bit instructions */
+   add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
+   addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
+   mulh, mulhu, mulhsu, swapb, swaph,
+@@ -39,8 +40,8 @@ enum microblaze_instr
+   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+   bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
+-  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
+-  sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
++  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, lli,
++  sbi, shi, sli, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
+   fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
+   /* 'fsqrt' is a glibc:math.h symbol.  */
+   fint, microblaze_fsqrt,
+@@ -59,6 +60,18 @@ enum microblaze_instr
+   aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
+   eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
+   eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
++
++  /* 64-bit instructions */
++  addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++  bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
++  andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
++  brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
++  bealned, bealt, beallt, bealtd, bealltd, beale, bealle, bealed, bealled, beagt,
++  bealgt, beagtd, bealgtd, beage, bealge, beaged, bealged, breai, breaid, brealid,
++  beaeqi, beaeqid, beanei, beaneid, bealti, bealtid, bealei, bealeid, beagti,
++  beagtid, beagei, beageid, imml, ll, llr, sl, slr,
++  dadd, drsub, dmul, ddiv, dcmp_lt, dcmp_eq, dcmp_le, dcmp_gt, dcmp_ne, dcmp_ge,
++  dcmp_un, dbl, dlong, dsqrt,
+   invalid_inst
+ };
+ 
+@@ -136,15 +149,18 @@ enum microblaze_instr_type
+ #define RA_MASK 0x001F0000
+ #define RB_MASK 0x0000F800
+ #define IMM_MASK 0x0000FFFF
++#define IMML_MASK 0x00FFFFFF
+ 
+-/* Imm mask for barrel shifts.  */
++/* Imm masks for barrel shifts.  */
+ #define IMM5_MASK 0x0000001F
++#define IMM6_MASK 0x0000003F
+ 
+ /* Imm mask for mbar.  */
+ #define IMM5_MBAR_MASK 0x03E00000
+ 
+-/* Imm mask for extract/insert width. */
++/* Imm masks for extract/insert width. */
+ #define IMM5_WIDTH_MASK 0x000007C0
++#define IMM6_WIDTH_MASK 0x00000FC0
+ 
+ /* FSL imm mask for get, put instructions.  */
+ #define  RFSL_MASK 0x000000F
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch
new file mode 100644
index 00000000..a744bcb4
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch
@@ -0,0 +1,35 @@
+From 6c699df5c33f13ea3226d144f544d5a295edcf17 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 19 Apr 2021 14:33:27 +0530
+Subject: [PATCH 07/53] these changes will make 64 bit vectors as default
+ target types when we built gdb with microblaze 64 bit type targets,for
+ instance microblaze-xilinx-elf64/microblazeel-xilinx-elf64
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/config.bfd | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/bfd/config.bfd b/bfd/config.bfd
+index cbba305354f..f7134608693 100644
+--- a/bfd/config.bfd
++++ b/bfd/config.bfd
+@@ -880,7 +880,15 @@ case "${targ}" in
+     targ_defvec=metag_elf32_vec
+     targ_underscore=yes
+     ;;
++  microblazeel*-*64)
++    targ_defvec=microblaze_elf64_le_vec
++    targ_selvecs=microblaze_elf64_vec
++    ;;
+ 
++  microblaze*-*64)
++    targ_defvec=microblaze_elf64_vec
++    targ_selvecs=microblaze_elf64_le_vec
++    ;;
+   microblazeel*-*)
+     targ_defvec=microblaze_elf32_le_vec
+     targ_selvecs=microblaze_elf32_vec
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch
new file mode 100644
index 00000000..10517953
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch
@@ -0,0 +1,4104 @@
+From 815e641399628fcde8e13f925e4a6d3bc565a762 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 9 Nov 2021 16:19:17 +0530
+Subject: [PATCH 08/53] Added m64 abi for 64 bit target descriptions. set m64
+ abi for 64 bit elf.
+
+Conflicts:
+        gdb/microblaze-tdep.c
+        gdb/microblaze-tdep.h
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elf64-microblaze.c | 3810 ++++++++++++++++++++++++++++++++++++++++
+ gdb/microblaze-tdep.c  |  160 +-
+ gdb/microblaze-tdep.h  |   13 +-
+ 3 files changed, 3975 insertions(+), 8 deletions(-)
+ create mode 100755 bfd/elf64-microblaze.c
+
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+new file mode 100755
+index 00000000000..6cd9753a592
+--- /dev/null
++++ b/bfd/elf64-microblaze.c
+@@ -0,0 +1,3810 @@
++/* Xilinx MicroBlaze-specific support for 32-bit ELF
++
++   Copyright (C) 2009-2021 Free Software Foundation, Inc.
++
++   This file is part of BFD, the Binary File Descriptor library.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program; if not, write to the
++   Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
++   Boston, MA 02110-1301, USA.  */
++
++
++#include "sysdep.h"
++#include "bfd.h"
++#include "bfdlink.h"
++#include "libbfd.h"
++#include "elf-bfd.h"
++#include "elf/microblaze.h"
++#include <assert.h>
++
++#define        USE_RELA        /* Only USE_REL is actually significant, but this is
++                          here are a reminder...  */
++#define INST_WORD_SIZE 4
++
++static int ro_small_data_pointer = 0;
++static int rw_small_data_pointer = 0;
++
++static reloc_howto_type * microblaze_elf_howto_table [(int) R_MICROBLAZE_max];
++
++static reloc_howto_type microblaze_elf_howto_raw[] =
++{
++   /* This reloc does nothing.  */
++   HOWTO (R_MICROBLAZE_NONE,   /* Type.  */
++         0,                    /* Rightshift.  */
++         0,                    /* Size.  */
++         0,                    /* Bitsize.  */
++         false,                /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_dont,  /* Complain on overflow.  */
++         NULL,                  /* Special Function.  */
++         "R_MICROBLAZE_NONE",  /* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0,                    /* Dest Mask.  */
++         false),               /* PC relative offset?  */
++
++   /* A standard 32 bit relocation.  */
++   HOWTO (R_MICROBLAZE_32,     /* Type.  */
++         0,                    /* Rightshift.  */
++         4,                    /* Size.  */
++         32,                   /* Bitsize.  */
++         false,                /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_bitfield, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,/* Special Function.  */
++         "R_MICROBLAZE_32",    /* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0xffffffff,           /* Dest Mask.  */
++         false),               /* PC relative offset?  */
++
++   /* A standard PCREL 32 bit relocation.  */
++   HOWTO (R_MICROBLAZE_32_PCREL,/* Type.  */
++         0,                    /* Rightshift.  */
++         4,                    /* Size.  */
++         32,                   /* Bitsize.  */
++         true,                 /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_bitfield, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,/* Special Function.  */
++         "R_MICROBLAZE_32_PCREL",      /* Name.  */
++         true,                 /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0xffffffff,           /* Dest Mask.  */
++         true),                /* PC relative offset?  */
++
++   /* A 64 bit PCREL relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_64_PCREL,/* Type.  */
++         0,                    /* Rightshift.  */
++         4,                    /* Size.  */
++         16,                   /* Bitsize.  */
++         true,                 /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_dont, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,/* Special Function.  */
++         "R_MICROBLAZE_64_PCREL",      /* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0x0000ffff,           /* Dest Mask.  */
++         true),                /* PC relative offset?  */
++
++   /* The low half of a PCREL 32 bit relocation.  */
++   HOWTO (R_MICROBLAZE_32_PCREL_LO,    /* Type.  */
++         0,                    /* Rightshift.  */
++         4,                    /* Size.  */
++         16,                   /* Bitsize.  */
++         true,                 /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_signed, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,        /* Special Function.  */
++         "R_MICROBLAZE_32_PCREL_LO",   /* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0x0000ffff,           /* Dest Mask.  */
++         true),                /* PC relative offset?  */
++
++   HOWTO (R_MICROBLAZE_IMML_64,        /* Type.  */
++          0,                   /* Rightshift.  */
++          4,                   /* Size (0 = byte, 1 = short, 2 = long).  */
++          64,                  /* Bitsize.  */
++          false,               /* PC_relative.  */
++          0,                   /* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_IMML_64",      /* Name.  */
++          false,               /* Partial Inplace.  */
++          0,                   /* Source Mask.  */
++          0xffffffffffffff,            /* Dest Mask.  */
++          false),              /* PC relative offset?  */
++
++   /* A 64 bit relocation.  Table entry not really used.  */
++   HOWTO (R_MICROBLAZE_64,             /* Type.  */
++          0,                   /* Rightshift.  */
++          2,                   /* Size (0 = byte, 1 = short, 2 = long).  */
++          16,                  /* Bitsize.  */
++          false,               /* PC_relative.  */
++          0,                   /* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_64",           /* Name.  */
++          false,               /* Partial Inplace.  */
++          0,                   /* Source Mask.  */
++          0x0000ffff,          /* Dest Mask.  */
++          false),              /* PC relative offset?  */
++
++   /* The low half of a 32 bit relocation.  */
++   HOWTO (R_MICROBLAZE_32_LO,  /* Type.  */
++         0,                    /* Rightshift.  */
++         4,                    /* Size.  */
++         16,                   /* Bitsize.  */
++         false,                /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_signed, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,/* Special Function.  */
++         "R_MICROBLAZE_32_LO", /* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0x0000ffff,           /* Dest Mask.  */
++         false),               /* PC relative offset?  */
++
++   /* Read-only small data section relocation.  */
++   HOWTO (R_MICROBLAZE_SRO32,  /* Type.  */
++         0,                    /* Rightshift.  */
++         4,                    /* Size.  */
++         16,                   /* Bitsize.  */
++         false,                /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_bitfield, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,/* Special Function.  */
++         "R_MICROBLAZE_SRO32", /* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0x0000ffff,           /* Dest Mask.  */
++         false),               /* PC relative offset?  */
++
++   /* Read-write small data area relocation.  */
++   HOWTO (R_MICROBLAZE_SRW32,  /* Type.  */
++         0,                    /* Rightshift.  */
++         4,                    /* Size.  */
++         16,                   /* Bitsize.  */
++         false,                /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_bitfield, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,/* Special Function.  */
++         "R_MICROBLAZE_SRW32", /* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0x0000ffff,           /* Dest Mask.  */
++         false),               /* PC relative offset?  */
++
++   /* This reloc does nothing. Used for relaxation.  */
++   HOWTO (R_MICROBLAZE_32_NONE,        /* Type.  */
++          0,                   /* Rightshift.  */
++          2,                   /* Size (0 = byte, 1 = short, 2 = long).  */
++          32,                  /* Bitsize.  */
++          true,                        /* PC_relative.  */
++          0,                   /* Bitpos.  */
++          complain_overflow_bitfield,  /* Complain on overflow.  */
++          NULL,                  /* Special Function.  */
++          "R_MICROBLAZE_32_NONE",/* Name.  */
++          false,               /* Partial Inplace.  */
++          0,                   /* Source Mask.  */
++          0,                   /* Dest Mask.  */
++          false),              /* PC relative offset?  */
++
++   /* This reloc does nothing.  Used for relaxation.  */
++   HOWTO (R_MICROBLAZE_64_NONE,        /* Type.  */
++         0,                    /* Rightshift.  */
++         0,                    /* Size.  */
++         0,                    /* Bitsize.  */
++         true,                 /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_dont, /* Complain on overflow.  */
++         NULL,                  /* Special Function.  */
++         "R_MICROBLAZE_64_NONE",/* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0,                    /* Dest Mask.  */
++         false),               /* PC relative offset?  */
++
++   /* Symbol Op Symbol relocation.  */
++   HOWTO (R_MICROBLAZE_32_SYM_OP_SYM,          /* Type.  */
++         0,                    /* Rightshift.  */
++         4,                    /* Size.  */
++         32,                   /* Bitsize.  */
++         false,                /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_bitfield, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,/* Special Function.  */
++         "R_MICROBLAZE_32_SYM_OP_SYM",         /* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0xffffffff,           /* Dest Mask.  */
++         false),               /* PC relative offset?  */
++
++   /* GNU extension to record C++ vtable hierarchy.  */
++   HOWTO (R_MICROBLAZE_GNU_VTINHERIT, /* Type.  */
++         0,                     /* Rightshift.  */
++         4,                     /* Size.  */
++         0,                     /* Bitsize.  */
++         false,                 /* PC_relative.  */
++         0,                     /* Bitpos.  */
++         complain_overflow_dont,/* Complain on overflow.  */
++         NULL,                  /* Special Function.  */
++         "R_MICROBLAZE_GNU_VTINHERIT", /* Name.  */
++         false,                 /* Partial Inplace.  */
++         0,                     /* Source Mask.  */
++         0,                     /* Dest Mask.  */
++         false),                /* PC relative offset?  */
++
++   /* GNU extension to record C++ vtable member usage.  */
++   HOWTO (R_MICROBLAZE_GNU_VTENTRY,   /* Type.  */
++         0,                     /* Rightshift.  */
++         4,                     /* Size.  */
++         0,                     /* Bitsize.  */
++         false,                 /* PC_relative.  */
++         0,                     /* Bitpos.  */
++         complain_overflow_dont,/* Complain on overflow.  */
++         _bfd_elf_rel_vtable_reloc_fn,  /* Special Function.  */
++         "R_MICROBLAZE_GNU_VTENTRY", /* Name.  */
++         false,                 /* Partial Inplace.  */
++         0,                     /* Source Mask.  */
++         0,                     /* Dest Mask.  */
++         false),                /* PC relative offset?  */
++
++   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GOTPC_64,       /* Type.  */
++         0,                    /* Rightshift.  */
++         4,                    /* Size.  */
++         16,                   /* Bitsize.  */
++         true,                 /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_dont, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,        /* Special Function.  */
++         "R_MICROBLAZE_GOTPC_64",      /* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0x0000ffff,           /* Dest Mask.  */
++         true),                /* PC relative offset?  */
++
++     /* A 64 bit TEXTPCREL relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_TEXTPCREL_64,   /* Type.  */
++         0,                    /* Rightshift.  */
++         2,                    /* Size (0 = byte, 1 = short, 2 = long).  */
++         16,                   /* Bitsize.  */
++         true,                 /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_dont, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,        /* Special Function.  */
++         "R_MICROBLAZE_TEXTPCREL_64",  /* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0x0000ffff,           /* Dest Mask.  */
++         true),                /* PC relative offset?  */
++
++   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GPC_64,         /* Type.  */
++          0,                   /* Rightshift.  */
++          2,                   /* Size (0 = byte, 1 = short, 2 = long).  */
++          16,                  /* Bitsize.  */
++          true,                        /* PC_relative.  */
++          0,                   /* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,       /* Special Function.  */
++          "R_MICROBLAZE_GPC_64",       /* Name.  */
++          false,               /* Partial Inplace.  */
++          0,                   /* Source Mask.  */
++          0x0000ffff,          /* Dest Mask.  */
++          true),               /* PC relative offset?  */
++
++   /* A 64 bit GOT relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GOT_64,  /* Type.  */
++         0,                    /* Rightshift.  */
++         2,                    /* Size (0 = byte, 1 = short, 2 = long).  */
++         16,                   /* Bitsize.  */
++         false,                /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_dont, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,/* Special Function.  */
++         "R_MICROBLAZE_GOT_64",/* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0x0000ffff,           /* Dest Mask.  */
++         false),               /* PC relative offset?  */
++
++    /* A 64 bit TEXTREL relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_TEXTREL_64,  /* Type.  */
++         0,                    /* Rightshift.  */
++         2,                    /* Size (0 = byte, 1 = short, 2 = long).  */
++         16,                   /* Bitsize.  */
++         false,                /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_dont, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,/* Special Function.  */
++         "R_MICROBLAZE_TEXTREL_64",/* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0x0000ffff,           /* Dest Mask.  */
++         false),               /* PC relative offset?  */
++
++   /* A 64 bit PLT relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_PLT_64,  /* Type.  */
++         0,                    /* Rightshift.  */
++         4,                    /* Size.  */
++         16,                   /* Bitsize.  */
++         true,                 /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_dont, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,/* Special Function.  */
++         "R_MICROBLAZE_PLT_64",/* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0x0000ffff,           /* Dest Mask.  */
++         true),                /* PC relative offset?  */
++
++   /*  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_REL,    /* Type.  */
++         0,                    /* Rightshift.  */
++         4,                    /* Size.  */
++         16,                   /* Bitsize.  */
++         true,                 /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_dont, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,/* Special Function.  */
++         "R_MICROBLAZE_REL",   /* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0x0000ffff,           /* Dest Mask.  */
++         true),                /* PC relative offset?  */
++
++   /*  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_JUMP_SLOT,/* Type.  */
++         0,                    /* Rightshift.  */
++         4,                    /* Size.  */
++         16,                   /* Bitsize.  */
++         true,                 /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_dont, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,/* Special Function.  */
++         "R_MICROBLAZE_JUMP_SLOT",     /* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0x0000ffff,           /* Dest Mask.  */
++         true),                /* PC relative offset?  */
++
++   /*  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GLOB_DAT,/* Type.  */
++         0,                    /* Rightshift.  */
++         4,                    /* Size.  */
++         16,                   /* Bitsize.  */
++         true,                 /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_dont, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,/* Special Function.  */
++         "R_MICROBLAZE_GLOB_DAT",      /* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0x0000ffff,           /* Dest Mask.  */
++         true),                /* PC relative offset?  */
++
++   /* A 64 bit GOT relative relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GOTOFF_64,      /* Type.  */
++         0,                    /* Rightshift.  */
++         4,                    /* Size.  */
++         16,                   /* Bitsize.  */
++         false,                /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_dont, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,/* Special Function.  */
++         "R_MICROBLAZE_GOTOFF_64",     /* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0x0000ffff,           /* Dest Mask.  */
++         false),               /* PC relative offset?  */
++
++   /* A 32 bit GOT relative relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GOTOFF_32,      /* Type.  */
++         0,                    /* Rightshift.  */
++         4,                    /* Size.  */
++         16,                   /* Bitsize.  */
++         false,                /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_dont, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,        /* Special Function.  */
++         "R_MICROBLAZE_GOTOFF_32",     /* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0x0000ffff,           /* Dest Mask.  */
++         false),               /* PC relative offset?  */
++
++   /* COPY relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_COPY,   /* Type.  */
++         0,                    /* Rightshift.  */
++         4,                    /* Size.  */
++         16,                   /* Bitsize.  */
++         false,                /* PC_relative.  */
++         0,                    /* Bitpos.  */
++         complain_overflow_dont, /* Complain on overflow.  */
++         bfd_elf_generic_reloc,/* Special Function.  */
++         "R_MICROBLAZE_COPY",  /* Name.  */
++         false,                /* Partial Inplace.  */
++         0,                    /* Source Mask.  */
++         0x0000ffff,           /* Dest Mask.  */
++         false),               /* PC relative offset?  */
++
++   /* Marker relocs for TLS.  */
++   HOWTO (R_MICROBLAZE_TLS,
++        0,                     /* rightshift */
++        2,                     /* size (0 = byte, 1 = short, 2 = long) */
++        32,                    /* bitsize */
++        false,                 /* pc_relative */
++        0,                     /* bitpos */
++        complain_overflow_dont, /* complain_on_overflow */
++        bfd_elf_generic_reloc, /* special_function */
++        "R_MICROBLAZE_TLS",            /* name */
++        false,                 /* partial_inplace */
++        0,                     /* src_mask */
++        0x0000ffff,                    /* dst_mask */
++        false),                /* pcrel_offset */
++
++   HOWTO (R_MICROBLAZE_TLSGD,
++        0,                     /* rightshift */
++        4,                     /* size */
++        32,                    /* bitsize */
++        false,                 /* pc_relative */
++        0,                     /* bitpos */
++        complain_overflow_dont, /* complain_on_overflow */
++        bfd_elf_generic_reloc, /* special_function */
++        "R_MICROBLAZE_TLSGD",          /* name */
++        false,                 /* partial_inplace */
++        0,                     /* src_mask */
++        0x0000ffff,                    /* dst_mask */
++        false),                /* pcrel_offset */
++
++   HOWTO (R_MICROBLAZE_TLSLD,
++        0,                     /* rightshift */
++        2,                     /* size (0 = byte, 1 = short, 2 = long) */
++        32,                    /* bitsize */
++        false,                 /* pc_relative */
++        0,                     /* bitpos */
++        complain_overflow_dont, /* complain_on_overflow */
++        bfd_elf_generic_reloc, /* special_function */
++        "R_MICROBLAZE_TLSLD",          /* name */
++        false,                 /* partial_inplace */
++        0,                     /* src_mask */
++        0x0000ffff,            /* dst_mask */
++        false),                /* pcrel_offset */
++
++   /* Computes the load module index of the load module that contains the
++      definition of its TLS sym.  */
++   HOWTO (R_MICROBLAZE_TLSDTPMOD32,
++        0,                     /* rightshift */
++        2,                     /* size (0 = byte, 1 = short, 2 = long) */
++        32,                    /* bitsize */
++        false,                 /* pc_relative */
++        0,                     /* bitpos */
++        complain_overflow_dont, /* complain_on_overflow */
++        bfd_elf_generic_reloc, /* special_function */
++        "R_MICROBLAZE_TLSDTPMOD32",    /* name */
++        false,                 /* partial_inplace */
++        0,                     /* src_mask */
++        0x0000ffff,            /* dst_mask */
++        false),                /* pcrel_offset */
++
++   /* Computes a dtv-relative displacement, the difference between the value
++      of sym+add and the base address of the thread-local storage block that
++      contains the definition of sym, minus 0x8000.  Used for initializing GOT */
++   HOWTO (R_MICROBLAZE_TLSDTPREL32,
++        0,                     /* rightshift */
++        4,                     /* size */
++        32,                    /* bitsize */
++        false,                 /* pc_relative */
++        0,                     /* bitpos */
++        complain_overflow_dont, /* complain_on_overflow */
++        bfd_elf_generic_reloc, /* special_function */
++        "R_MICROBLAZE_TLSDTPREL32",    /* name */
++        false,                 /* partial_inplace */
++        0,                     /* src_mask */
++        0x0000ffff,            /* dst_mask */
++        false),                /* pcrel_offset */
++
++   /* Computes a dtv-relative displacement, the difference between the value
++      of sym+add and the base address of the thread-local storage block that
++      contains the definition of sym, minus 0x8000.  */
++   HOWTO (R_MICROBLAZE_TLSDTPREL64,
++        0,                     /* rightshift */
++        4,                     /* size */
++        32,                    /* bitsize */
++        false,                 /* pc_relative */
++        0,                     /* bitpos */
++        complain_overflow_dont, /* complain_on_overflow */
++        bfd_elf_generic_reloc, /* special_function */
++        "R_MICROBLAZE_TLSDTPREL64",    /* name */
++        false,                 /* partial_inplace */
++        0,                     /* src_mask */
++        0x0000ffff,            /* dst_mask */
++        false),                /* pcrel_offset */
++
++   /* Computes a tp-relative displacement, the difference between the value of
++      sym+add and the value of the thread pointer (r13).  */
++   HOWTO (R_MICROBLAZE_TLSGOTTPREL32,
++        0,                     /* rightshift */
++        4,                     /* size */
++        32,                    /* bitsize */
++        false,                 /* pc_relative */
++        0,                     /* bitpos */
++        complain_overflow_dont, /* complain_on_overflow */
++        bfd_elf_generic_reloc, /* special_function */
++        "R_MICROBLAZE_TLSGOTTPREL32",  /* name */
++        false,                 /* partial_inplace */
++        0,                     /* src_mask */
++        0x0000ffff,            /* dst_mask */
++        false),                /* pcrel_offset */
++
++   /* Computes a tp-relative displacement, the difference between the value of
++      sym+add and the value of the thread pointer (r13).  */
++   HOWTO (R_MICROBLAZE_TLSTPREL32,
++        0,                     /* rightshift */
++        4,                     /* size */
++        32,                    /* bitsize */
++        false,                 /* pc_relative */
++        0,                     /* bitpos */
++        complain_overflow_dont, /* complain_on_overflow */
++        bfd_elf_generic_reloc, /* special_function */
++        "R_MICROBLAZE_TLSTPREL32",     /* name */
++        false,                 /* partial_inplace */
++        0,                     /* src_mask */
++        0x0000ffff,            /* dst_mask */
++        false),                /* pcrel_offset */
++
++};
++
++#ifndef NUM_ELEM
++#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
++#endif
++
++/* Initialize the microblaze_elf_howto_table, so that linear accesses can be done.  */
++
++static void
++microblaze_elf_howto_init (void)
++{
++  unsigned int i;
++
++  for (i = NUM_ELEM (microblaze_elf_howto_raw); i--;)
++    {
++      unsigned int type;
++
++      type = microblaze_elf_howto_raw[i].type;
++
++      BFD_ASSERT (type < NUM_ELEM (microblaze_elf_howto_table));
++
++      microblaze_elf_howto_table [type] = & microblaze_elf_howto_raw [i];
++    }
++}
++
++static reloc_howto_type *
++microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
++                                 bfd_reloc_code_real_type code)
++{
++  enum elf_microblaze_reloc_type microblaze_reloc = R_MICROBLAZE_NONE;
++
++  switch (code)
++    {
++    case BFD_RELOC_NONE:
++      microblaze_reloc = R_MICROBLAZE_NONE;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_NONE:
++      microblaze_reloc = R_MICROBLAZE_32_NONE;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_NONE:
++      microblaze_reloc = R_MICROBLAZE_64_NONE;
++      break;
++    case BFD_RELOC_32:
++      microblaze_reloc = R_MICROBLAZE_32;
++      break;
++      /* RVA is treated the same as 64 */
++    case BFD_RELOC_RVA:
++      microblaze_reloc = R_MICROBLAZE_IMML_64;
++      break;
++    case BFD_RELOC_32_PCREL:
++      microblaze_reloc = R_MICROBLAZE_32_PCREL;
++      break;
++    case BFD_RELOC_64_PCREL:
++      microblaze_reloc = R_MICROBLAZE_64_PCREL;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_LO_PCREL:
++      microblaze_reloc = R_MICROBLAZE_32_PCREL_LO;
++      break;
++    case BFD_RELOC_64:
++      microblaze_reloc = R_MICROBLAZE_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_LO:
++      microblaze_reloc = R_MICROBLAZE_32_LO;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_ROSDA:
++      microblaze_reloc = R_MICROBLAZE_SRO32;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_RWSDA:
++      microblaze_reloc = R_MICROBLAZE_SRW32;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM:
++      microblaze_reloc = R_MICROBLAZE_32_SYM_OP_SYM;
++      break;
++    case BFD_RELOC_VTABLE_INHERIT:
++      microblaze_reloc = R_MICROBLAZE_GNU_VTINHERIT;
++      break;
++    case BFD_RELOC_VTABLE_ENTRY:
++      microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
++      break;
++    case BFD_RELOC_MICROBLAZE_EA64:
++      microblaze_reloc = R_MICROBLAZE_IMML_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_GOTPC:
++      microblaze_reloc = R_MICROBLAZE_GOTPC_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_GPC:
++      microblaze_reloc = R_MICROBLAZE_GPC_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_GOT:
++      microblaze_reloc = R_MICROBLAZE_GOT_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TEXTPCREL:
++      microblaze_reloc = R_MICROBLAZE_TEXTPCREL_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TEXTREL:
++      microblaze_reloc = R_MICROBLAZE_TEXTREL_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_PLT:
++      microblaze_reloc = R_MICROBLAZE_PLT_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_GOTOFF:
++      microblaze_reloc = R_MICROBLAZE_GOTOFF_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_GOTOFF:
++      microblaze_reloc = R_MICROBLAZE_GOTOFF_32;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TLSGD:
++      microblaze_reloc = R_MICROBLAZE_TLSGD;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TLSLD:
++      microblaze_reloc = R_MICROBLAZE_TLSLD;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_TLSDTPREL:
++      microblaze_reloc = R_MICROBLAZE_TLSDTPREL32;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TLSDTPREL:
++      microblaze_reloc = R_MICROBLAZE_TLSDTPREL64;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_TLSDTPMOD:
++      microblaze_reloc = R_MICROBLAZE_TLSDTPMOD32;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL:
++      microblaze_reloc = R_MICROBLAZE_TLSGOTTPREL32;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TLSTPREL:
++      microblaze_reloc = R_MICROBLAZE_TLSTPREL32;
++      break;
++    case BFD_RELOC_MICROBLAZE_COPY:
++      microblaze_reloc = R_MICROBLAZE_COPY;
++      break;
++    default:
++      return (reloc_howto_type *) NULL;
++    }
++
++  if (!microblaze_elf_howto_table [R_MICROBLAZE_32])
++    /* Initialize howto table if needed.  */
++    microblaze_elf_howto_init ();
++
++  return microblaze_elf_howto_table [(int) microblaze_reloc];
++};
++
++static reloc_howto_type *
++microblaze_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
++                                 const char *r_name)
++{
++  unsigned int i;
++
++  for (i = 0; i < NUM_ELEM (microblaze_elf_howto_raw); i++)
++    if (microblaze_elf_howto_raw[i].name != NULL
++       && strcasecmp (microblaze_elf_howto_raw[i].name, r_name) == 0)
++      return &microblaze_elf_howto_raw[i];
++
++  return NULL;
++}
++
++/* Set the howto pointer for a RCE ELF reloc.  */
++
++static bool
++microblaze_elf_info_to_howto (bfd * abfd,
++                             arelent * cache_ptr,
++                             Elf_Internal_Rela * dst)
++{
++  unsigned int r_type;
++
++  if (!microblaze_elf_howto_table [R_MICROBLAZE_32])
++    /* Initialize howto table if needed.  */
++    microblaze_elf_howto_init ();
++
++  r_type = ELF64_R_TYPE (dst->r_info);
++  if (r_type >= R_MICROBLAZE_max)
++    {
++      /* xgettext:c-format */
++      _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
++                         abfd, r_type);
++      bfd_set_error (bfd_error_bad_value);
++      return false;
++    }
++
++  cache_ptr->howto = microblaze_elf_howto_table [r_type];
++  return true;
++}
++
++struct _microblaze_elf_section_data
++{
++  struct bfd_elf_section_data elf;
++  /* Count of used relaxation table entries.  */
++  size_t relax_count;
++  /* Relaxation table.  */
++  struct relax_table *relax;
++};
++
++#define microblaze_elf_section_data(sec) \
++  ((struct _microblaze_elf_section_data *) elf_section_data (sec))
++
++static bool
++microblaze_elf_new_section_hook (bfd *abfd, asection *sec)
++{
++  if (!sec->used_by_bfd)
++    {
++      struct _microblaze_elf_section_data *sdata;
++      size_t amt = sizeof (*sdata);
++
++      sdata = bfd_zalloc (abfd, amt);
++      if (sdata == NULL)
++       return false;
++      sec->used_by_bfd = sdata;
++    }
++
++  return _bfd_elf_new_section_hook (abfd, sec);
++}
++
++/* Microblaze ELF local labels start with 'L.' or '$L', not '.L'.  */
++
++static bool
++microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
++{
++  if (name[0] == 'L' && name[1] == '.')
++    return true;
++
++  if (name[0] == '$' && name[1] == 'L')
++    return true;
++
++  /* With gcc, the labels go back to starting with '.', so we accept
++     the generic ELF local label syntax as well.  */
++  return _bfd_elf_is_local_label_name (abfd, name);
++}
++
++/* The microblaze linker (like many others) needs to keep track of
++   the number of relocs that it decides to copy as dynamic relocs in
++   check_relocs for each symbol. This is so that it can later discard
++   them if they are found to be unnecessary.  We store the information
++   in a field extending the regular ELF linker hash table.  */
++
++struct elf64_mb_dyn_relocs
++{
++  struct elf64_mb_dyn_relocs *next;
++
++  /* The input section of the reloc.  */
++  asection *sec;
++
++  /* Total number of relocs copied for the input section.  */
++  bfd_size_type count;
++
++  /* Number of pc-relative relocs copied for the input section.  */
++  bfd_size_type pc_count;
++};
++
++/* ELF linker hash entry.  */
++
++struct elf64_mb_link_hash_entry
++{
++  struct elf_link_hash_entry elf;
++
++  /* Track dynamic relocs copied for this symbol.  */
++  struct elf64_mb_dyn_relocs *dyn_relocs;
++
++  /* TLS Reference Types for the symbol; Updated by check_relocs */
++#define TLS_GD     1  /* GD reloc. */
++#define TLS_LD     2  /* LD reloc. */
++#define TLS_TPREL  4  /* TPREL reloc, => IE. */
++#define TLS_DTPREL 8  /* DTPREL reloc, => LD. */
++#define TLS_TLS    16 /* Any TLS reloc.  */
++  unsigned char tls_mask;
++
++};
++
++#define IS_TLS_GD(x)     (x == (TLS_TLS | TLS_GD))
++#define IS_TLS_LD(x)     (x == (TLS_TLS | TLS_LD))
++#define IS_TLS_DTPREL(x) (x == (TLS_TLS | TLS_DTPREL))
++#define IS_TLS_NONE(x)   (x == 0)
++
++#define elf64_mb_hash_entry(ent) ((struct elf64_mb_link_hash_entry *)(ent))
++
++/* ELF linker hash table.  */
++
++struct elf64_mb_link_hash_table
++{
++  struct elf_link_hash_table elf;
++
++  /* Short-cuts to get to dynamic linker sections.  */
++  asection *sgot;
++  asection *sgotplt;
++  asection *srelgot;
++  asection *splt;
++  asection *srelplt;
++  asection *sdynbss;
++  asection *srelbss;
++
++  /* Small local sym to section mapping cache.  */
++  struct sym_cache sym_sec;
++
++  /* TLS Local Dynamic GOT Entry */
++  union {
++    bfd_signed_vma refcount;
++    bfd_vma offset;
++  } tlsld_got;
++};
++
++/* Nonzero if this section has TLS related relocations.  */
++#define has_tls_reloc sec_flg0
++
++/* Get the ELF linker hash table from a link_info structure.  */
++
++#define elf64_mb_hash_table(p) \
++  ((is_elf_hash_table ((p)->hash)                                      \
++    && elf_hash_table_id (elf_hash_table (p)) == MICROBLAZE_ELF_DATA)  \
++   ? (struct elf64_mb_link_hash_table *) (p)->hash : NULL)
++
++/* Create an entry in a microblaze ELF linker hash table.  */
++
++static struct bfd_hash_entry *
++link_hash_newfunc (struct bfd_hash_entry *entry,
++                  struct bfd_hash_table *table,
++                  const char *string)
++{
++  /* Allocate the structure if it has not already been allocated by a
++     subclass.  */
++  if (entry == NULL)
++    {
++      entry = bfd_hash_allocate (table,
++                                sizeof (struct elf64_mb_link_hash_entry));
++      if (entry == NULL)
++       return entry;
++    }
++
++  /* Call the allocation method of the superclass.  */
++  entry = _bfd_elf_link_hash_newfunc (entry, table, string);
++  if (entry != NULL)
++    {
++      struct elf64_mb_link_hash_entry *eh;
++
++      eh = (struct elf64_mb_link_hash_entry *) entry;
++      eh->tls_mask = 0;
++    }
++
++  return entry;
++}
++
++/* Create a mb ELF linker hash table.  */
++
++static struct bfd_link_hash_table *
++microblaze_elf_link_hash_table_create (bfd *abfd)
++{
++  struct elf64_mb_link_hash_table *ret;
++  size_t amt = sizeof (struct elf64_mb_link_hash_table);
++
++  ret = (struct elf64_mb_link_hash_table *) bfd_zmalloc (amt);
++  if (ret == NULL)
++    return NULL;
++
++  if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, link_hash_newfunc,
++                                     sizeof (struct elf64_mb_link_hash_entry),
++                                     MICROBLAZE_ELF_DATA))
++    {
++      free (ret);
++      return NULL;
++    }
++
++  return &ret->elf.root;
++}
++
++/* Set the values of the small data pointers.  */
++
++static void
++microblaze_elf_final_sdp (struct bfd_link_info *info)
++{
++  struct bfd_link_hash_entry *h;
++
++  h = bfd_link_hash_lookup (info->hash, RO_SDA_ANCHOR_NAME, false, false, true);
++  if (h != (struct bfd_link_hash_entry *) NULL
++      && h->type == bfd_link_hash_defined)
++    ro_small_data_pointer = (h->u.def.value
++                            + h->u.def.section->output_section->vma
++                            + h->u.def.section->output_offset);
++
++  h = bfd_link_hash_lookup (info->hash, RW_SDA_ANCHOR_NAME, false, false, true);
++  if (h != (struct bfd_link_hash_entry *) NULL
++      && h->type == bfd_link_hash_defined)
++    rw_small_data_pointer = (h->u.def.value
++                            + h->u.def.section->output_section->vma
++                            + h->u.def.section->output_offset);
++}
++
++static bfd_vma
++dtprel_base (struct bfd_link_info *info)
++{
++  /* If tls_sec is NULL, we should have signalled an error already.  */
++  if (elf_hash_table (info)->tls_sec == NULL)
++    return 0;
++  return elf_hash_table (info)->tls_sec->vma;
++}
++
++/* The size of the thread control block.  */
++#define TCB_SIZE       8
++
++/* Output a simple dynamic relocation into SRELOC.  */
++
++static void
++microblaze_elf_output_dynamic_relocation (bfd *output_bfd,
++                                         asection *sreloc,
++                                         unsigned long reloc_index,
++                                         unsigned long indx,
++                                         int r_type,
++                                         bfd_vma offset,
++                                         bfd_vma addend)
++{
++
++  Elf_Internal_Rela rel;
++
++  rel.r_info = ELF64_R_INFO (indx, r_type);
++  rel.r_offset = offset;
++  rel.r_addend = addend;
++
++  bfd_elf64_swap_reloca_out (output_bfd, &rel,
++              (sreloc->contents + reloc_index * sizeof (Elf64_External_Rela)));
++}
++
++/* This code is taken from elf64-m32r.c
++   There is some attempt to make this function usable for many architectures,
++   both USE_REL and USE_RELA ['twould be nice if such a critter existed],
++   if only to serve as a learning tool.
++
++   The RELOCATE_SECTION function is called by the new ELF backend linker
++   to handle the relocations for a section.
++
++   The relocs are always passed as Rela structures; if the section
++   actually uses Rel structures, the r_addend field will always be
++   zero.
++
++   This function is responsible for adjust the section contents as
++   necessary, and (if using Rela relocs and generating a
++   relocatable output file) adjusting the reloc addend as
++   necessary.
++
++   This function does not have to worry about setting the reloc
++   address or the reloc symbol index.
++
++   LOCAL_SYMS is a pointer to the swapped in local symbols.
++
++   LOCAL_SECTIONS is an array giving the section in the input file
++   corresponding to the st_shndx field of each local symbol.
++
++   The global hash table entry for the global symbols can be found
++   via elf_sym_hashes (input_bfd).
++
++   When generating relocatable output, this function must handle
++   STB_LOCAL/STT_SECTION symbols specially.  The output symbol is
++   going to be the section symbol corresponding to the output
++   section, which means that the addend must be adjusted
++   accordingly.  */
++
++static int
++microblaze_elf_relocate_section (bfd *output_bfd,
++                                struct bfd_link_info *info,
++                                bfd *input_bfd,
++                                asection *input_section,
++                                bfd_byte *contents,
++                                Elf_Internal_Rela *relocs,
++                                Elf_Internal_Sym *local_syms,
++                                asection **local_sections)
++{
++  struct elf64_mb_link_hash_table *htab;
++  Elf_Internal_Shdr *symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
++  struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd);
++  Elf_Internal_Rela *rel, *relend;
++  int endian = (bfd_little_endian (output_bfd)) ? 0 : 2;
++  /* Assume success.  */
++  bool ret = true;
++  asection *sreloc;
++  bfd_vma *local_got_offsets;
++  unsigned int tls_type;
++
++  if (!microblaze_elf_howto_table[R_MICROBLAZE_max-1])
++    microblaze_elf_howto_init ();
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return false;
++
++  local_got_offsets = elf_local_got_offsets (input_bfd);
++
++  sreloc = elf_section_data (input_section)->sreloc;
++
++  rel = relocs;
++  relend = relocs + input_section->reloc_count;
++  for (; rel < relend; rel++)
++    {
++      int r_type;
++      reloc_howto_type *howto;
++      unsigned long r_symndx;
++      bfd_vma addend = rel->r_addend;
++      bfd_vma offset = rel->r_offset;
++      struct elf_link_hash_entry *h;
++      Elf_Internal_Sym *sym;
++      asection *sec;
++      const char *sym_name;
++      bfd_reloc_status_type r = bfd_reloc_ok;
++      const char *errmsg = NULL;
++      bool unresolved_reloc = false;
++
++      h = NULL;
++      r_type = ELF64_R_TYPE (rel->r_info);
++      tls_type = 0;
++
++      if (r_type < 0 || r_type >= (int) R_MICROBLAZE_max)
++       {
++         /* xgettext:c-format */
++         _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
++                             input_bfd, (int) r_type);
++         bfd_set_error (bfd_error_bad_value);
++         ret = false;
++         continue;
++       }
++
++      howto = microblaze_elf_howto_table[r_type];
++      r_symndx = ELF64_R_SYM (rel->r_info);
++
++      if (bfd_link_relocatable (info))
++       {
++         /* This is a relocatable link.  We don't have to change
++            anything, unless the reloc is against a section symbol,
++            in which case we have to adjust according to where the
++            section symbol winds up in the output section.  */
++         sec = NULL;
++         if (r_symndx >= symtab_hdr->sh_info)
++           /* External symbol.  */
++           continue;
++
++         /* Local symbol.  */
++         sym = local_syms + r_symndx;
++         sym_name = "<local symbol>";
++         /* STT_SECTION: symbol is associated with a section.  */
++         if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
++           /* Symbol isn't associated with a section.  Nothing to do.  */
++           continue;
++
++         sec = local_sections[r_symndx];
++         addend += sec->output_offset + sym->st_value;
++#ifndef USE_REL
++         /* This can't be done for USE_REL because it doesn't mean anything
++            and elf_link_input_bfd asserts this stays zero.  */
++         /* rel->r_addend = addend; */
++#endif
++
++#ifndef USE_REL
++         /* Addends are stored with relocs.  We're done.  */
++         continue;
++#else /* USE_REL */
++         /* If partial_inplace, we need to store any additional addend
++            back in the section.  */
++         if (!howto->partial_inplace)
++           continue;
++         /* ??? Here is a nice place to call a special_function like handler.  */
++         r = _bfd_relocate_contents (howto, input_bfd, addend,
++                                     contents + offset);
++#endif /* USE_REL */
++       }
++      else
++       {
++         bfd_vma relocation;
++         bool resolved_to_zero;
++
++         /* This is a final link.  */
++         sym = NULL;
++         sec = NULL;
++         unresolved_reloc = false;
++
++         if (r_symndx < symtab_hdr->sh_info)
++           {
++             /* Local symbol.  */
++             sym = local_syms + r_symndx;
++             sec = local_sections[r_symndx];
++             if (sec == 0)
++               continue;
++             sym_name = "<local symbol>";
++             relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
++             /* r_addend may have changed if the reference section was
++                a merge section.  */
++             addend = rel->r_addend;
++           }
++         else
++           {
++             /* External symbol.  */
++             bool warned ATTRIBUTE_UNUSED;
++             bool ignored ATTRIBUTE_UNUSED;
++
++             RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
++                                      r_symndx, symtab_hdr, sym_hashes,
++                                      h, sec, relocation,
++                                      unresolved_reloc, warned, ignored);
++             sym_name = h->root.root.string;
++           }
++
++         /* Sanity check the address.  */
++         if (offset > bfd_get_section_limit (input_bfd, input_section))
++           {
++             r = bfd_reloc_outofrange;
++             goto check_reloc;
++           }
++
++         resolved_to_zero = (h != NULL
++                             && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
++
++         switch ((int) r_type)
++           {
++           case (int) R_MICROBLAZE_SRO32 :
++             {
++               const char *name;
++
++               /* Only relocate if the symbol is defined.  */
++               if (sec)
++                 {
++                   name = bfd_section_name (sec);
++
++                   if (strcmp (name, ".sdata2") == 0
++                       || strcmp (name, ".sbss2") == 0)
++                     {
++                       if (ro_small_data_pointer == 0)
++                         microblaze_elf_final_sdp (info);
++                       if (ro_small_data_pointer == 0)
++                         {
++                           ret = false;
++                           r = bfd_reloc_undefined;
++                           goto check_reloc;
++                         }
++
++                       /* At this point `relocation' contains the object's
++                          address.  */
++                       relocation -= ro_small_data_pointer;
++                       /* Now it contains the offset from _SDA2_BASE_.  */
++                       r = _bfd_final_link_relocate (howto, input_bfd,
++                                                     input_section,
++                                                     contents, offset,
++                                                     relocation, addend);
++                     }
++                   else
++                     {
++                       _bfd_error_handler
++                         /* xgettext:c-format */
++                         (_("%pB: the target (%s) of an %s relocation"
++                            " is in the wrong section (%pA)"),
++                          input_bfd,
++                          sym_name,
++                          microblaze_elf_howto_table[(int) r_type]->name,
++                          sec);
++                       /*bfd_set_error (bfd_error_bad_value); ??? why? */
++                       ret = false;
++                       continue;
++                     }
++                 }
++             }
++             break;
++
++           case (int) R_MICROBLAZE_SRW32 :
++             {
++               const char *name;
++
++               /* Only relocate if the symbol is defined.  */
++               if (sec)
++                 {
++                   name = bfd_section_name (sec);
++
++                   if (strcmp (name, ".sdata") == 0
++                       || strcmp (name, ".sbss") == 0)
++                     {
++                       if (rw_small_data_pointer == 0)
++                         microblaze_elf_final_sdp (info);
++                       if (rw_small_data_pointer == 0)
++                         {
++                           ret = false;
++                           r = bfd_reloc_undefined;
++                           goto check_reloc;
++                         }
++
++                       /* At this point `relocation' contains the object's
++                          address.  */
++                       relocation -= rw_small_data_pointer;
++                       /* Now it contains the offset from _SDA_BASE_.  */
++                       r = _bfd_final_link_relocate (howto, input_bfd,
++                                                     input_section,
++                                                     contents, offset,
++                                                     relocation, addend);
++                     }
++                   else
++                     {
++                       _bfd_error_handler
++                         /* xgettext:c-format */
++                         (_("%pB: the target (%s) of an %s relocation"
++                            " is in the wrong section (%pA)"),
++                          input_bfd,
++                          sym_name,
++                          microblaze_elf_howto_table[(int) r_type]->name,
++                          sec);
++                       /*bfd_set_error (bfd_error_bad_value); ??? why? */
++                       ret = false;
++                       continue;
++                     }
++                 }
++             }
++             break;
++
++           case (int) R_MICROBLAZE_32_SYM_OP_SYM:
++             break; /* Do nothing.  */
++
++           case (int) R_MICROBLAZE_GOTPC_64:
++             relocation = (htab->elf.sgotplt->output_section->vma
++                           + htab->elf.sgotplt->output_offset);
++             relocation -= (input_section->output_section->vma
++                            + input_section->output_offset
++                            + offset + INST_WORD_SIZE);
++             relocation += addend;
++             bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++                         contents + offset + endian);
++             bfd_put_16 (input_bfd, relocation & 0xffff,
++                         contents + offset + endian + INST_WORD_SIZE);
++             break;
++
++           case (int) R_MICROBLAZE_TEXTPCREL_64:
++             relocation = input_section->output_section->vma;
++             relocation -= (input_section->output_section->vma
++                            + input_section->output_offset
++                            + offset + INST_WORD_SIZE);
++             relocation += addend;
++             bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++                         contents + offset + endian);
++             bfd_put_16 (input_bfd, relocation & 0xffff,
++                         contents + offset + endian + INST_WORD_SIZE);
++             break;
++
++           case (int) R_MICROBLAZE_PLT_64:
++             {
++               bfd_vma immediate;
++               if (htab->elf.splt != NULL && h != NULL
++                   && h->plt.offset != (bfd_vma) -1)
++                 {
++                   relocation = (htab->elf.splt->output_section->vma
++                                 + htab->elf.splt->output_offset
++                                 + h->plt.offset);
++                   unresolved_reloc = false;
++                   immediate = relocation - (input_section->output_section->vma
++                                             + input_section->output_offset
++                                             + offset + INST_WORD_SIZE);
++                   bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff,
++                               contents + offset + endian);
++                   bfd_put_16 (input_bfd, immediate & 0xffff,
++                               contents + offset + endian + INST_WORD_SIZE);
++                 }
++               else
++                 {
++                   relocation -= (input_section->output_section->vma
++                                  + input_section->output_offset
++                                  + offset + INST_WORD_SIZE);
++                   immediate = relocation;
++                   bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff,
++                               contents + offset + endian);
++                   bfd_put_16 (input_bfd, immediate & 0xffff,
++                               contents + offset + endian + INST_WORD_SIZE);
++                 }
++               break;
++             }
++
++           case (int) R_MICROBLAZE_TLSGD:
++             tls_type = (TLS_TLS | TLS_GD);
++             goto dogot;
++           case (int) R_MICROBLAZE_TLSLD:
++             tls_type = (TLS_TLS | TLS_LD);
++             /* Fall through.  */
++           dogot:
++           case (int) R_MICROBLAZE_GOT_64:
++             {
++               bfd_vma *offp;
++               bfd_vma off, off2;
++               unsigned long indx;
++               bfd_vma static_value;
++
++               bool need_relocs = false;
++               if (htab->elf.sgot == NULL)
++                 abort ();
++
++               indx = 0;
++               offp = NULL;
++
++               /* 1. Identify GOT Offset;
++                  2. Compute Static Values
++                  3. Process Module Id, Process Offset
++                  4. Fixup Relocation with GOT offset value. */
++
++               /* 1. Determine GOT Offset to use : TLS_LD, global, local */
++               if (IS_TLS_LD (tls_type))
++                 offp = &htab->tlsld_got.offset;
++               else if (h != NULL)
++                 {
++                   if (htab->elf.sgotplt != NULL
++                       && h->got.offset != (bfd_vma) -1)
++                     offp = &h->got.offset;
++                   else
++                     abort ();
++                 }
++               else
++                 {
++                   if (local_got_offsets == NULL)
++                     abort ();
++                   offp = &local_got_offsets[r_symndx];
++                 }
++
++               if (!offp)
++                 abort ();
++
++               off = (*offp) & ~1;
++               off2 = off;
++
++               if (IS_TLS_LD(tls_type) || IS_TLS_GD(tls_type))
++                 off2 = off + 4;
++
++               /* Symbol index to use for relocs */
++               if (h != NULL)
++                 {
++                   bool dyn =
++                       elf_hash_table (info)->dynamic_sections_created;
++
++                   if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
++                                                        bfd_link_pic (info),
++                                                        h)
++                       && (!bfd_link_pic (info)
++                           || !SYMBOL_REFERENCES_LOCAL (info, h)))
++                     indx = h->dynindx;
++                 }
++
++               /* Need to generate relocs ? */
++               if ((bfd_link_pic (info) || indx != 0)
++                   && (h == NULL
++                   || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
++                   || h->root.type != bfd_link_hash_undefweak))
++                 need_relocs = true;
++
++               /* 2. Compute/Emit Static value of r-expression */
++               static_value = relocation + addend;
++
++               /* 3. Process module-id and offset */
++               if (! ((*offp) & 1) )
++                 {
++                   bfd_vma got_offset;
++
++                   got_offset = (htab->elf.sgot->output_section->vma
++                                 + htab->elf.sgot->output_offset
++                                 + off);
++
++                   /* Process module-id */
++                   if (IS_TLS_LD(tls_type))
++                     {
++                       if (! bfd_link_pic (info))
++                         bfd_put_32 (output_bfd, 1,
++                                     htab->elf.sgot->contents + off);
++                       else
++                         microblaze_elf_output_dynamic_relocation
++                           (output_bfd,
++                            htab->elf.srelgot,
++                            htab->elf.srelgot->reloc_count++,
++                            /* symindex= */ 0, R_MICROBLAZE_TLSDTPMOD32,
++                            got_offset, 0);
++                     }
++                   else if (IS_TLS_GD(tls_type))
++                     {
++                       if (! need_relocs)
++                         bfd_put_32 (output_bfd, 1,
++                                     htab->elf.sgot->contents + off);
++                       else
++                         microblaze_elf_output_dynamic_relocation
++                           (output_bfd,
++                            htab->elf.srelgot,
++                            htab->elf.srelgot->reloc_count++,
++                            /* symindex= */ indx, R_MICROBLAZE_TLSDTPMOD32,
++                            got_offset, indx ? 0 : static_value);
++                     }
++
++                   /* Process Offset */
++                   if (htab->elf.srelgot == NULL)
++                     abort ();
++
++                   got_offset = (htab->elf.sgot->output_section->vma
++                                 + htab->elf.sgot->output_offset
++                                 + off2);
++                   if (IS_TLS_LD(tls_type))
++                     {
++                       /* For LD, offset should be 0 */
++                       *offp |= 1;
++                       bfd_put_32 (output_bfd, 0,
++                                   htab->elf.sgot->contents + off2);
++                     }
++                   else if (IS_TLS_GD(tls_type))
++                     {
++                       *offp |= 1;
++                       static_value -= dtprel_base(info);
++                       if (need_relocs)
++                         microblaze_elf_output_dynamic_relocation
++                           (output_bfd,
++                            htab->elf.srelgot,
++                            htab->elf.srelgot->reloc_count++,
++                            /* symindex= */ indx, R_MICROBLAZE_TLSDTPREL32,
++                            got_offset, indx ? 0 : static_value);
++                       else
++                         bfd_put_32 (output_bfd, static_value,
++                                     htab->elf.sgot->contents + off2);
++                     }
++                   else
++                     {
++                       bfd_put_32 (output_bfd, static_value,
++                                   htab->elf.sgot->contents + off2);
++
++                       /* Relocs for dyn symbols generated by
++                          finish_dynamic_symbols */
++                       if (bfd_link_pic (info) && h == NULL)
++                         {
++                           *offp |= 1;
++                           microblaze_elf_output_dynamic_relocation
++                             (output_bfd,
++                              htab->elf.srelgot,
++                              htab->elf.srelgot->reloc_count++,
++                              /* symindex= */ indx, R_MICROBLAZE_REL,
++                              got_offset, static_value);
++                         }
++                     }
++                 }
++
++               /* 4. Fixup Relocation with GOT offset value
++                     Compute relative address of GOT entry for applying
++                     the current relocation */
++               relocation = htab->elf.sgot->output_section->vma
++                            + htab->elf.sgot->output_offset
++                            + off
++                            - htab->elf.sgotplt->output_section->vma
++                            - htab->elf.sgotplt->output_offset;
++
++               /* Apply Current Relocation */
++               bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++                           contents + offset + endian);
++               bfd_put_16 (input_bfd, relocation & 0xffff,
++                           contents + offset + endian + INST_WORD_SIZE);
++
++               unresolved_reloc = false;
++               break;
++             }
++
++           case (int) R_MICROBLAZE_GOTOFF_64:
++             {
++               bfd_vma immediate;
++               unsigned short lo, high;
++               relocation += addend;
++               relocation -= (htab->elf.sgotplt->output_section->vma
++                              + htab->elf.sgotplt->output_offset);
++               /* Write this value into correct location.  */
++               immediate = relocation;
++               lo = immediate & 0x0000ffff;
++               high = (immediate >> 16) & 0x0000ffff;
++               bfd_put_16 (input_bfd, high, contents + offset + endian);
++               bfd_put_16 (input_bfd, lo,
++                           contents + offset + INST_WORD_SIZE + endian);
++               break;
++             }
++
++           case (int) R_MICROBLAZE_GOTOFF_32:
++             {
++               relocation += addend;
++               relocation -= (htab->elf.sgotplt->output_section->vma
++                              + htab->elf.sgotplt->output_offset);
++               /* Write this value into correct location.  */
++               bfd_put_32 (input_bfd, relocation, contents + offset);
++               break;
++             }
++
++           case (int) R_MICROBLAZE_TLSDTPREL64:
++             relocation += addend;
++             relocation -= dtprel_base(info);
++             bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++                         contents + offset + endian);
++             bfd_put_16 (input_bfd, relocation & 0xffff,
++                         contents + offset + endian + INST_WORD_SIZE);
++             break;
++           case (int) R_MICROBLAZE_TEXTREL_64:
++           case (int) R_MICROBLAZE_TEXTREL_32_LO:
++           case (int) R_MICROBLAZE_64_PCREL :
++           case (int) R_MICROBLAZE_64:
++           case (int) R_MICROBLAZE_32:
++           case (int) R_MICROBLAZE_IMML_64:
++             {
++               /* r_symndx will be STN_UNDEF (zero) only for relocs against symbols
++                  from removed linkonce sections, or sections discarded by
++                  a linker script.  */
++               if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0)
++                 {
++                   relocation += addend;
++                   if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64)
++                     bfd_put_32 (input_bfd, relocation, contents + offset);
++                   else if (r_type == R_MICROBLAZE_IMML_64)
++                     bfd_put_64 (input_bfd, relocation, contents + offset);
++                   else
++                     {
++                       if (r_type == R_MICROBLAZE_64_PCREL)
++                         relocation -= (input_section->output_section->vma
++                                        + input_section->output_offset
++                                        + offset + INST_WORD_SIZE);
++                       else if (r_type == R_MICROBLAZE_TEXTREL_64
++                                || r_type == R_MICROBLAZE_TEXTREL_32_LO)
++                         relocation -= input_section->output_section->vma;
++
++                       if (r_type == R_MICROBLAZE_TEXTREL_32_LO)
++                         bfd_put_16 (input_bfd, relocation & 0xffff,
++                                     contents + offset + endian);
++
++                       unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
++                       if ((insn & 0xff000000) == 0xb2000000)
++                         {
++                           insn &= ~0x00ffffff;
++                           insn |= (relocation >> 16) & 0xffffff;
++                           bfd_put_32 (input_bfd, insn,
++                                   contents + offset + endian);
++                         }
++                       else
++                         bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++                                     contents + offset + endian);
++                       bfd_put_16 (input_bfd, relocation & 0xffff,
++                                   contents + offset + endian + INST_WORD_SIZE);
++                     }
++                   break;
++                 }
++
++               if ((bfd_link_pic (info)
++                    && (h == NULL
++                        || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
++                            && !resolved_to_zero)
++                        || h->root.type != bfd_link_hash_undefweak)
++                    && (!howto->pc_relative
++                        || (h != NULL
++                            && h->dynindx != -1
++                            && (!info->symbolic
++                                || !h->def_regular))))
++                   || (!bfd_link_pic (info)
++                       && h != NULL
++                       && h->dynindx != -1
++                       && !h->non_got_ref
++                       && ((h->def_dynamic
++                            && !h->def_regular)
++                           || h->root.type == bfd_link_hash_undefweak
++                           || h->root.type == bfd_link_hash_undefined)))
++                 {
++                   Elf_Internal_Rela outrel;
++                   bfd_byte *loc;
++                   bool skip;
++
++                   /* When generating a shared object, these relocations
++                      are copied into the output file to be resolved at run
++                      time.  */
++
++                   BFD_ASSERT (sreloc != NULL);
++
++                   skip = false;
++
++                   outrel.r_offset =
++                     _bfd_elf_section_offset (output_bfd, info, input_section,
++                                              rel->r_offset);
++                   if (outrel.r_offset == (bfd_vma) -1)
++                     skip = true;
++                   else if (outrel.r_offset == (bfd_vma) -2)
++                     skip = true;
++                   outrel.r_offset += (input_section->output_section->vma
++                                       + input_section->output_offset);
++
++                   if (skip)
++                     memset (&outrel, 0, sizeof outrel);
++                   /* h->dynindx may be -1 if the symbol was marked to
++                      become local.  */
++                   else if (h != NULL
++                            && ((! info->symbolic && h->dynindx != -1)
++                                || !h->def_regular))
++                     {
++                       BFD_ASSERT (h->dynindx != -1);
++                       outrel.r_info = ELF64_R_INFO (h->dynindx, r_type);
++                       outrel.r_addend = addend;
++                     }
++                   else
++                     {
++                       if (r_type == R_MICROBLAZE_32 || r_type == R_MICROBLAZE_IMML_64)
++                         {
++                           outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL);
++                           outrel.r_addend = relocation + addend;
++                         }
++                       else
++                         {
++                           BFD_FAIL ();
++                           _bfd_error_handler
++                             (_("%pB: probably compiled without -fPIC?"),
++                              input_bfd);
++                           bfd_set_error (bfd_error_bad_value);
++                           return false;
++                         }
++                     }
++
++                   loc = sreloc->contents;
++                   loc += sreloc->reloc_count++ * sizeof (Elf64_External_Rela);
++                   bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
++                   break;
++                 }
++               else
++                 {
++                   relocation += addend;
++                   if (r_type == R_MICROBLAZE_32)
++                     bfd_put_32 (input_bfd, relocation, contents + offset);
++                   else if (r_type == R_MICROBLAZE_IMML_64)
++                     bfd_put_64 (input_bfd, relocation, contents + offset + endian);
++                   else
++                     {
++                       if (r_type == R_MICROBLAZE_64_PCREL)
++                       {       
++                       if (!input_section->output_section->vma &&
++                                !input_section->output_offset && !offset)      
++                             relocation -= (input_section->output_section->vma
++                                            + input_section->output_offset
++                                            + offset);
++                           else
++                         relocation -= (input_section->output_section->vma
++                                        + input_section->output_offset + offset + INST_WORD_SIZE);
++                       }
++                       else if (r_type == R_MICROBLAZE_TEXTREL_64
++                                || r_type == R_MICROBLAZE_TEXTREL_32_LO)
++                         relocation -= input_section->output_section->vma;
++
++                       if (r_type == R_MICROBLAZE_TEXTREL_32_LO)
++                         {
++                            bfd_put_16 (input_bfd, relocation & 0xffff,
++                                        contents + offset + endian);
++                         }
++                       unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
++                       if ((insn & 0xff000000) == 0xb2000000)
++                          {
++                            insn &= ~0x00ffffff;
++                            insn |= (relocation >> 16) & 0xffffff;
++                            bfd_put_32 (input_bfd, insn,
++                                    contents + offset + endian);
++                          }
++                       else
++                         bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++                                     contents + offset + endian);
++                       bfd_put_16 (input_bfd, relocation & 0xffff,
++                                   contents + offset + endian + INST_WORD_SIZE);
++                     }
++                   break;
++                 }
++             }
++
++           default :
++             r = _bfd_final_link_relocate (howto, input_bfd, input_section,
++                                           contents, offset,
++                                           relocation, addend);
++             break;
++           }
++       }
++
++    check_reloc:
++
++      if (r != bfd_reloc_ok)
++       {
++         /* FIXME: This should be generic enough to go in a utility.  */
++         const char *name;
++
++         if (h != NULL)
++           name = h->root.root.string;
++         else
++           {
++             name = (bfd_elf_string_from_elf_section
++                     (input_bfd, symtab_hdr->sh_link, sym->st_name));
++             if (name == NULL || *name == '\0')
++               name = bfd_section_name (sec);
++           }
++
++         if (errmsg != NULL)
++           goto common_error;
++
++         switch (r)
++           {
++           case bfd_reloc_overflow:
++             (*info->callbacks->reloc_overflow)
++               (info, (h ? &h->root : NULL), name, howto->name,
++                (bfd_vma) 0, input_bfd, input_section, offset);
++             break;
++
++           case bfd_reloc_undefined:
++             (*info->callbacks->undefined_symbol)
++               (info, name, input_bfd, input_section, offset, true);
++             break;
++
++           case bfd_reloc_outofrange:
++             errmsg = _("internal error: out of range error");
++             goto common_error;
++
++           case bfd_reloc_notsupported:
++             errmsg = _("internal error: unsupported relocation error");
++             goto common_error;
++
++           case bfd_reloc_dangerous:
++             errmsg = _("internal error: dangerous error");
++             goto common_error;
++
++           default:
++             errmsg = _("internal error: unknown error");
++             /* Fall through.  */
++           common_error:
++             (*info->callbacks->warning) (info, errmsg, name, input_bfd,
++                                          input_section, offset);
++             break;
++           }
++       }
++    }
++
++  return ret;
++}
++
++/* Merge backend specific data from an object file to the output
++   object file when linking.
++
++   Note: We only use this hook to catch endian mismatches.  */
++static bool
++microblaze_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
++{
++  /* Check if we have the same endianess.  */
++  if (! _bfd_generic_verify_endian_match (ibfd, obfd))
++    return false;
++
++  return true;
++}
++
++
++/* Calculate fixup value for reference.  */
++
++static size_t
++calc_fixup (bfd_vma start, bfd_vma size, asection *sec)
++{
++  bfd_vma end = start + size;
++  size_t i, fixup = 0;
++  struct _microblaze_elf_section_data *sdata;
++
++  if (sec == NULL || (sdata = microblaze_elf_section_data (sec)) == NULL)
++    return 0;
++
++  /* Look for addr in relax table, total fixup value.  */
++  for (i = 0; i < sdata->relax_count; i++)
++    {
++      if (end <= sdata->relax[i].addr)
++       break;
++      if (end != start && start > sdata->relax[i].addr)
++       continue;
++      fixup += sdata->relax[i].size;
++    }
++  return fixup;
++}
++
++/* Read-modify-write into the bfd, an immediate value into appropriate fields of
++   a 32-bit instruction.  */
++static void
++microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
++{
++    unsigned long instr = bfd_get_32 (abfd, bfd_addr);
++
++    if ((instr & 0xff000000) == 0xb2000000)
++      {
++        instr &= ~0x00ffffff;
++        instr |= (val & 0xffffff);
++        bfd_put_32 (abfd, instr, bfd_addr);
++      }
++    else
++      {
++        instr &= ~0x0000ffff;
++        instr |= (val & 0x0000ffff);
++        bfd_put_32 (abfd, instr, bfd_addr);
++      }
++}
++
++/* Read-modify-write into the bfd, an immediate value into appropriate fields of
++   two consecutive 32-bit instructions.  */
++static void
++microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
++{
++    unsigned long instr_hi;
++    unsigned long instr_lo;
++
++    instr_hi = bfd_get_32 (abfd, bfd_addr);
++    if ((instr_hi & 0xff000000) == 0xb2000000)
++      {
++        instr_hi &= ~0x00ffffff;
++        instr_hi |= (val >> 16) & 0xffffff;
++        bfd_put_32 (abfd, instr_hi,bfd_addr);
++      }
++    else
++      {
++        instr_hi &= ~0x0000ffff;
++        instr_hi |= ((val >> 16) & 0x0000ffff);
++        bfd_put_32 (abfd, instr_hi, bfd_addr);
++      }
++    instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE);
++    instr_lo &= ~0x0000ffff;
++    instr_lo |= (val & 0x0000ffff);
++    bfd_put_32 (abfd, instr_lo, bfd_addr + INST_WORD_SIZE);
++}
++
++static bool
++microblaze_elf_relax_section (bfd *abfd,
++                             asection *sec,
++                             struct bfd_link_info *link_info,
++                             bool *again)
++{
++  Elf_Internal_Shdr *symtab_hdr;
++  Elf_Internal_Rela *internal_relocs;
++  Elf_Internal_Rela *irel, *irelend;
++  bfd_byte *contents = NULL;
++  int rel_count;
++  unsigned int shndx;
++  size_t i, sym_index;
++  asection *o;
++  struct elf_link_hash_entry *sym_hash;
++  Elf_Internal_Sym *isymbuf, *isymend;
++  Elf_Internal_Sym *isym;
++  size_t symcount;
++  size_t offset;
++  bfd_vma src, dest;
++  struct _microblaze_elf_section_data *sdata;
++
++  /* We only do this once per section.  We may be able to delete some code
++     by running multiple passes, but it is not worth it.  */
++  *again = false;
++
++  /* Only do this for a text section.  */
++  if (bfd_link_relocatable (link_info)
++      || (sec->flags & SEC_RELOC) == 0
++      || (sec->flags & SEC_CODE) == 0
++      || sec->reloc_count == 0
++      || (sdata = microblaze_elf_section_data (sec)) == NULL)
++    return true;
++
++  BFD_ASSERT ((sec->size > 0) || (sec->rawsize > 0));
++
++  /* If this is the first time we have been called for this section,
++     initialize the cooked size.  */
++  if (sec->size == 0)
++    sec->size = sec->rawsize;
++
++  /* Get symbols for this section.  */
++  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
++  isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
++  symcount =  symtab_hdr->sh_size / sizeof (Elf64_External_Sym);
++  if (isymbuf == NULL)
++    isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, symcount,
++                                   0, NULL, NULL, NULL);
++  BFD_ASSERT (isymbuf != NULL);
++
++  internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory);
++  if (internal_relocs == NULL)
++    goto error_return;
++
++  sdata->relax_count = 0;
++  sdata->relax = (struct relax_table *) bfd_malloc ((sec->reloc_count + 1)
++                                                   * sizeof (*sdata->relax));
++  if (sdata->relax == NULL)
++    goto error_return;
++
++  irelend = internal_relocs + sec->reloc_count;
++  rel_count = 0;
++  for (irel = internal_relocs; irel < irelend; irel++, rel_count++)
++    {
++      bfd_vma symval;
++      if ((ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64_PCREL)
++         && (ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64 )
++&& (ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_TEXTREL_64))
++       continue; /* Can't delete this reloc.  */
++
++      /* Get the section contents.  */
++      if (contents == NULL)
++       {
++         if (elf_section_data (sec)->this_hdr.contents != NULL)
++           contents = elf_section_data (sec)->this_hdr.contents;
++         else
++           {
++             contents = (bfd_byte *) bfd_malloc (sec->size);
++             if (contents == NULL)
++               goto error_return;
++             if (!bfd_get_section_contents (abfd, sec, contents,
++                                            (file_ptr) 0, sec->size))
++               goto error_return;
++              elf_section_data (sec)->this_hdr.contents = contents;
++           }
++       }
++
++      /* Get the value of the symbol referred to by the reloc.  */
++      if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info)
++       {
++         /* A local symbol.  */
++         asection *sym_sec;
++
++         isym = isymbuf + ELF64_R_SYM (irel->r_info);
++          if (isym->st_shndx == SHN_UNDEF)
++           sym_sec = bfd_und_section_ptr;
++         else if (isym->st_shndx == SHN_ABS)
++           sym_sec = bfd_abs_section_ptr;
++         else if (isym->st_shndx == SHN_COMMON)
++           sym_sec = bfd_com_section_ptr;
++         else
++           sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
++
++         symval = _bfd_elf_rela_local_sym (abfd, isym, &sym_sec, irel);
++       }
++      else
++       {
++         unsigned long indx;
++         struct elf_link_hash_entry *h;
++
++         indx = ELF64_R_SYM (irel->r_info) - symtab_hdr->sh_info;
++         h = elf_sym_hashes (abfd)[indx];
++         BFD_ASSERT (h != NULL);
++
++          if (h->root.type != bfd_link_hash_defined
++             && h->root.type != bfd_link_hash_defweak)
++           /* This appears to be a reference to an undefined
++              symbol.  Just ignore it--it will be caught by the
++              regular reloc processing.  */
++           continue;
++
++         symval = (h->root.u.def.value
++                   + h->root.u.def.section->output_section->vma
++                   + h->root.u.def.section->output_offset);
++       }
++
++      /* If this is a PC-relative reloc, subtract the instr offset from
++         the symbol value.  */
++      if (ELF64_R_TYPE (irel->r_info) == (int) R_MICROBLAZE_64_PCREL)
++       {
++         symval = symval + irel->r_addend
++           - (irel->r_offset
++              + sec->output_section->vma
++              + sec->output_offset);
++        }
++      else if (ELF64_R_TYPE (irel->r_info) == (int) R_MICROBLAZE_TEXTREL_64)
++       {
++         symval = symval + irel->r_addend - (sec->output_section->vma);
++       }
++      else
++       symval += irel->r_addend;
++
++      if ((symval & 0xffff8000) == 0
++         || (symval & 0xffff8000) == 0xffff8000)
++       {
++         /* We can delete this instruction.  */
++         sdata->relax[sdata->relax_count].addr = irel->r_offset;
++         sdata->relax[sdata->relax_count].size = INST_WORD_SIZE;
++         sdata->relax_count++;
++
++         /* Rewrite relocation type.  */
++          switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info))
++           {
++           case R_MICROBLAZE_64_PCREL:
++             irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),
++                                           (int) R_MICROBLAZE_32_PCREL_LO);
++             break;
++           case R_MICROBLAZE_64:
++              irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),
++                                           (int) R_MICROBLAZE_32_LO);
++             break;
++           case R_MICROBLAZE_TEXTREL_64:
++             irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),
++                                          (int) R_MICROBLAZE_TEXTREL_32_LO);
++             break;
++           default:
++             /* Cannot happen.  */
++             BFD_ASSERT (false);
++            }
++        }
++    } /* Loop through all relocations.  */
++
++  /* Loop through the relocs again, and see if anything needs to change.  */
++  if (sdata->relax_count > 0)
++    {
++      shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
++      rel_count = 0;
++      sdata->relax[sdata->relax_count].addr = sec->size;
++
++      for (irel = internal_relocs; irel < irelend; irel++, rel_count++)
++        {
++         bfd_vma nraddr;
++
++          /* Get the new reloc address.  */
++         nraddr = irel->r_offset - calc_fixup (irel->r_offset, 0, sec);
++          switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info))
++           {
++           default:
++             break;
++           case R_MICROBLAZE_64_PCREL:
++             break;
++           case R_MICROBLAZE_64:
++           case R_MICROBLAZE_32_LO:
++             /* If this reloc is against a symbol defined in this
++                section, we must check the addend to see it will put the value in
++                range to be adjusted, and hence must be changed.  */
++             if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info)
++               {
++                 isym = isymbuf + ELF64_R_SYM (irel->r_info);
++                 /* Only handle relocs against .text.  */
++                 if (isym->st_shndx == shndx
++                     && ELF64_ST_TYPE (isym->st_info) == STT_SECTION)
++                   irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
++               }
++             break;
++           case R_MICROBLAZE_IMML_64:
++             {
++               /* This was a PC-relative instruction that was
++                  completely resolved.  */
++               int sfix, efix;
++            unsigned int val;
++               bfd_vma target_address;
++               target_address = irel->r_addend + irel->r_offset;
++               sfix = calc_fixup (irel->r_offset, 0, sec);
++               efix = calc_fixup (target_address, 0, sec);
++
++            /* Validate the in-band val.  */
++            val = bfd_get_64 (abfd, contents + irel->r_offset);
++            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++            }
++               irel->r_addend -= (efix - sfix);
++               /* Should use HOWTO.  */
++               microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
++                                                  irel->r_addend);
++             }
++             break;
++           case R_MICROBLAZE_NONE:
++           case R_MICROBLAZE_32_NONE:
++             {
++               /* This was a PC-relative instruction that was
++                  completely resolved.  */
++               size_t sfix, efix;
++                unsigned int val;
++               bfd_vma target_address;
++               target_address = irel->r_addend + irel->r_offset;
++               sfix = calc_fixup (irel->r_offset, 0, sec);
++               efix = calc_fixup (target_address, 0, sec);
++
++            /* Validate the in-band val.  */
++            val = bfd_get_32 (abfd, contents + irel->r_offset);
++            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++            }
++               irel->r_addend -= (efix - sfix);
++               /* Should use HOWTO.  */
++               microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
++                                                  irel->r_addend);
++             }
++             break;
++           case R_MICROBLAZE_64_NONE:
++             {
++               /* This was a PC-relative 64-bit instruction that was
++                  completely resolved.  */
++               size_t sfix, efix;
++               bfd_vma target_address;
++               target_address = irel->r_addend + irel->r_offset + INST_WORD_SIZE;
++               sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec);
++               efix = calc_fixup (target_address, 0, sec);
++               irel->r_addend -= (efix - sfix);
++    microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
++                                       irel->r_addend);
++             }
++             break;
++           }
++          irel->r_offset = nraddr;
++        } /* Change all relocs in this section.  */
++
++      /* Look through all other sections.  */
++      for (o = abfd->sections; o != NULL; o = o->next)
++        {
++          Elf_Internal_Rela *irelocs;
++          Elf_Internal_Rela *irelscan, *irelscanend;
++          bfd_byte *ocontents;
++
++          if (o == sec
++              || (o->flags & SEC_RELOC) == 0
++              || o->reloc_count == 0)
++            continue;
++
++          /* We always cache the relocs.  Perhaps, if info->keep_memory is
++             false, we should free them, if we are permitted to.  */
++
++          irelocs = _bfd_elf_link_read_relocs (abfd, o, NULL, NULL, true);
++          if (irelocs == NULL)
++            goto error_return;
++
++          ocontents = NULL;
++          irelscanend = irelocs + o->reloc_count;
++          for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
++            {
++              if (1 && ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
++                {
++                  unsigned int val;
++                 if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                   continue;
++
++                  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++                  /* hax: We only do the following fixup for debug location lists.  */
++                  if (strcmp(".debug_loc", o->name))
++                    continue;
++
++                  /* This was a PC-relative instruction that was completely resolved.  */
++                  if (ocontents == NULL)
++                    {
++                     if (elf_section_data (o)->this_hdr.contents != NULL)
++                         ocontents = elf_section_data (o)->this_hdr.contents;
++                     else
++                       {
++                         /* We always cache the section contents.
++                            Perhaps, if info->keep_memory is false, we
++                            should free them, if we are permitted to.  */
++
++                         if (o->rawsize == 0)
++                             o->rawsize = o->size;
++                         ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++                         if (ocontents == NULL)
++                             goto error_return;
++                         if (!bfd_get_section_contents (abfd, o, ocontents,
++                                                         (file_ptr) 0,
++                                                         o->rawsize))
++                              goto error_return;
++                         elf_section_data (o)->this_hdr.contents = ocontents;
++                       }
++                   }
++
++                  val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++                  if (val != irelscan->r_addend) {
++                    fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
++                  }
++                  irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
++                  microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++                                                     irelscan->r_addend);
++              }
++              if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32 
++                  || ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64)
++                {
++                 if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                   continue;
++
++                 isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++                  /* Look at the reloc only if the value has been resolved.  */
++                  if (isym->st_shndx == shndx
++                      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
++                    {
++                      if (ocontents == NULL)
++                        {
++                          if (elf_section_data (o)->this_hdr.contents != NULL)
++                            ocontents = elf_section_data (o)->this_hdr.contents;
++                          else
++                            {
++                              /* We always cache the section contents.
++                                 Perhaps, if info->keep_memory is false, we
++                                 should free them, if we are permitted to.  */
++                             if (o->rawsize == 0)
++                               o->rawsize = o->size;
++                              ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++                              if (ocontents == NULL)
++                                goto error_return;
++                              if (!bfd_get_section_contents (abfd, o, ocontents,
++                                                             (file_ptr) 0,
++                                                            o->rawsize))
++                                goto error_return;
++                              elf_section_data (o)->this_hdr.contents = ocontents;
++                            }
++
++                        }
++                     irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
++                    }
++                 else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_SYM_OP_SYM)
++                   {
++                      if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                        continue;
++
++                     isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++                     /* Look at the reloc only if the value has been resolved.  */
++                     if (ocontents == NULL)
++                       {
++                         if (elf_section_data (o)->this_hdr.contents != NULL)
++                           ocontents = elf_section_data (o)->this_hdr.contents;
++                         else
++                           {
++                             /* We always cache the section contents.
++                                Perhaps, if info->keep_memory is false, we
++                                should free them, if we are permitted to.  */
++
++                             if (o->rawsize == 0)
++                               o->rawsize = o->size;
++                             ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++                             if (ocontents == NULL)
++                               goto error_return;
++                             if (!bfd_get_section_contents (abfd, o, ocontents,
++                                                            (file_ptr) 0,
++                                                            o->rawsize))
++                               goto error_return;
++                             elf_section_data (o)->this_hdr.contents = ocontents;
++                           }
++                       }
++              irelscan->r_addend -= calc_fixup (irelscan->r_addend
++                                                       + isym->st_value,
++                                                       0,
++                                                       sec);
++                   }
++               }
++             else if ((ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_PCREL_LO)
++                      || (ELF32_R_TYPE (irelscan->r_info)
++                                  == (int) R_MICROBLAZE_32_LO)
++                      || (ELF32_R_TYPE (irelscan->r_info)
++                                  == (int) R_MICROBLAZE_TEXTREL_32_LO))
++               {
++                  if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                    continue;
++
++                 isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++                 /* Look at the reloc only if the value has been resolved.  */
++                 if (isym->st_shndx == shndx
++                     && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
++                   {
++                     bfd_vma immediate;
++                     bfd_vma target_address;
++
++                     if (ocontents == NULL)
++                       {
++                         if (elf_section_data (o)->this_hdr.contents != NULL)
++                           ocontents = elf_section_data (o)->this_hdr.contents;
++                         else
++                           {
++                             /* We always cache the section contents.
++                                Perhaps, if info->keep_memory is false, we
++                                should free them, if we are permitted to.  */
++                             if (o->rawsize == 0)
++                               o->rawsize = o->size;
++                             ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++                             if (ocontents == NULL)
++                               goto error_return;
++                             if (!bfd_get_section_contents (abfd, o, ocontents,
++                                                            (file_ptr) 0,
++                                                            o->rawsize))
++                               goto error_return;
++                             elf_section_data (o)->this_hdr.contents = ocontents;
++                           }
++                       }
++
++                     unsigned long instr = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++                     immediate = instr & 0x0000ffff;
++                     target_address = immediate;
++                     offset = calc_fixup (target_address, 0, sec);
++                     immediate -= offset;
++                     irelscan->r_addend -= offset;
++          microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++                                             irelscan->r_addend);
++                   }
++               }
++
++             if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64
++          || (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_TEXTREL_64))
++               {
++                  if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                    continue;
++
++                 isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++                 /* Look at the reloc only if the value has been resolved.  */
++                 if (isym->st_shndx == shndx
++                     && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
++                   {
++                     bfd_vma immediate;
++
++                     if (ocontents == NULL)
++                       {
++                         if (elf_section_data (o)->this_hdr.contents != NULL)
++                           ocontents = elf_section_data (o)->this_hdr.contents;
++                         else
++                           {
++                             /* We always cache the section contents.
++                                Perhaps, if info->keep_memory is false, we
++                                should free them, if we are permitted to.  */
++
++                             if (o->rawsize == 0)
++                               o->rawsize = o->size;
++                             ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++                             if (ocontents == NULL)
++                               goto error_return;
++                             if (!bfd_get_section_contents (abfd, o, ocontents,
++                                                            (file_ptr) 0,
++                                                            o->rawsize))
++                               goto error_return;
++                             elf_section_data (o)->this_hdr.contents = ocontents;
++                           }
++                       }
++              unsigned long instr_hi =  bfd_get_32 (abfd, ocontents
++                                                + irelscan->r_offset);
++              unsigned long instr_lo =  bfd_get_32 (abfd, ocontents
++                                                + irelscan->r_offset
++                                                + INST_WORD_SIZE);
++              if ((instr_hi & 0xff000000) == 0xb2000000)
++                immediate = (instr_hi & 0x00ffffff) << 24;
++             else
++                immediate = (instr_hi & 0x0000ffff) << 16;
++              immediate |= (instr_lo & 0x0000ffff);
++                     offset = calc_fixup (irelscan->r_addend, 0, sec);
++                     immediate -= offset;
++                     irelscan->r_addend -= offset;
++                         
++                   }
++               }
++             else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_PCREL)
++               {
++                  if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                    continue;
++
++                 isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++                 /* Look at the reloc only if the value has been resolved.  */
++                 if (isym->st_shndx == shndx
++                     && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
++                   {
++                     bfd_vma immediate;
++                     bfd_vma target_address;
++
++                     if (ocontents == NULL)
++                       {
++                         if (elf_section_data (o)->this_hdr.contents != NULL)
++                           ocontents = elf_section_data (o)->this_hdr.contents;
++                         else
++                           {
++                             /* We always cache the section contents.
++                                Perhaps, if info->keep_memory is false, we
++                                should free them, if we are permitted to.  */
++                             if (o->rawsize == 0)
++                               o->rawsize = o->size;
++                             ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++                             if (ocontents == NULL)
++                               goto error_return;
++                             if (!bfd_get_section_contents (abfd, o, ocontents,
++                                                            (file_ptr) 0,
++                                                            o->rawsize))
++                               goto error_return;
++                             elf_section_data (o)->this_hdr.contents = ocontents;
++                           }
++                       }
++          unsigned long instr_hi =  bfd_get_32 (abfd, ocontents
++                                                + irelscan->r_offset);
++          unsigned long instr_lo =  bfd_get_32 (abfd, ocontents
++                                                + irelscan->r_offset
++                                                + INST_WORD_SIZE);
++          if ((instr_hi & 0xff000000) == 0xb2000000)
++            immediate = (instr_hi & 0x00ffffff) << 24;
++         else
++            immediate = (instr_hi & 0x0000ffff) << 16;
++          immediate |= (instr_lo & 0x0000ffff);
++                     target_address = immediate;
++                     offset = calc_fixup (target_address, 0, sec);
++                     immediate -= offset;
++                     irelscan->r_addend -= offset;
++          microblaze_bfd_write_imm_value_64 (abfd, ocontents
++                                             + irelscan->r_offset, immediate);
++                   }
++               }
++            }
++        }
++
++      /* Adjust the local symbols defined in this section.  */
++      isymend = isymbuf + symtab_hdr->sh_info;
++      for (isym = isymbuf; isym < isymend; isym++)
++        {
++          if (isym->st_shndx == shndx)
++            {
++              isym->st_value -= calc_fixup (isym->st_value, 0, sec);
++              if (isym->st_size)
++                isym->st_size -= calc_fixup (isym->st_value, isym->st_size, sec);
++            }
++        }
++
++      /* Now adjust the global symbols defined in this section.  */
++      isym = isymbuf + symtab_hdr->sh_info;
++      symcount =  (symtab_hdr->sh_size / sizeof (Elf64_External_Sym)) - symtab_hdr->sh_info;
++      for (sym_index = 0; sym_index < symcount; sym_index++)
++        {
++          sym_hash = elf_sym_hashes (abfd)[sym_index];
++          if ((sym_hash->root.type == bfd_link_hash_defined
++                  || sym_hash->root.type == bfd_link_hash_defweak)
++              && sym_hash->root.u.def.section == sec)
++            {
++              sym_hash->root.u.def.value -= calc_fixup (sym_hash->root.u.def.value,
++                                                        0, sec);
++              if (sym_hash->size)
++                sym_hash->size -= calc_fixup (sym_hash->root.u.def.value,
++                                              sym_hash->size, sec);
++            }
++        }
++
++      /* Physically move the code and change the cooked size.  */
++      dest = sdata->relax[0].addr;
++      for (i = 0; i < sdata->relax_count; i++)
++       {
++         size_t len;
++         src = sdata->relax[i].addr + sdata->relax[i].size;
++         len = (sdata->relax[i+1].addr - sdata->relax[i].addr
++                - sdata->relax[i].size);
++
++         memmove (contents + dest, contents + src, len);
++         sec->size -= sdata->relax[i].size;
++         dest += len;
++       }
++
++      elf_section_data (sec)->relocs = internal_relocs;
++
++      elf_section_data (sec)->this_hdr.contents = contents;
++
++      symtab_hdr->contents = (bfd_byte *) isymbuf;
++    }
++
++  if (internal_relocs != NULL
++      && elf_section_data (sec)->relocs != internal_relocs)
++    free (internal_relocs);
++
++  if (contents != NULL
++      && elf_section_data (sec)->this_hdr.contents != contents)
++    {
++      if (! link_info->keep_memory)
++       free (contents);
++      else
++       {
++         /* Cache the section contents for elf_link_input_bfd.  */
++         elf_section_data (sec)->this_hdr.contents = contents;
++       }
++    }
++
++  if (sdata->relax_count == 0)
++    {
++      *again = false;
++      free (sdata->relax);
++      sdata->relax = NULL;
++    }
++  else
++    *again = true;
++  return true;
++
++ error_return:
++  if (isymbuf != NULL
++      && symtab_hdr->contents != (unsigned char *) isymbuf)
++    free (isymbuf);
++  if (internal_relocs != NULL
++      && elf_section_data (sec)->relocs != internal_relocs)
++    free (internal_relocs);
++  if (contents != NULL
++      && elf_section_data (sec)->this_hdr.contents != contents)
++    free (contents);
++  free (sdata->relax);
++  sdata->relax = NULL;
++  sdata->relax_count = 0;
++  return false;
++}
++
++/* Return the section that should be marked against GC for a given
++   relocation.  */
++
++static asection *
++microblaze_elf_gc_mark_hook (asection *sec,
++                            struct bfd_link_info * info,
++                            Elf_Internal_Rela * rel,
++                            struct elf_link_hash_entry * h,
++                            Elf_Internal_Sym * sym)
++{
++  if (h != NULL)
++    switch (ELF64_R_TYPE (rel->r_info))
++      {
++      case R_MICROBLAZE_GNU_VTINHERIT:
++      case R_MICROBLAZE_GNU_VTENTRY:
++       return NULL;
++      }
++
++  return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
++}
++
++/* Update the got entry reference counts for the section being removed.  */
++
++static bool
++microblaze_elf_gc_sweep_hook (bfd * abfd ATTRIBUTE_UNUSED,
++                             struct bfd_link_info * info ATTRIBUTE_UNUSED,
++                             asection * sec ATTRIBUTE_UNUSED,
++                             const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED)
++{
++  return true;
++}
++
++/* PIC support.  */
++
++#define PLT_ENTRY_SIZE 16
++
++#define PLT_ENTRY_WORD_0  0xb0000000          /* "imm 0".  */
++#define PLT_ENTRY_WORD_1  0xe9940000          /* "lwi r12,r20,0" - relocated to lwi r12,r20,func@GOT.  */
++#define PLT_ENTRY_WORD_1_NOPIC  0xe9800000    /* "lwi r12,r0,0" - non-PIC object.  */
++#define PLT_ENTRY_WORD_2  0x98186000          /* "brad r12".  */
++#define PLT_ENTRY_WORD_3  0x80000000          /* "nop".  */
++
++/* Create .got, .gotplt, and .rela.got sections in DYNOBJ, and set up
++   shortcuts to them in our hash table.  */
++
++static bool
++update_local_sym_info (bfd *abfd,
++                      Elf_Internal_Shdr *symtab_hdr,
++                      unsigned long r_symndx,
++                      unsigned int tls_type)
++{
++  bfd_signed_vma *local_got_refcounts = elf_local_got_refcounts (abfd);
++  unsigned char *local_got_tls_masks;
++
++  if (local_got_refcounts == NULL)
++    {
++      bfd_size_type size = symtab_hdr->sh_info;
++
++      size *= (sizeof (*local_got_refcounts) + sizeof (*local_got_tls_masks));
++      local_got_refcounts = bfd_zalloc (abfd, size);
++      if (local_got_refcounts == NULL)
++        return false;
++      elf_local_got_refcounts (abfd) = local_got_refcounts;
++    }
++
++  local_got_tls_masks =
++         (unsigned char *) (local_got_refcounts + symtab_hdr->sh_info);
++  local_got_tls_masks[r_symndx] |= tls_type;
++  local_got_refcounts[r_symndx] += 1;
++
++  return true;
++}
++/* Look through the relocs for a section during the first phase.  */
++
++static bool
++microblaze_elf_check_relocs (bfd * abfd,
++                            struct bfd_link_info * info,
++                            asection * sec,
++                            const Elf_Internal_Rela * relocs)
++{
++  Elf_Internal_Shdr *           symtab_hdr;
++  struct elf_link_hash_entry ** sym_hashes;
++  struct elf_link_hash_entry ** sym_hashes_end;
++  const Elf_Internal_Rela *     rel;
++  const Elf_Internal_Rela *     rel_end;
++  struct elf64_mb_link_hash_table *htab;
++  asection *sreloc = NULL;
++
++  if (bfd_link_relocatable (info))
++    return true;
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return false;
++
++  symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
++  sym_hashes = elf_sym_hashes (abfd);
++  sym_hashes_end = sym_hashes + symtab_hdr->sh_size / sizeof (Elf64_External_Sym);
++  if (!elf_bad_symtab (abfd))
++    sym_hashes_end -= symtab_hdr->sh_info;
++
++  rel_end = relocs + sec->reloc_count;
++
++  for (rel = relocs; rel < rel_end; rel++)
++    {
++      unsigned int r_type;
++      struct elf_link_hash_entry * h;
++      unsigned long r_symndx;
++      unsigned char tls_type = 0;
++
++      r_symndx = ELF64_R_SYM (rel->r_info);
++      r_type = ELF64_R_TYPE (rel->r_info);
++
++      if (r_symndx < symtab_hdr->sh_info)
++        h = NULL;
++      else
++       {
++         h = sym_hashes [r_symndx - symtab_hdr->sh_info];
++         while (h->root.type == bfd_link_hash_indirect
++                || h->root.type == bfd_link_hash_warning)
++           h = (struct elf_link_hash_entry *) h->root.u.i.link;
++         /* PR15323, ref flags aren't set for references in the same
++            object.  */
++         h->root.non_ir_ref_regular = 1;
++       }
++
++      switch (r_type)
++        {
++         /* This relocation describes the C++ object vtable hierarchy.
++            Reconstruct it for later use during GC.  */
++        case R_MICROBLAZE_GNU_VTINHERIT:
++          if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
++            return false;
++          break;
++
++         /* This relocation describes which C++ vtable entries are actually
++            used.  Record for later use during GC.  */
++        case R_MICROBLAZE_GNU_VTENTRY:
++          if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend))
++            return false;
++          break;
++
++         /* This relocation requires .plt entry.  */
++        case R_MICROBLAZE_PLT_64:
++          if (h != NULL)
++           {
++             h->needs_plt = 1;
++             h->plt.refcount += 1;
++           }
++          break;
++
++         /* This relocation requires .got entry.  */
++       case R_MICROBLAZE_TLSGD:
++         tls_type |= (TLS_TLS | TLS_GD);
++         goto dogottls;
++       case R_MICROBLAZE_TLSLD:
++         tls_type |= (TLS_TLS | TLS_LD);
++         /* Fall through.  */
++       dogottls:
++         sec->has_tls_reloc = 1;
++         /* Fall through.  */
++       case R_MICROBLAZE_GOT_64:
++         if (htab->elf.sgot == NULL)
++           {
++             if (htab->elf.dynobj == NULL)
++               htab->elf.dynobj = abfd;
++             if (!_bfd_elf_create_got_section (htab->elf.dynobj, info))
++               return false;
++           }
++         if (h != NULL)
++           {
++             h->got.refcount += 1;
++             elf64_mb_hash_entry (h)->tls_mask |= tls_type;
++           }
++          else
++           {
++             if (! update_local_sym_info(abfd, symtab_hdr, r_symndx, tls_type) )
++               return false;
++           }
++         break;
++
++       case R_MICROBLAZE_GOTOFF_64:
++       case R_MICROBLAZE_GOTOFF_32:
++         if (htab->elf.sgot == NULL)
++           {
++             if (htab->elf.dynobj == NULL)
++               htab->elf.dynobj = abfd;
++             if (!_bfd_elf_create_got_section (htab->elf.dynobj, info))
++               return false;
++           }
++          break;
++
++        case R_MICROBLAZE_64:
++        case R_MICROBLAZE_64_PCREL:
++        case R_MICROBLAZE_32:
++        case R_MICROBLAZE_IMML_64:
++          {
++            if (h != NULL && !bfd_link_pic (info))
++             {
++               /* we may need a copy reloc.  */
++               h->non_got_ref = 1;
++
++               /* we may also need a .plt entry.  */
++               h->plt.refcount += 1;
++               if (ELF64_R_TYPE (rel->r_info) != R_MICROBLAZE_64_PCREL)
++                 h->pointer_equality_needed = 1;
++             }
++
++
++           /* If we are creating a shared library, and this is a reloc
++              against a global symbol, or a non PC relative reloc
++              against a local symbol, then we need to copy the reloc
++              into the shared library.  However, if we are linking with
++              -Bsymbolic, we do not need to copy a reloc against a
++              global symbol which is defined in an object we are
++              including in the link (i.e., DEF_REGULAR is set).  At
++              this point we have not seen all the input files, so it is
++              possible that DEF_REGULAR is not set now but will be set
++              later (it is never cleared).  In case of a weak definition,
++              DEF_REGULAR may be cleared later by a strong definition in
++              a shared library.  We account for that possibility below by
++              storing information in the relocs_copied field of the hash
++              table entry.  A similar situation occurs when creating
++              shared libraries and symbol visibility changes render the
++              symbol local.
++
++              If on the other hand, we are creating an executable, we
++              may need to keep relocations for symbols satisfied by a
++              dynamic library if we manage to avoid copy relocs for the
++              symbol.  */
++
++            if ((bfd_link_pic (info)
++                 && (sec->flags & SEC_ALLOC) != 0
++                 && (r_type != R_MICROBLAZE_64_PCREL
++                     || (h != NULL
++                        && (! info->symbolic
++                            || h->root.type == bfd_link_hash_defweak
++                            || !h->def_regular))))
++                || (!bfd_link_pic (info)
++                    && (sec->flags & SEC_ALLOC) != 0
++                    && h != NULL
++                    && (h->root.type == bfd_link_hash_defweak
++                        || !h->def_regular)))
++              {
++                struct elf64_mb_dyn_relocs *p;
++                struct elf64_mb_dyn_relocs **head;
++
++                /* When creating a shared object, we must copy these
++                   relocs into the output file.  We create a reloc
++                   section in dynobj and make room for the reloc.  */
++
++               if (sreloc == NULL)
++                 {
++                   bfd *dynobj;
++
++                   if (htab->elf.dynobj == NULL)
++                     htab->elf.dynobj = abfd;
++                   dynobj = htab->elf.dynobj;
++
++                   sreloc = _bfd_elf_make_dynamic_reloc_section (sec, dynobj,
++                                                                 2, abfd, 1);
++                   if (sreloc == NULL)
++                     return false;
++                 }
++
++               /* If this is a global symbol, we count the number of
++                  relocations we need for this symbol.  */
++               if (h != NULL)
++                 head = &h->dyn_relocs;
++               else
++                 {
++                   /* Track dynamic relocs needed for local syms too.
++                      We really need local syms available to do this
++                      easily.  Oh well.  */
++
++                   asection *s;
++                   Elf_Internal_Sym *isym;
++                   void *vpp;
++
++                   isym = bfd_sym_from_r_symndx (&htab->elf.sym_cache,
++                                                 abfd, r_symndx);
++                   if (isym == NULL)
++                     return false;
++
++                   s = bfd_section_from_elf_index (abfd, isym->st_shndx);
++                   if (s == NULL)
++                     return false;
++
++                   vpp = &elf_section_data (s)->local_dynrel;
++                   head = (struct elf64_mb_dyn_relocs **) vpp;
++                 }
++
++               p = *head;
++               if (p == NULL || p->sec != sec)
++                 {
++                   size_t amt = sizeof *p;
++                   p = ((struct elf64_mb_dyn_relocs *)
++                        bfd_alloc (htab->elf.dynobj, amt));
++                   if (p == NULL)
++                     return false;
++                   p->next = *head;
++                   *head = p;
++                   p->sec = sec;
++                   p->count = 0;
++                   p->pc_count = 0;
++                 }
++
++               p->count += 1;
++               if (r_type == R_MICROBLAZE_64_PCREL)
++                 p->pc_count += 1;
++             }
++          }
++          break;
++        }
++    }
++
++  return true;
++}
++
++static bool
++microblaze_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
++{
++  struct elf64_mb_link_hash_table *htab;
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return false;
++
++  if (!htab->sgot && !_bfd_elf_create_got_section (dynobj, info))
++    return false;
++
++  if (!_bfd_elf_create_dynamic_sections (dynobj, info))
++    return false;
++
++  htab->splt = bfd_get_linker_section (dynobj, ".plt");
++  htab->srelplt = bfd_get_linker_section (dynobj, ".rela.plt");
++  htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
++  if (!bfd_link_pic (info))
++    htab->srelbss = bfd_get_linker_section (dynobj, ".rela.bss");
++
++  if (!htab->splt || !htab->srelplt || !htab->sdynbss
++      || (!bfd_link_pic (info) && !htab->srelbss))
++    abort ();
++
++  return true;
++}
++
++/* Copy the extra info we tack onto an elf_link_hash_entry.  */
++
++static void
++microblaze_elf_copy_indirect_symbol (struct bfd_link_info *info,
++                                    struct elf_link_hash_entry *dir,
++                                    struct elf_link_hash_entry *ind)
++{
++  struct elf64_mb_link_hash_entry *edir, *eind;
++
++  edir = (struct elf64_mb_link_hash_entry *) dir;
++  eind = (struct elf64_mb_link_hash_entry *) ind;
++
++  if (eind->dyn_relocs != NULL)
++    {
++      if (edir->dyn_relocs != NULL)
++       {
++         struct elf64_mb_dyn_relocs **pp;
++         struct elf64_mb_dyn_relocs *p;
++
++         if (ind->root.type == bfd_link_hash_indirect)
++           abort ();
++
++         /* Add reloc counts against the weak sym to the strong sym
++            list.  Merge any entries against the same section.  */
++         for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
++           {
++             struct elf64_mb_dyn_relocs *q;
++
++             for (q = edir->dyn_relocs; q != NULL; q = q->next)
++               if (q->sec == p->sec)
++                 {
++                   q->pc_count += p->pc_count;
++                   q->count += p->count;
++                   *pp = p->next;
++                   break;
++                 }
++             if (q == NULL)
++               pp = &p->next;
++           }
++         *pp = edir->dyn_relocs;
++       }
++
++      edir->dyn_relocs = eind->dyn_relocs;
++      eind->dyn_relocs = NULL;
++    }
++
++  edir->tls_mask |= eind->tls_mask;
++
++  _bfd_elf_link_hash_copy_indirect (info, dir, ind);
++}
++
++static bool
++microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info,
++                                     struct elf_link_hash_entry *h)
++{
++  struct elf64_mb_link_hash_table *htab;
++  struct elf64_mb_link_hash_entry * eh;
++  struct elf64_mb_dyn_relocs *p;
++  asection *sdynbss;
++  asection *s, *srel;
++  unsigned int power_of_two;
++  bfd *dynobj;
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return false;
++
++  /* If this is a function, put it in the procedure linkage table.  We
++     will fill in the contents of the procedure linkage table later,
++     when we know the address of the .got section.  */
++  if (h->type == STT_FUNC
++      || h->needs_plt)
++    {
++      if (h->plt.refcount <= 0
++         || SYMBOL_CALLS_LOCAL (info, h)
++         || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
++             && h->root.type == bfd_link_hash_undefweak))
++       {
++         /* This case can occur if we saw a PLT reloc in an input
++            file, but the symbol was never referred to by a dynamic
++            object, or if all references were garbage collected.  In
++            such a case, we don't actually need to build a procedure
++            linkage table, and we can just do a PC32 reloc instead.  */
++         h->plt.offset = (bfd_vma) -1;
++         h->needs_plt = 0;
++       }
++
++      return true;
++    }
++  else
++    /* It's possible that we incorrectly decided a .plt reloc was
++       needed for an R_MICROBLAZE_64_PCREL reloc to a non-function sym in
++       check_relocs.  We can't decide accurately between function and
++       non-function syms in check-relocs;  Objects loaded later in
++       the link may change h->type.  So fix it now.  */
++    h->plt.offset = (bfd_vma) -1;
++
++  /* If this is a weak symbol, and there is a real definition, the
++     processor independent code will have arranged for us to see the
++     real definition first, and we can just use the same value.  */
++  if (h->is_weakalias)
++    {
++      struct elf_link_hash_entry *def = weakdef (h);
++      BFD_ASSERT (def->root.type == bfd_link_hash_defined);
++      h->root.u.def.section = def->root.u.def.section;
++      h->root.u.def.value = def->root.u.def.value;
++      return true;
++    }
++
++  /* This is a reference to a symbol defined by a dynamic object which
++     is not a function.  */
++
++  /* If we are creating a shared library, we must presume that the
++     only references to the symbol are via the global offset table.
++     For such cases we need not do anything here; the relocations will
++     be handled correctly by relocate_section.  */
++  if (bfd_link_pic (info))
++    return true;
++
++  /* If there are no references to this symbol that do not use the
++     GOT, we don't need to generate a copy reloc.  */
++  if (!h->non_got_ref)
++    return true;
++
++  /* If -z nocopyreloc was given, we won't generate them either.  */
++  if (info->nocopyreloc)
++    {
++      h->non_got_ref = 0;
++      return true;
++    }
++
++  eh = (struct elf64_mb_link_hash_entry *) h;
++  for (p = eh->dyn_relocs; p != NULL; p = p->next)
++    {
++      s = p->sec->output_section;
++      if (s != NULL && (s->flags & SEC_READONLY) != 0)
++       break;
++    }
++
++  /* If we didn't find any dynamic relocs in read-only sections, then
++     we'll be keeping the dynamic relocs and avoiding the copy reloc.  */
++  if (p == NULL)
++    {
++      h->non_got_ref = 0;
++      return true;
++    }
++
++  /* We must allocate the symbol in our .dynbss section, which will
++     become part of the .bss section of the executable.  There will be
++     an entry for this symbol in the .dynsym section.  The dynamic
++     object will contain position independent code, so all references
++     from the dynamic object to this symbol will go through the global
++     offset table.  The dynamic linker will use the .dynsym entry to
++     determine the address it must put in the global offset table, so
++     both the dynamic object and the regular object will refer to the
++     same memory location for the variable.  */
++
++  /* We must generate a R_MICROBLAZE_COPY reloc to tell the dynamic linker
++     to copy the initial value out of the dynamic object and into the
++     runtime process image.  */
++  dynobj = elf_hash_table (info)->dynobj;
++  BFD_ASSERT (dynobj != NULL);
++  if ((h->root.u.def.section->flags & SEC_ALLOC) != 0)
++    {
++      htab->srelbss->size += sizeof (Elf64_External_Rela);
++      h->needs_copy = 1;
++    }
++
++  /* We need to figure out the alignment required for this symbol.  I
++     have no idea how ELF linkers handle this.  */
++  power_of_two = bfd_log2 (h->size);
++  if (power_of_two > 3)
++    power_of_two = 3;
++
++  sdynbss = htab->sdynbss;
++  /* Apply the required alignment.  */
++  sdynbss->size = BFD_ALIGN (sdynbss->size, (bfd_size_type) (1 << power_of_two));
++  if (power_of_two > sdynbss->alignment_power)
++    {
++      if (! bfd_set_section_alignment (sdynbss, power_of_two))
++       return false;
++    }
++
++  /* Define the symbol as being at this point in the section.  */
++  h->root.u.def.section = s;
++  h->root.u.def.value = s->size;
++
++  /* Increment the section size to make room for the symbol.  */
++  s->size += h->size;
++  return true;
++}
++
++/* Allocate space in .plt, .got and associated reloc sections for
++   dynamic relocs.  */
++
++static bool
++allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat)
++{
++  struct bfd_link_info *info;
++  struct elf64_mb_link_hash_table *htab;
++  struct elf64_mb_link_hash_entry *eh;
++  struct elf64_mb_dyn_relocs *p;
++
++  if (h->root.type == bfd_link_hash_indirect)
++    return true;
++
++  info = (struct bfd_link_info *) dat;
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return false;
++
++  if (htab->elf.dynamic_sections_created
++      && h->plt.refcount > 0)
++    {
++      /* Make sure this symbol is output as a dynamic symbol.
++        Undefined weak syms won't yet be marked as dynamic.  */
++      if (h->dynindx == -1
++          && !h->forced_local)
++        {
++          if (! bfd_elf_link_record_dynamic_symbol (info, h))
++            return false;
++        }
++
++      if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, bfd_link_pic (info), h))
++       {
++         asection *s = htab->elf.splt;
++
++          /* The first entry in .plt is reserved.  */
++          if (s->size == 0)
++            s->size = PLT_ENTRY_SIZE;
++
++          h->plt.offset = s->size;
++
++          /* If this symbol is not defined in a regular file, and we are
++             not generating a shared library, then set the symbol to this
++             location in the .plt.  This is required to make function
++             pointers compare as equal between the normal executable and
++             the shared library.  */
++          if (! bfd_link_pic (info)
++              && !h->def_regular)
++            {
++              h->root.u.def.section = s;
++              h->root.u.def.value = h->plt.offset;
++            }
++
++          /* Make room for this entry.  */
++          s->size += PLT_ENTRY_SIZE;
++
++         /* We also need to make an entry in the .got.plt section, which
++            will be placed in the .got section by the linker script.  */
++         htab->elf.sgotplt->size += 4;
++
++         /* We also need to make an entry in the .rel.plt section.  */
++         htab->elf.srelplt->size += sizeof (Elf64_External_Rela);
++       }
++      else
++        {
++          h->plt.offset = (bfd_vma) -1;
++          h->needs_plt = 0;
++        }
++    }
++  else
++    {
++      h->plt.offset = (bfd_vma) -1;
++      h->needs_plt = 0;
++    }
++
++  eh = (struct elf64_mb_link_hash_entry *) h;
++  if (h->got.refcount > 0)
++    {
++      unsigned int need;
++      asection *s;
++
++      /* Make sure this symbol is output as a dynamic symbol.
++         Undefined weak syms won't yet be marked as dynamic.  */
++      if (h->dynindx == -1
++          && !h->forced_local)
++        {
++          if (! bfd_elf_link_record_dynamic_symbol (info, h))
++            return false;
++        }
++
++      need = 0;
++      if ((eh->tls_mask & TLS_TLS) != 0)
++        {
++          /* Handle TLS Symbol */
++          if ((eh->tls_mask & TLS_LD) != 0)
++            {
++              if (!eh->elf.def_dynamic)
++                /* We'll just use htab->tlsld_got.offset.  This should
++                   always be the case.  It's a little odd if we have
++                   a local dynamic reloc against a non-local symbol.  */
++                htab->tlsld_got.refcount += 1;
++              else
++                need += 8;
++            }
++          if ((eh->tls_mask & TLS_GD) != 0)
++            need += 8;
++        }
++      else
++        {
++          /* Regular (non-TLS) symbol */
++          need += 4;
++        }
++      if (need == 0)
++        {
++          h->got.offset = (bfd_vma) -1;
++        }
++      else
++       {
++         s = htab->elf.sgot;
++         h->got.offset = s->size;
++         s->size += need;
++         htab->elf.srelgot->size += need * (sizeof (Elf64_External_Rela) / 4);
++       }
++    }
++  else
++    h->got.offset = (bfd_vma) -1;
++
++  if (eh->dyn_relocs == NULL)
++    return true;
++
++  /* In the shared -Bsymbolic case, discard space allocated for
++     dynamic pc-relative relocs against symbols which turn out to be
++     defined in regular objects.  For the normal shared case, discard
++     space for pc-relative relocs that have become local due to symbol
++     visibility changes.  */
++
++  if (bfd_link_pic (info))
++    {
++      if (h->def_regular
++         && (h->forced_local
++             || info->symbolic))
++       {
++         struct elf64_mb_dyn_relocs **pp;
++
++         for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
++           {
++             p->count -= p->pc_count;
++             p->pc_count = 0;
++             if (p->count == 0)
++               *pp = p->next;
++             else
++               pp = &p->next;
++           }
++       }
++      else if (UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
++       h->dyn_relocs = NULL;
++    }
++  else
++    {
++      /* For the non-shared case, discard space for relocs against
++        symbols which turn out to need copy relocs or are not
++        dynamic.  */
++
++      if (!h->non_got_ref
++         && ((h->def_dynamic
++              && !h->def_regular)
++             || (htab->elf.dynamic_sections_created
++                 && (h->root.type == bfd_link_hash_undefweak
++                     || h->root.type == bfd_link_hash_undefined))))
++       {
++         /* Make sure this symbol is output as a dynamic symbol.
++            Undefined weak syms won't yet be marked as dynamic.  */
++         if (h->dynindx == -1
++             && !h->forced_local)
++           {
++             if (! bfd_elf_link_record_dynamic_symbol (info, h))
++               return false;
++           }
++
++         /* If that succeeded, we know we'll be keeping all the
++            relocs.  */
++         if (h->dynindx != -1)
++           goto keep;
++       }
++
++      h->dyn_relocs = NULL;
++
++    keep: ;
++    }
++
++  /* Finally, allocate space.  */
++  for (p = h->dyn_relocs; p != NULL; p = p->next)
++    {
++      asection *sreloc = elf_section_data (p->sec)->sreloc;
++      sreloc->size += p->count * sizeof (Elf64_External_Rela);
++    }
++
++  return true;
++}
++
++/* Set the sizes of the dynamic sections.  */
++
++static bool
++microblaze_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
++                                     struct bfd_link_info *info)
++{
++  struct elf64_mb_link_hash_table *htab;
++  bfd *dynobj;
++  asection *s;
++  bfd *ibfd;
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return false;
++
++  dynobj = htab->elf.dynobj;
++  BFD_ASSERT (dynobj != NULL);
++
++  /* Set up .got offsets for local syms, and space for local dynamic
++     relocs.  */
++  for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
++    {
++      bfd_signed_vma *local_got;
++      bfd_signed_vma *end_local_got;
++      bfd_size_type locsymcount;
++      Elf_Internal_Shdr *symtab_hdr;
++      unsigned char *lgot_masks;
++      asection *srel;
++
++      if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour)
++        continue;
++
++      for (s = ibfd->sections; s != NULL; s = s->next)
++       {
++         struct elf_dyn_relocs *p;
++
++         for (p = ((struct elf64_mb_dyn_relocs *)
++                   elf_section_data (s)->local_dynrel);
++              p != NULL;
++              p = p->next)
++           {
++             if (!bfd_is_abs_section (p->sec)
++                 && bfd_is_abs_section (p->sec->output_section))
++               {
++                 /* Input section has been discarded, either because
++                    it is a copy of a linkonce section or due to
++                    linker script /DISCARD/, so we'll be discarding
++                    the relocs too.  */
++               }
++             else if (p->count != 0)
++               {
++                 srel = elf_section_data (p->sec)->sreloc;
++                 srel->size += p->count * sizeof (Elf64_External_Rela);
++                 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
++                   info->flags |= DF_TEXTREL;
++               }
++           }
++       }
++
++      local_got = elf_local_got_refcounts (ibfd);
++      if (!local_got)
++        continue;
++
++      symtab_hdr = &elf_tdata (ibfd)->symtab_hdr;
++      locsymcount = symtab_hdr->sh_info;
++      end_local_got = local_got + locsymcount;
++      lgot_masks = (unsigned char *) end_local_got;
++      s = htab->elf.sgot;
++      srel = htab->elf.srelgot;
++
++      for (; local_got < end_local_got; ++local_got, ++lgot_masks)
++       {
++         if (*local_got > 0)
++           {
++             unsigned int need = 0;
++             if ((*lgot_masks & TLS_TLS) != 0)
++               {
++                 if ((*lgot_masks & TLS_GD) != 0)
++                   need += 8;
++                 if ((*lgot_masks & TLS_LD) != 0)
++                   htab->tlsld_got.refcount += 1;
++               }
++             else
++               need += 4;
++
++             if (need == 0)
++               {
++                 *local_got = (bfd_vma) -1;
++               }
++             else
++               {
++                 *local_got = s->size;
++                 s->size += need;
++                 if (bfd_link_pic (info))
++                   srel->size += need * (sizeof (Elf64_External_Rela) / 4);
++               }
++            }
++          else
++            *local_got = (bfd_vma) -1;
++        }
++    }
++
++  /* Allocate global sym .plt and .got entries, and space for global
++     sym dynamic relocs.  */
++  elf_link_hash_traverse (elf_hash_table (info), allocate_dynrelocs, info);
++
++  if (htab->tlsld_got.refcount > 0)
++    {
++      htab->tlsld_got.offset = htab->elf.sgot->size;
++      htab->elf.sgot->size += 8;
++      if (bfd_link_pic (info))
++       htab->elf.srelgot->size += sizeof (Elf64_External_Rela);
++    }
++  else
++    htab->tlsld_got.offset = (bfd_vma) -1;
++
++  if (elf_hash_table (info)->dynamic_sections_created)
++    {
++      /* Make space for the trailing nop in .plt.  */
++      if (htab->elf.splt->size > 0)
++       htab->elf.splt->size += 4;
++    }
++
++  /* The check_relocs and adjust_dynamic_symbol entry points have
++     determined the sizes of the various dynamic sections.  Allocate
++     memory for them.  */
++  for (s = dynobj->sections; s != NULL; s = s->next)
++    {
++      const char *name;
++      bool strip = false;
++
++      if ((s->flags & SEC_LINKER_CREATED) == 0)
++        continue;
++
++      /* It's OK to base decisions on the section name, because none
++        of the dynobj section names depend upon the input files.  */
++      name = bfd_section_name (s);
++
++      if (startswith (name, ".rela"))
++       {
++         if (s->size == 0)
++           {
++             /* If we don't need this section, strip it from the
++                output file.  This is to handle .rela.bss and
++                .rela.plt.  We must create it in
++                create_dynamic_sections, because it must be created
++                before the linker maps input sections to output
++                sections.  The linker does that before
++                adjust_dynamic_symbol is called, and it is that
++                function which decides whether anything needs to go
++                into these sections.  */
++             strip = true;
++           }
++         else
++           {
++             /* We use the reloc_count field as a counter if we need
++                to copy relocs into the output file.  */
++             s->reloc_count = 0;
++           }
++       }
++      else if (s != htab->elf.splt
++              && s != htab->elf.sgot
++              && s != htab->elf.sgotplt
++              && s != htab->elf.sdynbss
++              && s != htab->elf.sdynrelro)
++       {
++         /* It's not one of our sections, so don't allocate space.  */
++         continue;
++       }
++
++      if (strip)
++       {
++         s->flags |= SEC_EXCLUDE;
++         continue;
++       }
++
++      /* Allocate memory for the section contents.  */
++      /* FIXME: This should be a call to bfd_alloc not bfd_zalloc.
++        Unused entries should be reclaimed before the section's contents
++        are written out, but at the moment this does not happen.  Thus in
++        order to prevent writing out garbage, we initialise the section's
++        contents to zero.  */
++      s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size);
++      if (s->contents == NULL && s->size != 0)
++       return false;
++    }
++
++  /* ??? Force DF_BIND_NOW?  */
++  info->flags |= DF_BIND_NOW;
++  return _bfd_elf_add_dynamic_tags (output_bfd, info, true);
++}
++
++/* Finish up dynamic symbol handling.  We set the contents of various
++   dynamic sections here.  */
++
++static bool
++microblaze_elf_finish_dynamic_symbol (bfd *output_bfd,
++                                     struct bfd_link_info *info,
++                                     struct elf_link_hash_entry *h,
++                                     Elf_Internal_Sym *sym)
++{
++  struct elf64_mb_link_hash_table *htab;
++  struct elf64_mb_link_hash_entry *eh = elf64_mb_hash_entry(h);
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return false;
++
++  if (h->plt.offset != (bfd_vma) -1)
++    {
++      asection *splt;
++      asection *srela;
++      asection *sgotplt;
++      Elf_Internal_Rela rela;
++      bfd_byte *loc;
++      bfd_vma plt_index;
++      bfd_vma got_offset;
++      bfd_vma got_addr;
++
++      /* This symbol has an entry in the procedure linkage table.  Set
++         it up.  */
++      BFD_ASSERT (h->dynindx != -1);
++
++      splt = htab->elf.splt;
++      srela = htab->elf.srelplt;
++      sgotplt = htab->elf.sgotplt;
++      BFD_ASSERT (splt != NULL && srela != NULL && sgotplt != NULL);
++
++      plt_index = h->plt.offset / PLT_ENTRY_SIZE - 1; /* first entry reserved.  */
++      got_offset = (plt_index + 3) * 4; /* 3 reserved ???  */
++      got_addr = got_offset;
++
++      /* For non-PIC objects we need absolute address of the GOT entry.  */
++      if (!bfd_link_pic (info))
++       got_addr += sgotplt->output_section->vma + sgotplt->output_offset;
++
++      /* Fill in the entry in the procedure linkage table.  */
++      bfd_put_32 (output_bfd, PLT_ENTRY_WORD_0 + ((got_addr >> 16) & 0xffff),
++                  splt->contents + h->plt.offset);
++      if (bfd_link_pic (info))
++        bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1 + (got_addr & 0xffff),
++                    splt->contents + h->plt.offset + 4);
++      else
++        bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1_NOPIC + (got_addr & 0xffff),
++                    splt->contents + h->plt.offset + 4);
++      bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_2,
++                  splt->contents + h->plt.offset + 8);
++      bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_3,
++                  splt->contents + h->plt.offset + 12);
++
++      /* Any additions to the .got section??? */
++      /*      bfd_put_32 (output_bfd,
++             splt->output_section->vma + splt->output_offset + h->plt.offset + 4,
++             sgotplt->contents + got_offset); */
++
++      /* Fill in the entry in the .rela.plt section.  */
++      rela.r_offset = (sgotplt->output_section->vma
++                       + sgotplt->output_offset
++                       + got_offset);
++      rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_JUMP_SLOT);
++      rela.r_addend = 0;
++      loc = srela->contents;
++      loc += plt_index * sizeof (Elf64_External_Rela);
++      bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
++
++      if (!h->def_regular)
++        {
++          /* Mark the symbol as undefined, rather than as defined in
++             the .plt section.  Zero the value.  */
++          sym->st_shndx = SHN_UNDEF;
++          sym->st_value = 0;
++        }
++    }
++
++  /* h->got.refcount to be checked ? */
++  if (h->got.offset != (bfd_vma) -1 &&
++      ! ((h->got.offset & 1) ||
++          IS_TLS_LD(eh->tls_mask) || IS_TLS_GD(eh->tls_mask)))
++    {
++      asection *sgot;
++      asection *srela;
++      bfd_vma offset;
++
++      /* This symbol has an entry in the global offset table.  Set it
++         up.  */
++
++      sgot = htab->elf.sgot;
++      srela = htab->elf.srelgot;
++      BFD_ASSERT (sgot != NULL && srela != NULL);
++
++      offset = (sgot->output_section->vma + sgot->output_offset
++               + (h->got.offset &~ (bfd_vma) 1));
++
++      /* If this is a -Bsymbolic link, and the symbol is defined
++         locally, we just want to emit a RELATIVE reloc.  Likewise if
++         the symbol was forced to be local because of a version file.
++         The entry in the global offset table will already have been
++         initialized in the relocate_section function.  */
++      if (bfd_link_pic (info)
++          && ((info->symbolic && h->def_regular)
++             || h->dynindx == -1))
++       {
++         asection *sec = h->root.u.def.section;
++         bfd_vma value;
++
++         value = h->root.u.def.value;
++         if (sec->output_section != NULL)
++           /* PR 21180: If the output section is NULL, then the symbol is no
++              longer needed, and in theory the GOT entry is redundant.  But
++              it is too late to change our minds now...  */
++           value += sec->output_section->vma + sec->output_offset;
++
++         microblaze_elf_output_dynamic_relocation (output_bfd,
++                                                   srela, srela->reloc_count++,
++                                                   /* symindex= */ 0,
++                                                   R_MICROBLAZE_REL, offset,
++                                                   value);
++       }
++      else
++        {
++          microblaze_elf_output_dynamic_relocation (output_bfd,
++                                                    srela, srela->reloc_count++,
++                                                    h->dynindx,
++                                                    R_MICROBLAZE_GLOB_DAT,
++                                                    offset, 0);
++        }
++
++      bfd_put_32 (output_bfd, (bfd_vma) 0,
++                  sgot->contents + (h->got.offset &~ (bfd_vma) 1));
++    }
++
++  if (h->needs_copy)
++    {
++      asection *s;
++      Elf_Internal_Rela rela;
++      bfd_byte *loc;
++
++      /* This symbols needs a copy reloc.  Set it up.  */
++
++      BFD_ASSERT (h->dynindx != -1);
++
++      rela.r_offset = (h->root.u.def.value
++                       + h->root.u.def.section->output_section->vma
++                       + h->root.u.def.section->output_offset);
++      rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_COPY);
++      rela.r_addend = 0;
++      if (h->root.u.def.section == htab->elf.sdynrelro)
++       s = htab->elf.sreldynrelro;
++      else
++       s = htab->elf.srelbss;
++      loc = s->contents + s->reloc_count++ * sizeof (Elf32_External_Rela);
++      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
++    }
++
++  /* Mark some specially defined symbols as absolute.  */
++  if (h == htab->elf.hdynamic
++      || h == htab->elf.hgot
++      || h == htab->elf.hplt)
++    sym->st_shndx = SHN_ABS;
++
++  return true;
++}
++
++
++/* Finish up the dynamic sections.  */
++
++static bool
++microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
++                                       struct bfd_link_info *info)
++{
++  bfd *dynobj;
++  asection *sdyn, *sgot;
++  struct elf64_mb_link_hash_table *htab;
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return false;
++
++  dynobj = htab->elf.dynobj;
++
++  sdyn = bfd_get_linker_section (dynobj, ".dynamic");
++
++  if (htab->elf.dynamic_sections_created)
++    {
++      asection *splt;
++      Elf64_External_Dyn *dyncon, *dynconend;
++
++      dyncon = (Elf64_External_Dyn *) sdyn->contents;
++      dynconend = (Elf64_External_Dyn *) (sdyn->contents + sdyn->size);
++      for (; dyncon < dynconend; dyncon++)
++       {
++         Elf_Internal_Dyn dyn;
++         asection *s;
++         bool size;
++
++          bfd_elf64_swap_dyn_in (dynobj, dyncon, &dyn);
++
++         switch (dyn.d_tag)
++           {
++           case DT_PLTGOT:
++             s = htab->elf.sgotplt;
++             size = false;
++             break;
++
++           case DT_PLTRELSZ:
++             s = htab->elf.srelplt;
++             size = true;
++             break;
++
++           case DT_JMPREL:
++             s = htab->elf.srelplt;
++             size = false;
++             break;
++
++           default:
++             continue;
++           }
++
++         if (s == NULL)
++           dyn.d_un.d_val = 0;
++         else
++           {
++             if (!size)
++               dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
++             else
++               dyn.d_un.d_val = s->size;
++           }
++         bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon);
++       }
++
++      splt = htab->elf.splt;
++      BFD_ASSERT (splt != NULL && sdyn != NULL);
++
++      /* Clear the first entry in the procedure linkage table,
++        and put a nop in the last four bytes.  */
++      if (splt->size > 0)
++       {
++         memset (splt->contents, 0, PLT_ENTRY_SIZE);
++         bfd_put_32 (output_bfd, (bfd_vma) 0x80000000 /* nop.  */,
++                     splt->contents + splt->size - 4);
++
++         if (splt->output_section != bfd_abs_section_ptr)
++           elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
++       }
++    }
++
++  /* Set the first entry in the global offset table to the address of
++     the dynamic section.  */
++  sgot = htab->elf.sgotplt;
++  if (sgot && sgot->size > 0)
++    {
++      if (sdyn == NULL)
++        bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
++      else
++        bfd_put_32 (output_bfd,
++                    sdyn->output_section->vma + sdyn->output_offset,
++                    sgot->contents);
++      elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
++    }
++
++  if (htab->elf.sgot && htab->elf.sgot->size > 0)
++    elf_section_data (htab->elf.sgot->output_section)->this_hdr.sh_entsize = 4;
++
++  return true;
++}
++
++/* Hook called by the linker routine which adds symbols from an object
++   file.  We use it to put .comm items in .sbss, and not .bss.  */
++
++static bool
++microblaze_elf_add_symbol_hook (bfd *abfd,
++                               struct bfd_link_info *info,
++                               Elf_Internal_Sym *sym,
++                               const char **namep ATTRIBUTE_UNUSED,
++                               flagword *flagsp ATTRIBUTE_UNUSED,
++                               asection **secp,
++                               bfd_vma *valp)
++{
++  if (sym->st_shndx == SHN_COMMON
++      && !bfd_link_relocatable (info)
++      && sym->st_size <= elf_gp_size (abfd))
++    {
++      /* Common symbols less than or equal to -G nn bytes are automatically
++        put into .sbss.  */
++      *secp = bfd_make_section_old_way (abfd, ".sbss");
++      if (*secp == NULL
++         || !bfd_set_section_flags (*secp, SEC_IS_COMMON | SEC_SMALL_DATA))
++       return false;
++
++      *valp = sym->st_size;
++    }
++
++  return true;
++}
++
++#define TARGET_LITTLE_SYM      microblaze_elf64_le_vec
++#define TARGET_LITTLE_NAME     "elf64-microblazeel"
++
++#define TARGET_BIG_SYM          microblaze_elf64_vec
++#define TARGET_BIG_NAME                "elf64-microblaze"
++
++#define ELF_ARCH               bfd_arch_microblaze
++#define ELF_TARGET_ID          MICROBLAZE_ELF_DATA
++#define ELF_MACHINE_CODE       EM_MICROBLAZE
++#define ELF_MACHINE_ALT1       EM_MICROBLAZE_OLD
++#define ELF_MAXPAGESIZE                0x1000
++#define elf_info_to_howto      microblaze_elf_info_to_howto
++#define elf_info_to_howto_rel  NULL
++
++#define bfd_elf64_bfd_reloc_type_lookup                microblaze_elf_reloc_type_lookup
++#define bfd_elf64_bfd_is_local_label_name       microblaze_elf_is_local_label_name
++#define bfd_elf64_new_section_hook             microblaze_elf_new_section_hook
++#define elf_backend_relocate_section           microblaze_elf_relocate_section
++#define bfd_elf64_bfd_relax_section             microblaze_elf_relax_section
++#define bfd_elf64_bfd_merge_private_bfd_data    microblaze_elf_merge_private_bfd_data
++#define bfd_elf64_bfd_reloc_name_lookup                microblaze_elf_reloc_name_lookup
++
++#define elf_backend_gc_mark_hook               microblaze_elf_gc_mark_hook
++#define elf_backend_gc_sweep_hook              microblaze_elf_gc_sweep_hook
++#define elf_backend_check_relocs                microblaze_elf_check_relocs
++#define elf_backend_copy_indirect_symbol        microblaze_elf_copy_indirect_symbol
++#define bfd_elf64_bfd_link_hash_table_create    microblaze_elf_link_hash_table_create
++#define elf_backend_can_gc_sections            1
++#define elf_backend_can_refcount               1
++#define elf_backend_want_got_plt               1
++#define elf_backend_plt_readonly               1
++#define elf_backend_got_header_size            12
++#define elf_backend_want_dynrelro              1
++#define elf_backend_rela_normal                        1
++#define elf_backend_dtrel_excludes_plt         1
++
++#define elf_backend_adjust_dynamic_symbol       microblaze_elf_adjust_dynamic_symbol
++#define elf_backend_create_dynamic_sections     microblaze_elf_create_dynamic_sections
++#define elf_backend_finish_dynamic_sections     microblaze_elf_finish_dynamic_sections
++#define elf_backend_finish_dynamic_symbol       microblaze_elf_finish_dynamic_symbol
++#define elf_backend_size_dynamic_sections       microblaze_elf_size_dynamic_sections
++#define elf_backend_add_symbol_hook            microblaze_elf_add_symbol_hook
++
++#include "elf64-target.h"
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 7cbbc8986a1..597507e53cd 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -65,8 +65,95 @@
+ #define IS_SAVE_HIDDEN_PTR(op, rd, ra, rb) \
+   ((op == add || op == addik) && ra == MICROBLAZE_FIRST_ARGREG && rb == 0)
+ 
++static const char *microblaze_abi_string;
++
++static const char *const microblaze_abi_strings[] = {
++  "auto",
++  "m64",
++};
++
++enum microblaze_abi
++microblaze_abi (struct gdbarch *gdbarch)
++{
++  microblaze_gdbarch_tdep *tdep = (microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch);
++  return tdep->microblaze_abi;
++}
+ /* The registers of the Xilinx microblaze processor.  */
+ 
++ static struct cmd_list_element *setmicroblazecmdlist = NULL;
++ static struct cmd_list_element *showmicroblazecmdlist = NULL;
++
++static void
++microblaze_abi_update (const char *ignore_args,
++                 int from_tty, struct cmd_list_element *c)
++{
++  struct gdbarch_info info;
++
++  /* Force the architecture to update, and (if it's a microblaze architecture)
++ *      microblaze_gdbarch_init will take care of the rest.  */
++//  gdbarch_info_init (&info);
++  gdbarch_update_p (info);
++}
++
++
++static enum microblaze_abi
++global_microblaze_abi (void)
++{
++  int i;
++
++  for (i = 0; microblaze_abi_strings[i] != NULL; i++)
++    if (microblaze_abi_strings[i] == microblaze_abi_string)
++      return (enum microblaze_abi) i;
++
++//  internal_error (__FILE__, __LINE__, _("unknown ABI string"));
++}
++
++static void
++show_microblaze_abi (struct ui_file *file,
++               int from_tty,
++               struct cmd_list_element *ignored_cmd,
++               const char *ignored_value)
++{
++      enum microblaze_abi global_abi = global_microblaze_abi ();
++      enum microblaze_abi actual_abi = microblaze_abi (target_gdbarch ());
++      const char *actual_abi_str = microblaze_abi_strings[actual_abi];
++
++#if 1 
++      if (global_abi == MICROBLAZE_ABI_AUTO)
++        fprintf_filtered
++          (file,
++           "The microblaze ABI is set automatically (currently \"%s\").\n",
++           actual_abi_str);    
++      else if (global_abi == actual_abi)
++        fprintf_filtered
++          (file,
++           "The microblaze ABI is assumed to be \"%s\" (due to user setting).\n",
++           actual_abi_str);
++      else
++        {
++#endif
++          /* Probably shouldn't happen...  */
++          fprintf_filtered (file,
++                            "The (auto detected) microblaze ABI \"%s\" is in use "
++                            "even though the user setting was \"%s\".\n",
++             actual_abi_str, microblaze_abi_strings[global_abi]);
++        }
++}                 
++
++static void
++show_microblaze_command (const char *args, int from_tty)
++{
++  help_list (showmicroblazecmdlist, "show microblaze ", all_commands, gdb_stdout);
++}
++
++static void
++set_microblaze_command (const char *args, int from_tty)
++{
++  printf_unfiltered
++    ("\"set microblaze\" must be followed by an appropriate subcommand.\n");
++  help_list (setmicroblazecmdlist, "set microblaze ", all_commands, gdb_stdout);
++}
++
+ static const char * const microblaze_register_names[] =
+ {
+   "r0",   "r1",  "r2",    "r3",   "r4",   "r5",   "r6",   "r7",
+@@ -85,9 +172,21 @@ static const char * const microblaze_register_names[] =
+ static unsigned int microblaze_debug_flag = 0;
+ int reg_size = 4;
+ 
++unsigned int
++microblaze_abi_regsize (struct gdbarch *gdbarch)
++{
++  switch (microblaze_abi (gdbarch))
++    {
++    case MICROBLAZE_ABI_M64:
++      return 8;
++    default:
++      return 4;
++    }
++}
++
+ #define microblaze_debug(fmt, ...) \
+   debug_prefixed_printf_cond_nofunc (microblaze_debug_flag, "MICROBLAZE", \
+-                                    fmt, ## __VA_ARGS__)
++                                     fmt, ## __VA_ARGS__)
+ 
+ 
+ /* Return the name of register REGNUM.  */
+@@ -867,15 +966,30 @@ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ {
+   tdesc_arch_data_up tdesc_data;
++  enum microblaze_abi microblaze_abi, found_abi, wanted_abi;
+   const struct target_desc *tdesc = info.target_desc;
+ 
++ /* What has the user specified from the command line?  */
++  wanted_abi = global_microblaze_abi ();
++  if (gdbarch_debug)
++    fprintf_unfiltered (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n",
++                        wanted_abi);
++  if (wanted_abi != MICROBLAZE_ABI_AUTO)
++    microblaze_abi = wanted_abi;
++
+   /* If there is already a candidate, use it.  */
+   arches = gdbarch_list_lookup_by_info (arches, &info);
+-  if (arches != NULL)
++  if ((arches != NULL) && (microblaze_abi != MICROBLAZE_ABI_M64))
+     return arches->gdbarch;
++
++  if (microblaze_abi == MICROBLAZE_ABI_M64)
++    {
++          tdesc = tdesc_microblaze64;
++          reg_size = 8;
++    }
+   if (tdesc == NULL)
+     {
+-      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) 
++      if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) 
+         {
+          tdesc = tdesc_microblaze64;
+           reg_size = 8;
+@@ -890,7 +1004,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+       int valid_p;
+       int i;
+ 
+-      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++      if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64))
+         feature = tdesc_find_feature (tdesc,
+                                     "org.gnu.gdb.microblaze64.core");
+       else
+@@ -904,7 +1018,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+       for (i = 0; i < MICROBLAZE_NUM_REGS; i++)
+         valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), i,
+                                             microblaze_register_names[i]);
+-      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++      if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64))
+         feature = tdesc_find_feature (tdesc,
+                                     "org.gnu.gdb.microblaze64.stack-protect");
+       else
+@@ -954,7 +1068,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+       set_gdbarch_ptr_bit (gdbarch, 64);
+     break;
+     }
+-
++  if(microblaze_abi == MICROBLAZE_ABI_M64)
++    set_gdbarch_ptr_bit (gdbarch, 64);
+   
+   /* Map Dwarf2 registers to GDB registers.  */
+   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum);
+@@ -1014,6 +1129,38 @@ _initialize_microblaze_tdep ()
+ {
+   gdbarch_register (bfd_arch_microblaze, microblaze_gdbarch_init);
+ 
++// static struct cmd_list_element *setmicroblazecmdlist = NULL;
++// static struct cmd_list_element *showmicroblazecmdlist = NULL;
++
++  /* Add root prefix command for all "set microblaze"/"show microblaze" commands.  */
++ 
++  add_setshow_prefix_cmd ("microblaze", no_class,
++                        _("Various microblaze specific commands."),
++                        _("Various microblaze specific commands."),
++                        &setmicroblazecmdlist,&showmicroblazecmdlist,
++                        &setlist,&showlist);
++#if 0
++  add_prefix_cmd ("microblaze", no_class, set_microblaze_command,
++                  _("Various microblaze specific commands."),
++                  &setmicroblazecmdlist, "set microblaze ", 0, &setlist);
++
++  add_prefix_cmd ("microblaze", no_class, show_microblaze_command,
++                  _("Various microblaze specific commands."),
++                  &showmicroblazecmdlist, "show microblaze ", 0, &showlist);
++#endif
++
++  /* Allow the user to override the ABI.  */
++  add_setshow_enum_cmd ("abi", class_obscure, microblaze_abi_strings,
++                        &microblaze_abi_string, _("\
++Set the microblaze ABI used by this program."), _("\
++Show the microblaze ABI used by this program."), _("\
++This option can be set to one of:\n\
++  auto  - the default ABI associated with the current binary\n\
++  m64"),
++                       microblaze_abi_update,
++                      show_microblaze_abi,
++                       &setmicroblazecmdlist, &showmicroblazecmdlist);
++  
+   initialize_tdesc_microblaze_with_stack_protect ();
+   initialize_tdesc_microblaze ();
+   initialize_tdesc_microblaze64_with_stack_protect ();
+@@ -1028,5 +1175,4 @@ When non-zero, microblaze specific debugging is enabled."),
+                             NULL,
+                             &setdebuglist, &showdebuglist);
+ 
+-
+ }
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 81f7f30cb8e..f6cef7c9a33 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -19,9 +19,17 @@
+ 
+ #ifndef MICROBLAZE_TDEP_H
+ #define MICROBLAZE_TDEP_H 1
+-
++#include "objfiles.h"
+ #include "gdbarch.h"
+ 
++struct gdbarch;
++enum microblaze_abi
++  {
++    MICROBLAZE_ABI_AUTO = 0,
++    MICROBLAZE_ABI_M64,
++ };
++
++enum microblaze_abi microblaze_abi (struct gdbarch *gdbarch);
+ /* Microblaze architecture-specific information.  */
+ struct microblaze_gregset
+ {
+@@ -35,11 +43,14 @@ struct microblaze_gdbarch_tdep : gdbarch_tdep_base
+ {
+   int dummy;           // declare something.
+ 
++  enum microblaze_abi microblaze_abi {};
++  enum microblaze_abi found_abi {};
+   /* Register sets.  */
+   struct regset *gregset;
+   size_t sizeof_gregset;
+   struct regset *fpregset;
+   size_t sizeof_fpregset;
++  int register_size;
+ };
+ 
+ /* Register numbers.  */
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0009-Depth-Total-number-of-inline-functions-refer-inline-.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0009-Depth-Total-number-of-inline-functions-refer-inline-.patch
new file mode 100644
index 00000000..6ec184d0
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0009-Depth-Total-number-of-inline-functions-refer-inline-.patch
@@ -0,0 +1,74 @@
+From bd2d24cf21943babe2e0a73cf68da273a38d7058 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 21 Jul 2022 11:45:01 +0530
+Subject: [PATCH 09/53] =?UTF-8?q?Depth:=20Total=20number=20of=20inline=20f?=
+ =?UTF-8?q?unctions=20[refer=20inline-frame.c]=20state->skipped=5Fframes?=
+ =?UTF-8?q?=20:=20Number=20of=20inline=20functions=20skipped.=20the=20curr?=
+ =?UTF-8?q?ent=20unwind=5Fpc=20is=20causing=20an=20issue=20when=20we=20try?=
+ =?UTF-8?q?=20to=20step=20into=20inline=20functions[Depth=20is=20becoming?=
+ =?UTF-8?q?=200].=20It=E2=80=99s=20incrementing=20pc=20by=208=20even=20wit?=
+ =?UTF-8?q?h=20si=20instruction.?=
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/features/microblaze64.xml |  1 +
+ gdb/microblaze-tdep.c         | 14 +++-----------
+ 2 files changed, 4 insertions(+), 11 deletions(-)
+
+diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml
+index 515d18e65cf..9c1b7d22003 100644
+--- a/gdb/features/microblaze64.xml
++++ b/gdb/features/microblaze64.xml
+@@ -7,5 +7,6 @@
+ 
+ <!DOCTYPE target SYSTEM "gdb-target.dtd">
+ <target>
++  <architecture>microblaze64</architecture>
+   <xi:include href="microblaze64-core.xml"/>
+ </target>
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 597507e53cd..aed5f2ec30c 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -513,16 +513,8 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+ static CORE_ADDR
+ microblaze_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame)
+ {
+-  gdb_byte buf[4];
+   CORE_ADDR pc;
+-
+-  frame_unwind_register (next_frame, MICROBLAZE_PC_REGNUM, buf);
+-  pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
+-  /* For sentinel frame, return address is actual PC.  For other frames,
+-     return address is pc+8.  This is a workaround because gcc does not
+-     generate correct return address in CIE.  */
+-  if (frame_relative_level (next_frame) >= 0)
+-    pc += 8;
++  pc=frame_unwind_register_unsigned (next_frame, MICROBLAZE_PC_REGNUM);
+   return pc;
+ }
+ 
+@@ -553,7 +545,6 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
+   ostart_pc = microblaze_analyze_prologue (gdbarch, func_start, 0xffffffffUL, 
+                                           &cache);
+ 
+-
+   if (ostart_pc > start_pc)
+     return ostart_pc;
+   return start_pc;
+@@ -660,7 +651,8 @@ static const struct frame_unwind microblaze_frame_unwind =
+   microblaze_frame_this_id,
+   microblaze_frame_prev_register,
+   NULL,
+-  default_frame_sniffer
++  default_frame_sniffer,
++  NULL,
+ };
+ 
+ static CORE_ADDR
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch
new file mode 100644
index 00000000..78e4970b
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch
@@ -0,0 +1,133 @@
+From 3616ef25911d9fa8b5c0e4883f19131da48896d5 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 29 Feb 2024 10:53:04 +0530
+Subject: [PATCH 10/53] Fix gdb-14 build errors for microblaze-xilinx-elf
+ 2023.2 merge
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elf64-microblaze.c | 12 ++++++++++++
+ gdb/frame.c            |  2 +-
+ gdb/microblaze-tdep.c  | 17 +++++++++++------
+ 3 files changed, 24 insertions(+), 7 deletions(-)
+
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index 6cd9753a592..119d266f95a 100755
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -750,6 +750,18 @@ microblaze_elf_info_to_howto (bfd * abfd,
+   return true;
+ }
+ 
++/* Relax table contains information about instructions which can
++   be removed by relaxation -- replacing a long address with a
++   short address.  */
++struct relax_table
++{
++  /* Address where bytes may be deleted.  */
++  bfd_vma addr;
++
++  /* Number of bytes to be deleted.  */
++  size_t size;
++};
++
+ struct _microblaze_elf_section_data
+ {
+   struct bfd_elf_section_data elf;
+diff --git a/gdb/frame.c b/gdb/frame.c
+index 859e1a6553d..94bb026c4d9 100644
+--- a/gdb/frame.c
++++ b/gdb/frame.c
+@@ -1319,7 +1319,7 @@ frame_unwind_register_value (frame_info_ptr next_frame, int regnum)
+              int i;
+ 
+              const gdb_byte *buf = NULL;
+-             if (value_entirely_available(value)) {
++             if (value->entirely_available()) {
+                gdb::array_view<const gdb_byte> buf = value->contents ();
+              }
+ 
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index aed5f2ec30c..e1a7a49eb84 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -75,7 +75,7 @@ static const char *const microblaze_abi_strings[] = {
+ enum microblaze_abi
+ microblaze_abi (struct gdbarch *gdbarch)
+ {
+-  microblaze_gdbarch_tdep *tdep = (microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch);
++  microblaze_gdbarch_tdep *tdep = gdbarch_tdep<microblaze_gdbarch_tdep> (gdbarch);
+   return tdep->microblaze_abi;
+ }
+ /* The registers of the Xilinx microblaze processor.  */
+@@ -120,12 +120,12 @@ show_microblaze_abi (struct ui_file *file,
+ 
+ #if 1 
+       if (global_abi == MICROBLAZE_ABI_AUTO)
+-        fprintf_filtered
++        gdb_printf
+           (file,
+            "The microblaze ABI is set automatically (currently \"%s\").\n",
+            actual_abi_str);    
+       else if (global_abi == actual_abi)
+-        fprintf_filtered
++        gdb_printf
+           (file,
+            "The microblaze ABI is assumed to be \"%s\" (due to user setting).\n",
+            actual_abi_str);
+@@ -133,7 +133,7 @@ show_microblaze_abi (struct ui_file *file,
+         {
+ #endif
+           /* Probably shouldn't happen...  */
+-          fprintf_filtered (file,
++          gdb_printf (file,
+                             "The (auto detected) microblaze ABI \"%s\" is in use "
+                             "even though the user setting was \"%s\".\n",
+              actual_abi_str, microblaze_abi_strings[global_abi]);
+@@ -934,7 +934,7 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
+                                      void *cb_data,
+                                      const struct regcache *regcache)
+ {
+-  struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch);
++  microblaze_gdbarch_tdep *tdep = gdbarch_tdep<microblaze_gdbarch_tdep> (gdbarch);
+ 
+   cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data);
+ 
+@@ -942,6 +942,8 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
+ }
+ 
+ 
++#if 0
++// compilation errors - function is not actually used ?
+ static void
+ make_regs (struct gdbarch *arch)
+ {
+@@ -953,6 +955,7 @@ make_regs (struct gdbarch *arch)
+       set_gdbarch_ptr_bit (arch, 64);
+     }
+ }
++#endif
+ 
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+@@ -964,7 +967,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+  /* What has the user specified from the command line?  */
+   wanted_abi = global_microblaze_abi ();
+   if (gdbarch_debug)
+-    fprintf_unfiltered (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n",
++    gdb_printf (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n",
+                         wanted_abi);
+   if (wanted_abi != MICROBLAZE_ABI_AUTO)
+     microblaze_abi = wanted_abi;
+@@ -1038,6 +1041,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   gdbarch *gdbarch
+     = gdbarch_alloc (&info, gdbarch_tdep_up (new microblaze_gdbarch_tdep));
+ 
++  microblaze_gdbarch_tdep *tdep = gdbarch_tdep<microblaze_gdbarch_tdep> (gdbarch);
++
+   tdep->gregset = NULL;
+   tdep->sizeof_gregset = 0;
+   tdep->fpregset = NULL;
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch
new file mode 100644
index 00000000..d3da41d5
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch
@@ -0,0 +1,28 @@
+From 9037b1a9e862263ba935314e8604a922d14c8dd4 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 29 Feb 2024 10:55:16 +0530
+Subject: [PATCH 11/53] fix gdb microblaze-xilinx-elf crash issue on invocation
+ Regression from merging microblaze 64-bit support
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/microblaze-tdep.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index e1a7a49eb84..f9cb3dfda33 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -1124,6 +1124,9 @@ void _initialize_microblaze_tdep ();
+ void
+ _initialize_microblaze_tdep ()
+ {
++  //Setting abi to auto manually, should be able to modify in 'arch'_gdbarch_init function
++  microblaze_abi_string = microblaze_abi_strings[0]; 
++
+   gdbarch_register (bfd_arch_microblaze, microblaze_gdbarch_init);
+ 
+ // static struct cmd_list_element *setmicroblazecmdlist = NULL;
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0012-Add-mlittle-endian-and-mbig-endian-flags.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0012-Add-mlittle-endian-and-mbig-endian-flags.patch
new file mode 100644
index 00000000..e1074c85
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0012-Add-mlittle-endian-and-mbig-endian-flags.patch
@@ -0,0 +1,46 @@
+From 05a5677c1b5cd7f109c49e6697b6716f7ac0fb97 Mon Sep 17 00:00:00 2001
+From: nagaraju <nmekala@xilix.com>
+Date: Tue, 19 Mar 2013 17:18:23 +0530
+Subject: [PATCH 12/53] Add mlittle-endian and mbig-endian flags
+
+Added support in gas for mlittle-endian and mbig-endian flags
+as options.
+
+Updated show usage for MicroBlaze specific assembler options
+to include new entries.
+
+Signed-off-by:nagaraju <nmekala@xilix.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index c971d187095..62238646a52 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -37,6 +37,8 @@
+ 
+ #define OPTION_EB (OPTION_MD_BASE + 0)
+ #define OPTION_EL (OPTION_MD_BASE + 1)
++#define OPTION_LITTLE (OPTION_MD_BASE + 2)
++#define OPTION_BIG (OPTION_MD_BASE + 3)
+ 
+ void microblaze_generate_symbol (char *sym);
+ static bool check_spl_reg (unsigned *);
+@@ -2565,9 +2567,11 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+   switch (c)
+     {
+     case OPTION_EB:
++    case OPTION_BIG:
+       target_big_endian = 1;
+       break;
+     case OPTION_EL:
++    case OPTION_LITTLE:
+       target_big_endian = 0;
+       break;
+     default:
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0013-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0013-Disable-the-warning-message-for-eh_frame_hdr.patch
new file mode 100644
index 00000000..31529d0d
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0013-Disable-the-warning-message-for-eh_frame_hdr.patch
@@ -0,0 +1,35 @@
+From a622ee3ff40515edf05a61a77fbcd8999ecf0905 Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Fri, 22 Jun 2012 01:20:20 +0200
+Subject: [PATCH 13/53] Disable the warning message for eh_frame_hdr
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+
+Conflicts:
+        bfd/elf-eh-frame.c
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elf-eh-frame.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c
+index 9a504234163..5e393558293 100644
+--- a/bfd/elf-eh-frame.c
++++ b/bfd/elf-eh-frame.c
+@@ -1045,10 +1045,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
+   goto success;
+ 
+  free_no_table:
++/* FIXME: Remove the microblaze specifics when relaxing gets fixed.  */
++if (bfd_get_arch(abfd) != bfd_arch_microblaze) {
+   _bfd_error_handler
+     /* xgettext:c-format */
+     (_("error in %pB(%pA); no .eh_frame_hdr table will be created"),
+      abfd, sec);
++}
+   hdr_info->u.dwarf.table = false;
+   free (sec_info);
+  success:
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0014-Fix-relaxation-of-assembler-resolved-references-Fixu.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0014-Fix-relaxation-of-assembler-resolved-references-Fixu.patch
new file mode 100644
index 00000000..7574067d
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0014-Fix-relaxation-of-assembler-resolved-references-Fixu.patch
@@ -0,0 +1,48 @@
+From 965a464418e8c8968453206f27763043fb38dc64 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 8 Nov 2016 11:54:08 +0530
+Subject: [PATCH 14/53] Fix relaxation of assembler resolved references,Fixup
+ debug_loc sections after linker relaxation Adds a new reloctype
+ R_MICROBLAZE_32_NONE, used for passing reloc info from the assembler to the
+ linker when the linker manages to fully resolve a local symbol reference.
+
+This is a workaround for design flaws in the assembler to
+linker interface with regards to linker relaxation.
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+
+Conflicts:
+        bfd/elf32-microblaze.c
+        binutils/readelf.c
+        include/elf/microblaze.h
+
+Conflicts:
+        binutils/readelf.c
+
+Conflicts:
+        bfd/elf32-microblaze.c
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ binutils/readelf.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/binutils/readelf.c b/binutils/readelf.c
+index 5e4ad6ea6ad..3ca9f3697d1 100644
+--- a/binutils/readelf.c
++++ b/binutils/readelf.c
+@@ -15288,6 +15288,11 @@ is_8bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
+              || reloc_type == 9 /* R_MICROBLAZE_64_NONE.  */);
+     default:
+       return false;
++    /* REVISIT microblaze-binutils-merge */
++    case EM_MICROBLAZE:
++      return reloc_type == 33 /* R_MICROBLAZE_32_NONE.  */
++             || reloc_type == 0 /* R_MICROBLAZE_NONE.  */
++             || reloc_type == 9; /* R_MICROBLAZE_64_NONE.  */
+     }
+ }
+ 
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0015-upstream-change-to-garbage-collection-sweep-causes-m.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0015-upstream-change-to-garbage-collection-sweep-causes-m.patch
new file mode 100644
index 00000000..c46af2e7
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0015-upstream-change-to-garbage-collection-sweep-causes-m.patch
@@ -0,0 +1,43 @@
+From 07743ed9395bfea466cdbdf0bbe9566fa93165de Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Wed, 27 Feb 2013 13:56:11 +1000
+Subject: [PATCH 15/53] upstream change to garbage collection sweep causes mb
+ regression
+
+Upstream change for PR13177 now clears the def_regular during gc_sweep of a
+section. (All other archs in binutils/bfd/elf32-*.c received an update
+to a warning about unresolvable relocations - this warning is not present
+in binutils/bfd/elf32-microblaze.c, but this warning check would not
+prevent the error being seen)
+
+The visible issue with this change is when running a c++ application
+in Petalinux which links libstdc++.so for exception handling it segfaults
+on execution.
+
+This does not occur if static linking libstdc++.a, so its during the
+relocations for a shared lib with garbage collection this occurs
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+
+Conflicts:
+        bfd/elflink.c
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elflink.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/bfd/elflink.c b/bfd/elflink.c
+index c2494b3e12e..1f8f54cd4e6 100644
+--- a/bfd/elflink.c
++++ b/bfd/elflink.c
+@@ -6633,7 +6633,6 @@ elf_gc_sweep_symbol (struct elf_link_hash_entry *h, void *data)
+ 
+       inf = (struct elf_gc_sweep_symbol_info *) data;
+       (*inf->hide_symbol) (inf->info, h, true);
+-      h->def_regular = 0;
+       h->ref_regular = 0;
+       h->ref_regular_nonweak = 0;
+     }
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0016-Add-new-bit-field-instructions.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0016-Add-new-bit-field-instructions.patch
new file mode 100644
index 00000000..aab6c5d1
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0016-Add-new-bit-field-instructions.patch
@@ -0,0 +1,219 @@
+From 39ef5af3dd4551b24a47c8e48af67478183a7149 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 18 Jul 2016 12:24:28 +0530
+Subject: [PATCH 16/53] Add new bit-field instructions
+
+This patches adds new bsefi and bsifi instructions.
+BSEFI- The instruction shall extract a bit field from a
+register and place it right-adjusted in the destination register.
+The other bits in the destination register shall be set to zero
+BSIFI- The instruction shall insert a right-adjusted bit field
+from a register at another position in the destination register.
+The rest of the bits in the destination register shall be unchanged
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+
+Conflicts:
+        opcodes/microblaze-dis.c
+
+Conflicts:
+        gas/config/tc-microblaze.c
+        opcodes/microblaze-opc.h
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c | 82 ++++++++++++++++----------------------
+ opcodes/microblaze-dis.c   | 18 ++++++++-
+ opcodes/microblaze-opc.h   |  6 +++
+ 3 files changed, 58 insertions(+), 48 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 62238646a52..f13efcae979 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -1150,88 +1150,76 @@ md_assemble (char * str)
+       inst |= (reg2 << RA_LOW) & RA_MASK;
+       inst |= (immed << IMM_LOW) & IMM5_MASK;
+       break;
+-
+-    case INST_TYPE_RD_R1_IMMW_IMMS:
++ case INST_TYPE_RD_R1_IMM5_IMM5:
+       if (strcmp (op_end, ""))
+-       op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
++        op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
+       else
+        {
+-         as_fatal (_("Error in statement syntax"));
+-         reg1 = 0;
+-       }
+-
++          as_fatal (_("Error in statement syntax"));
++          reg1 = 0;
++        }
+       if (strcmp (op_end, ""))
+-       op_end = parse_reg (op_end + 1, &reg2);  /* Get r1.  */
++        op_end = parse_reg (op_end + 1, &reg2);  /* Get r1.  */
+       else
+        {
+-         as_fatal (_("Error in statement syntax"));
+-         reg2 = 0;
+-       }
++          as_fatal (_("Error in statement syntax"));
++          reg2 = 0;
++        }
+ 
+       /* Check for spl registers.  */
+       if (check_spl_reg (&reg1))
+-       as_fatal (_("Cannot use special register with this instruction"));
++        as_fatal (_("Cannot use special register with this instruction"));
+       if (check_spl_reg (&reg2))
+-       as_fatal (_("Cannot use special register with this instruction"));
++        as_fatal (_("Cannot use special register with this instruction"));
+ 
+       /* Width immediate value.  */
+       if (strcmp (op_end, ""))
+-       op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
++        op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
+       else
+-       as_fatal (_("Error in statement syntax"));
+-
++        as_fatal (_("Error in statement syntax"));
+       if (exp.X_op != O_constant)
+        {
+-         as_warn (_(
+-         "Symbol used as immediate width value for bit field instruction"));
+-         immed = 1;
+-       }
++          as_warn (_("Symbol used as immediate width value for bit field instruction"));
++          immed = 1;
++        }
+       else
+-       immed = exp.X_add_number;
+-
++        immed = exp.X_add_number;
+       if (opcode->instr == bsefi && immed > 31)
+-       as_fatal (_("Width value must be less than 32"));
++        as_fatal (_("Width value must be less than 32"));
+ 
+       /* Shift immediate value.  */
+       if (strcmp (op_end, ""))
+-       op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
++        op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
+       else
+-       as_fatal (_("Error in statement syntax"));
+-
++        as_fatal (_("Error in statement syntax"));
+       if (exp.X_op != O_constant)
+-       {
+-         as_warn (_(
+-         "Symbol used as immediate shift value for bit field instruction"));
+-         immed2 = 0;
+-       }
++           {
++          as_warn (_("Symbol used as immediate shift value for bit field instruction"));
++          immed2 = 0;
++        }
+       else
+-       {
+-         output = frag_more (isize);
+-         immed2 = exp.X_add_number;
+-       }
+-
++           {
++          output = frag_more (isize);
++          immed2 = exp.X_add_number;
++           }
+       if (immed2 != (immed2 % 32))
+-       {
+-         as_warn (_("Shift value greater than 32. using <value %% 32>"));
+-         immed2 = immed2 % 32;
+-       }
++           {
++          as_warn (_("Shift value greater than 32. using <value %% 32>"));
++          immed2 = immed2 % 32;
++        }
+ 
+       /* Check combined value.  */
+       if (immed + immed2 > 32)
+-       as_fatal (_("Width value + shift value must not be greater than 32"));
++        as_fatal (_("Width value + shift value must not be greater than 32"));
+ 
+       inst |= (reg1 << RD_LOW) & RD_MASK;
+       inst |= (reg2 << RA_LOW) & RA_MASK;
+-
+       if (opcode->instr == bsefi)
+-       inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
++        inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
+       else
+-       inst |= ((immed + immed2 - 1) & IMM5_MASK)
+-               << IMM_WIDTH_LOW; /* bsifi */
+-
++        inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */
+       inst |= (immed2 << IMM_LOW) & IMM5_MASK;
+       break;
+-
+     case INST_TYPE_R1_R2:
+       if (strcmp (op_end, ""))
+         op_end = parse_reg (op_end + 1, &reg1);  /* Get r1.  */
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index ee447cecc3f..45135f9d264 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -113,7 +113,19 @@ get_field_immw (struct string_buf *buf, long instr)
+ }
+ 
+ static char *
+-get_field_rfsl (struct string_buf *buf, long instr)
++get_field_imm5width (struct string_buf *buf, long instr)
++{
++  char *p = strbuf (buf);
++
++  if (instr & 0x00004000)
++    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
++ else
++    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
++  return p;
++}
++
++static char *
++get_field_rfsl (struct string_buf *buf,long instr)
+ {
+   char *p = strbuf (buf);
+ 
+@@ -462,6 +474,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst),
+                   get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+          break;
++        /* For bit field insns.  */
++       case INST_TYPE_RD_R1_IMM5_IMM5:
++          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
++            break;
+        /* For tuqula instruction */
+        case INST_TYPE_RD:
+          print_func (stream, "\t%s", get_field_rd (&buf, inst));
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index afc1220e357..a952b9ac3c2 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -67,6 +67,9 @@
+ #define INST_TYPE_RD_R1_IMML 23
+ #define INST_TYPE_R1_IMML 24
+ 
++/* For bsefi and bsifi */
++#define INST_TYPE_RD_R1_IMM5_IMM5  21
++
+ #define INST_TYPE_NONE 25
+ 
+ 
+@@ -586,5 +589,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMML  ((long) 0xffffff8000000000L)
+ #define MAX_IMML  ((long) 0x0000007fffffffffL)
+ 
++#define MIN_IMM_WIDTH  ((int) 0x00000001)
++#define MAX_IMM_WIDTH  ((int) 0x00000020)
++
+ #endif /* MICROBLAZE_OPC */
+ 
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0017-fixed-bug-in-GCC-so-that-It-will-support-.long-0U-an.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0017-fixed-bug-in-GCC-so-that-It-will-support-.long-0U-an.patch
new file mode 100644
index 00000000..f679971d
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0017-fixed-bug-in-GCC-so-that-It-will-support-.long-0U-an.patch
@@ -0,0 +1,34 @@
+From ea27bc6ec052b20f4c193054ecdef9bd4ecbcde7 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Fri, 29 Sep 2017 18:00:23 +0530
+Subject: [PATCH 17/53] fixed bug in GCC so that It will support .long 0U and
+ .long 0u
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/expr.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/gas/expr.c b/gas/expr.c
+index 3a01b88e310..8214bdf3263 100644
+--- a/gas/expr.c
++++ b/gas/expr.c
+@@ -833,6 +833,15 @@ operand (expressionS *expressionP, enum expr_mode mode)
+              break;
+            }
+        }
++      if ((*input_line_pointer == 'U') || (*input_line_pointer == 'u'))
++      {
++      input_line_pointer--;
++
++      integer_constant ((NUMBERS_WITH_SUFFIX || flag_m68k_mri)
++                        ? 0 : 10,
++                        expressionP);
++      break;
++      }
+       c = *input_line_pointer;
+       switch (c)
+        {
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0018-Compiler-will-give-error-messages-in-more-detail-for.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0018-Compiler-will-give-error-messages-in-more-detail-for.patch
new file mode 100644
index 00000000..c63f4566
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0018-Compiler-will-give-error-messages-in-more-detail-for.patch
@@ -0,0 +1,37 @@
+From 3056650d65b5bfa34bf16cd1ee7829a64dfb19ac Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 21 Feb 2018 12:32:02 +0530
+Subject: [PATCH 18/53] Compiler will give error messages in more detail for
+ mxl-gp-opt flag..
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ ld/ldmain.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/ld/ldmain.c b/ld/ldmain.c
+index e90c2021b33..e135939fade 100644
+--- a/ld/ldmain.c
++++ b/ld/ldmain.c
+@@ -1575,6 +1575,18 @@ reloc_overflow (struct bfd_link_info *info,
+          break;
+        case bfd_link_hash_defined:
+        case bfd_link_hash_defweak:
++
++         if((strcmp(reloc_name,"R_MICROBLAZE_SRW32") == 0) &&  entry->type == bfd_link_hash_defined)
++         {
++         einfo (_(" relocation truncated to fit: don't enable small data pointer optimizations[mxl-gp-opt] if extern or multiple declarations used: "
++                "%s against symbol `%T' defined in %A section in %B"),
++                 reloc_name, entry->root.string,
++                 entry->u.def.section,
++                 entry->u.def.section == bfd_abs_section_ptr
++                  ? info->output_bfd : entry->u.def.section->owner);
++             break;
++         }
++
+          einfo (_(" relocation truncated to fit: "
+                   "%s against symbol `%pT' defined in %pA section in %pB"),
+                 reloc_name, entry->root.string,
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0019-initial-support-for-MicroBlaze-64-bit-m64.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0019-initial-support-for-MicroBlaze-64-bit-m64.patch
new file mode 100644
index 00000000..452c1418
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0019-initial-support-for-MicroBlaze-64-bit-m64.patch
@@ -0,0 +1,202 @@
+From 06c3e8ef9bdea329af1099e14abbde3d76a114a9 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 1 Nov 2021 19:06:53 +0530
+Subject: [PATCH 19/53] initial support for MicroBlaze 64 bit [-m64]
+
+Conflicts:
+        bfd/elf32-microblaze.c
+        include/elf/common.h
+        ld/Makefile.am
+        ld/Makefile.in
+signed-off-by:Nagaraju Mekala<nmekala@xilinx.com>
+              Mahesh Bodapati<mbodapat@xilinx.com>
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/bfd-in2.h              | 14 ++++++++++++--
+ bfd/libbfd.h               |  2 ++
+ bfd/reloc.c                | 18 +++++++++++++++---
+ gas/config/tc-microblaze.h |  4 +++-
+ ld/Makefile.am             |  2 ++
+ ld/configure.tgt           |  3 +++
+ opcodes/microblaze-dis.c   |  8 ++++++--
+ opcodes/microblaze-opc.h   | 11 +++++++----
+ 8 files changed, 50 insertions(+), 12 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 7ccc155394d..8b2815d7303 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -6472,8 +6472,13 @@ done here - only used for relaxing  */
+     BFD_RELOC_MICROBLAZE_64_NONE,
+ 
+   /* This is a 64 bit reloc that stores the 32 bit pc relative value in
+-     two words (with an imm instruction).  The relocation is PC-relative
+-     GOT offset.  */
++     two words (with an imm instruction).  No relocation is done here
++     only used for relaxing  */
++    BFD_RELOC_MICROBLAZE_64,
++
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++value in two words (with an imm instruction).  The relocation is
++PC-relative GOT offset  */
+   BFD_RELOC_MICROBLAZE_64_GOTPC,
+ 
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+@@ -6481,6 +6486,11 @@ value in two words (with an imml instruction).  The relocation is
+ PC-relative GOT offset  */
+   BFD_RELOC_MICROBLAZE_64_GPC,
+ 
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++value in two words (with an imml instruction).  The relocation is
++PC-relative GOT offset  */
++  BFD_RELOC_MICROBLAZE_64_GPC,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  The relocation is
+ GOT offset  */
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index 7a3e558d70a..603ed8260cb 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -3005,7 +3005,9 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
+   "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
++  "BFD_RELOC_MICROBLAZE_64",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
++  "BFD_RELOC_MICROBLAZE_64_GPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+   "BFD_RELOC_MICROBLAZE_64_PLT",
+   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index fda67e5ffda..3e8647f601e 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6677,12 +6677,24 @@ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative value in
+   two words (with an imm instruction).  No relocation is done here -
+   only used for relaxing.
++ENUM
++  BFD_RELOC_MICROBLAZE_64
++ENUMDOC
++  This is a 64 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imm instruction).  No relocation is
++  done here - only used for relaxing
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_GOTPC
+ ENUMDOC
+-  This is a 64 bit reloc that stores the 32 bit pc relative value in
+-  two words (with an imm instruction).  The relocation is PC-relative
+-  GOT offset.
++  This is a 64 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imml instruction).  No relocation is
++  done here - only used for relaxing
++ENUM
++  BFD_RELOC_MICROBLAZE_64_GPC
++ENUMDOC
++  This is a 64 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imm instruction).  The relocation is
++  PC-relative GOT offset
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_GOT
+ ENUMDOC
+diff --git a/gas/config/tc-microblaze.h b/gas/config/tc-microblaze.h
+index 20d0da5496d..f0f861c3373 100644
+--- a/gas/config/tc-microblaze.h
++++ b/gas/config/tc-microblaze.h
+@@ -81,7 +81,9 @@ extern const struct relax_type md_relax_table[];
+ 
+ #ifdef OBJ_ELF
+ 
+-#define TARGET_FORMAT (target_big_endian ? "elf32-microblaze" : "elf32-microblazeel")
++#define TARGET_FORMAT microblaze_target_format()
++extern const char *microblaze_target_format (void);
++//#define TARGET_FORMAT (target_big_endian ? "elf32-microblaze" : "elf32-microblazeel")
+ 
+ #define ELF_TC_SPECIAL_SECTIONS \
+   { ".sdata",          SHT_PROGBITS,   SHF_ALLOC + SHF_WRITE }, \
+diff --git a/ld/Makefile.am b/ld/Makefile.am
+index f9ee05b1400..c1daf842444 100644
+--- a/ld/Makefile.am
++++ b/ld/Makefile.am
+@@ -424,6 +424,8 @@ ALL_64_EMULATION_SOURCES = \
+        eelf32ltsmipn32.c \
+        eelf32ltsmipn32_fbsd.c \
+        eelf32mipswindiss.c \
++        eelf64microblazeel.c \
++        eelf64microblaze.c \
+        eelf64_aix.c \
+        eelf64_ia64.c \
+        eelf64_ia64_fbsd.c \
+diff --git a/ld/configure.tgt b/ld/configure.tgt
+index f937f78b876..a9d3004e445 100644
+--- a/ld/configure.tgt
++++ b/ld/configure.tgt
+@@ -527,6 +527,9 @@ microblaze*-linux*) targ_emul="elf32mb_linux"
+ microblazeel*)         targ_emul=elf32microblazeel
+                        targ_extra_emuls=elf32microblaze
+                        ;;
++microblazeel64*)       targ_emul=elf64microblazeel
++                       targ_extra_emuls=elf64microblaze
++                       ;;
+ microblaze*)           targ_emul=elf32microblaze
+                        targ_extra_emuls=elf32microblazeel
+                        ;;
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 45135f9d264..45262aef909 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -457,6 +457,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+        case INST_TYPE_R1_R2_SPECIAL:
+          print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
+                      get_field_r2 (&buf, inst));
++          break;
++        case INST_TYPE_IMML:
++         print_func (stream, "\t%s", get_field_imml (&buf, inst));
++          /* TODO: Also print symbol */
+          break;
+        case INST_TYPE_RD_IMM15:
+          print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
+@@ -475,8 +479,8 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+                   get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+          break;
+         /* For bit field insns.  */
+-       case INST_TYPE_RD_R1_IMM5_IMM5:
+-          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
++       case INST_TYPE_RD_R1_IMMW_IMMS:
++          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+             break;
+        /* For tuqula instruction */
+        case INST_TYPE_RD:
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index a952b9ac3c2..d9d05721dae 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -68,7 +68,13 @@
+ #define INST_TYPE_R1_IMML 24
+ 
+ /* For bsefi and bsifi */
+-#define INST_TYPE_RD_R1_IMM5_IMM5  21
++#define INST_TYPE_RD_R1_IMMW_IMMS  21
++
++/* For 64-bit instructions */
++#define INST_TYPE_IMML 22
++#define INST_TYPE_RD_R1_IMML 23
++#define INST_TYPE_R1_IMML 24
++#define INST_TYPE_RD_R1_IMMW_IMMS  21
+ 
+ #define INST_TYPE_NONE 25
+ 
+@@ -589,8 +595,5 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMML  ((long) 0xffffff8000000000L)
+ #define MAX_IMML  ((long) 0x0000007fffffffffL)
+ 
+-#define MIN_IMM_WIDTH  ((int) 0x00000001)
+-#define MAX_IMM_WIDTH  ((int) 0x00000020)
+-
+ #endif /* MICROBLAZE_OPC */
+ 
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0020-initial-support-for-MicroBlaze-64-bit-m64.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0020-initial-support-for-MicroBlaze-64-bit-m64.patch
new file mode 100644
index 00000000..f3073f1e
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0020-initial-support-for-MicroBlaze-64-bit-m64.patch
@@ -0,0 +1,82 @@
+From f46a81a4ffa73453403a5e99e7005a8f1d974ecf Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 1 Nov 2021 19:06:53 +0530
+Subject: [PATCH 20/53] initial support for MicroBlaze 64 bit [-m64]
+
+Conflicts:
+        bfd/elf32-microblaze.c
+        include/elf/common.h
+        ld/Makefile.am
+        ld/Makefile.in
+signed-off-by:Nagaraju Mekala<nmekala@xilinx.com>
+              Mahesh Bodapati<mbodapat@xilinx.com>
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ ld/emulparams/elf64microblaze.sh   | 23 +++++++++++++++++++++++
+ ld/emulparams/elf64microblazeel.sh | 23 +++++++++++++++++++++++
+ 2 files changed, 46 insertions(+)
+ create mode 100644 ld/emulparams/elf64microblaze.sh
+ create mode 100644 ld/emulparams/elf64microblazeel.sh
+
+diff --git a/ld/emulparams/elf64microblaze.sh b/ld/emulparams/elf64microblaze.sh
+new file mode 100644
+index 00000000000..9c7b0eb7080
+--- /dev/null
++++ b/ld/emulparams/elf64microblaze.sh
+@@ -0,0 +1,23 @@
++SCRIPT_NAME=elfmicroblaze
++OUTPUT_FORMAT="elf64-microblazeel"
++#BIG_OUTPUT_FORMAT="elf64-microblaze"
++LITTLE_OUTPUT_FORMAT="elf64-microblazeel"
++#TEXT_START_ADDR=0
++NONPAGED_TEXT_START_ADDR=0x28
++ALIGNMENT=4
++MAXPAGESIZE=4
++ARCH=microblaze
++EMBEDDED=yes
++
++NOP=0x80000000
++
++# Hmmm, there's got to be a better way.  This sets the stack to the
++# top of the simulator memory (2^19 bytes).
++#PAGE_SIZE=0x1000
++#DATA_ADDR=0x10000
++#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }'
++#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
++#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
++
++TEMPLATE_NAME=elf32
++#GENERATE_SHLIB_SCRIPT=yes
+diff --git a/ld/emulparams/elf64microblazeel.sh b/ld/emulparams/elf64microblazeel.sh
+new file mode 100644
+index 00000000000..9c7b0eb7080
+--- /dev/null
++++ b/ld/emulparams/elf64microblazeel.sh
+@@ -0,0 +1,23 @@
++SCRIPT_NAME=elfmicroblaze
++OUTPUT_FORMAT="elf64-microblazeel"
++#BIG_OUTPUT_FORMAT="elf64-microblaze"
++LITTLE_OUTPUT_FORMAT="elf64-microblazeel"
++#TEXT_START_ADDR=0
++NONPAGED_TEXT_START_ADDR=0x28
++ALIGNMENT=4
++MAXPAGESIZE=4
++ARCH=microblaze
++EMBEDDED=yes
++
++NOP=0x80000000
++
++# Hmmm, there's got to be a better way.  This sets the stack to the
++# top of the simulator memory (2^19 bytes).
++#PAGE_SIZE=0x1000
++#DATA_ADDR=0x10000
++#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }'
++#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
++#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
++
++TEMPLATE_NAME=elf32
++#GENERATE_SHLIB_SCRIPT=yes
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0021-Added-relocations-for-MB-X.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0021-Added-relocations-for-MB-X.patch
new file mode 100644
index 00000000..24e0894d
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0021-Added-relocations-for-MB-X.patch
@@ -0,0 +1,108 @@
+From 39ba1e8a13828ac3c860a72b95c3abae024044b5 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 11 Sep 2018 17:30:17 +0530
+Subject: [PATCH 21/53] Added relocations for MB-X
+
+Conflicts:
+        bfd/bfd-in2.h
+        gas/config/tc-microblaze.c
+
+Conflicts:
+        gas/config/tc-microblaze.c
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/reloc.c                | 26 ++++++++++++++------------
+ gas/config/tc-microblaze.c | 11 +++++++++++
+ 2 files changed, 25 insertions(+), 12 deletions(-)
+
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index 3e8647f601e..c5c0ce5d060 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6661,12 +6661,6 @@ ENUMDOC
+   the form "Symbol Op Symbol".
+ ENUM
+   BFD_RELOC_MICROBLAZE_32_NONE
+-ENUMDOC
+-  This is a 32 bit reloc that stores the 32 bit pc relative value in
+-  two words (with an imm instruction).  No relocation is done here -
+-  only used for relaxing.
+-ENUM
+-  BFD_RELOC_MICROBLAZE_32_NONE
+ ENUMDOC
+   This is a 32 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  No relocation is
+@@ -6685,12 +6679,6 @@ ENUMDOC
+   done here - only used for relaxing
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_GOTPC
+-ENUMDOC
+-  This is a 64 bit reloc that stores the 32 bit pc relative
+-  value in two words (with an imml instruction).  No relocation is
+-  done here - only used for relaxing
+-ENUM
+-  BFD_RELOC_MICROBLAZE_64_GPC
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  The relocation is
+@@ -7929,6 +7917,20 @@ ENUMX
+ ENUMDOC
+   Linux eBPF relocations.
+ 
++  This is a 64 bit reloc that stores 64-bit thread pointer relative offset
++  to two words (uses imml instruction).
++ENUM
++BFD_RELOC_MICROBLAZE_64,
++ENUMDOC
++ This is a 64 bit reloc that stores the 64 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
++ENUM
++BFD_RELOC_MICROBLAZE_64_PCREL,
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
+ ENUM
+   BFD_RELOC_EPIPHANY_SIMM8
+ ENUMDOC
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index f13efcae979..9b8b129e309 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -91,6 +91,8 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP";
+ #define TLSTPREL_OFFSET      16
+ #define TEXT_OFFSET         17
+ #define TEXT_PC_OFFSET       18
++#define DEFINED_64_OFFSET   19
++#define DEFINED_64_PC_OFFSET 20 
+ 
+ /* Initialize the relax table.  */
+ const relax_typeS md_relax_table[] =
+@@ -114,6 +116,8 @@ const relax_typeS md_relax_table[] =
+   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 16: TLSTPREL_OFFSET.  */
+   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 17: TEXT_OFFSET.  */
+   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }   /* 18: TEXT_PC_OFFSET.  */
++  { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 },   /* 19: DEFINED_64_OFFSET.  */
++  { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE*2, 0 }   /* 20: DEFINED_64_PC_OFFSET.  */
+ };
+ 
+ static htab_t  opcode_hash_control;    /* Opcode mnemonics.  */
+@@ -2330,6 +2334,13 @@ md_estimate_size_before_relax (fragS * fragP,
+              /* Variable part does not change.  */
+              fragP->fr_var = INST_WORD_SIZE*2;
+            }
++         else if (streq (fragP->fr_opcode, str_microblaze_64))
++           {
++              /* Used as an absolute value.  */
++              fragP->fr_subtype = DEFINED_64_OFFSET;
++              /* Variable part does not change.  */
++              fragP->fr_var = INST_WORD_SIZE;
++            }
+          else if (streq (fragP->fr_opcode, str_microblaze_ro_anchor))
+            {
+               /* It is accessed using the small data read only anchor.  */
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0022-initial-support-for-MicroBlaze-64-bit-m64.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0022-initial-support-for-MicroBlaze-64-bit-m64.patch
new file mode 100644
index 00000000..5ef086bd
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0022-initial-support-for-MicroBlaze-64-bit-m64.patch
@@ -0,0 +1,958 @@
+From 6e30e2ce72e9257daae0633a6b57e7a5c4c918f2 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 1 Nov 2021 19:06:53 +0530
+Subject: [PATCH 22/53] initial support for MicroBlaze 64 bit [-m64]
+
+Conflicts:
+        bfd/elf32-microblaze.c
+        include/elf/common.h
+        ld/Makefile.am
+        ld/Makefile.in
+signed-off-by:Nagaraju Mekala<nmekala@xilinx.com>
+              Mahesh Bodapati<mbodapat@xilinx.com>
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elf64-microblaze.c     |   8 +
+ bfd/reloc.c                |  36 +--
+ gas/config/tc-microblaze.c | 556 ++++++++++++++++++++++++++++++++-----
+ 3 files changed, 499 insertions(+), 101 deletions(-)
+
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index 119d266f95a..ca92df647c9 100755
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -1666,6 +1666,14 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+                            outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL);
+                            outrel.r_addend = relocation + addend;
+                          }
++                       unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
++                        if (insn == 0xb2000000 || insn == 0xb2ffffff)
++                          {
++                            insn &= ~0x00ffffff;
++                            insn |= (relocation >> 16) & 0xffffff;
++                            bfd_put_32 (input_bfd, insn,
++                                    contents + offset + endian);
++                          }
+                        else
+                          {
+                            BFD_FAIL ();
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index c5c0ce5d060..6eb93e993f0 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6677,8 +6677,20 @@ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  No relocation is
+   done here - only used for relaxing
++ENUM
++BFD_RELOC_MICROBLAZE_64_PCREL,
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_GOTPC
++ENUMDOC
++  This is a 64 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imml instruction).  No relocation is
++  done here - only used for relaxing
++ENUM
++  BFD_RELOC_MICROBLAZE_64_GPC
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  The relocation is
+@@ -7894,18 +7906,6 @@ ENUMDOC
+ 
+   This is a 64 bit reloc that stores 64-bit thread pointer relative offset
+   to two words (uses imml instruction).
+-ENUM
+-BFD_RELOC_MICROBLAZE_64,
+-ENUMDOC
+- This is a 64 bit reloc that stores the 64 bit pc relative
+- value in two words (with an imml instruction).  No relocation is
+- done here - only used for relaxing
+-ENUM
+-BFD_RELOC_MICROBLAZE_64_PCREL,
+-ENUMDOC
+- This is a 32 bit reloc that stores the 32 bit pc relative
+- value in two words (with an imml instruction).  No relocation is
+- done here - only used for relaxing
+ ENUM
+   BFD_RELOC_BPF_64
+ ENUMX
+@@ -7919,18 +7919,6 @@ ENUMDOC
+ 
+   This is a 64 bit reloc that stores 64-bit thread pointer relative offset
+   to two words (uses imml instruction).
+-ENUM
+-BFD_RELOC_MICROBLAZE_64,
+-ENUMDOC
+- This is a 64 bit reloc that stores the 64 bit pc relative
+- value in two words (with an imml instruction).  No relocation is
+- done here - only used for relaxing
+-ENUM
+-BFD_RELOC_MICROBLAZE_64_PCREL,
+-ENUMDOC
+- This is a 32 bit reloc that stores the 32 bit pc relative
+- value in two words (with an imml instruction).  No relocation is
+- done here - only used for relaxing
+ ENUM
+   BFD_RELOC_EPIPHANY_SIMM8
+ ENUMDOC
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 9b8b129e309..6640266cc47 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -35,10 +35,13 @@
+ #define streq(a,b) (strcmp (a, b) == 0)
+ #endif
+ 
++static int microblaze_arch_size = 0;
++
+ #define OPTION_EB (OPTION_MD_BASE + 0)
+ #define OPTION_EL (OPTION_MD_BASE + 1)
+ #define OPTION_LITTLE (OPTION_MD_BASE + 2)
+ #define OPTION_BIG (OPTION_MD_BASE + 3)
++#define OPTION_M64 (OPTION_MD_BASE + 4)
+ 
+ void microblaze_generate_symbol (char *sym);
+ static bool check_spl_reg (unsigned *);
+@@ -360,7 +363,7 @@ microblaze_s_weakext (int ignore ATTRIBUTE_UNUSED)
+    Integer arg to pass to the function.  */
+ /* If the pseudo-op is not found in this table, it searches in the obj-elf.c,
+    and then in the read.c table.  */
+-const pseudo_typeS md_pseudo_table[] =
++pseudo_typeS md_pseudo_table[] =
+ {
+   {"lcomm", microblaze_s_lcomm, 1},
+   {"data8", cons, 1},      /* Same as byte.  */
+@@ -369,6 +372,7 @@ const pseudo_typeS md_pseudo_table[] =
+   {"ent", s_func, 0}, /* Treat ent as function entry point.  */
+   {"end", microblaze_s_func, 1}, /* Treat end as function end point.  */
+   {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section.  */
++   {"gpdword", s_rva, 8}, /* gpword label => store resolved label address in data section.  */
+   {"weakext", microblaze_s_weakext, 0},
+   {"rodata", microblaze_s_rdata, 0},
+   {"sdata2", microblaze_s_rdata, 1},
+@@ -378,6 +382,7 @@ const pseudo_typeS md_pseudo_table[] =
+ #endif
+   {"sbss", microblaze_s_sbss, 0},
+   {"word", cons, 4},
++  {"dword", cons, 8},
+   {"frame", s_ignore, 0},
+   {"mask", s_ignore, 0}, /* Emitted by gcc.  */
+   {NULL, NULL, 0}
+@@ -749,6 +754,74 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max)
+   return new_pointer;
+ }
+ 
++ static char *
++parse_imml (char * s, expressionS * e, long min, long max)
++{
++  char *new_pointer;
++  char *atp;
++  int itype, ilen;
++
++  ilen = 0;
++
++  /* Find the start of "@GOT" or "@PLT" suffix (if any) */
++  for (atp = s; *atp != '@'; atp++)
++    if (is_end_of_line[(unsigned char) *atp])
++      break;
++
++  if (*atp == '@')
++    {
++      itype = match_imm (atp + 1, &ilen);
++      if (itype != 0)
++        {
++          *atp = 0;
++          e->X_md = itype;
++        }
++      else
++        {
++          atp = NULL;
++          e->X_md = 0;
++          ilen = 0;
++        }
++      *atp = 0;
++    }
++  else
++    {
++      atp = NULL;
++      e->X_md = 0;
++    }
++
++  if (atp && !GOT_symbol)
++    {
++      GOT_symbol = symbol_find_or_make (GOT_SYMBOL_NAME);
++    }
++
++  new_pointer = parse_exp (s, e);
++
++  if (!GOT_symbol && ! strncmp (s, GOT_SYMBOL_NAME, 20))
++    {
++      GOT_symbol = symbol_find_or_make (GOT_SYMBOL_NAME);
++    }
++
++  if (e->X_op == O_absent)
++    ; /* An error message has already been emitted.  */
++  else if ((e->X_op != O_constant && e->X_op != O_symbol) )
++    as_fatal (_("operand must be a constant or a label"));
++  else if ((e->X_op == O_constant) && ((long) e->X_add_number < min
++                                      || (long) e->X_add_number > max))
++    {
++      as_fatal (_("operand must be absolute in range %ld..%ld, not %ld"),
++                min, max, (long) e->X_add_number);
++    }
++
++  if (atp)
++    {
++      *atp = '@'; /* restore back (needed?)  */
++      if (new_pointer >= atp)
++        new_pointer += ilen + 1; /* sizeof (imm_suffix) + 1 for '@' */
++    }
++  return new_pointer;
++}
++
+ static char *
+ check_got (int * got_type, int * got_len)
+ {
+@@ -803,7 +876,7 @@ check_got (int * got_type, int * got_len)
+ extern bfd_reloc_code_real_type
+ parse_cons_expression_microblaze (expressionS *exp, int size)
+ {
+-  if (size == 4)
++  if (size == 4 || (microblaze_arch_size == 64 && size == 8))
+     {
+       /* Handle @GOTOFF et.al.  */
+       char *save, *gotfree_copy;
+@@ -835,6 +908,7 @@ parse_cons_expression_microblaze (expressionS *exp, int size)
+ 
+ static const char * str_microblaze_ro_anchor = "RO";
+ static const char * str_microblaze_rw_anchor = "RW";
++static const char * str_microblaze_64 = "64";
+ 
+ static bool
+ check_spl_reg (unsigned * reg)
+@@ -893,9 +967,10 @@ md_assemble (char * str)
+   unsigned reg2;
+   unsigned reg3;
+   unsigned isize;
+-  unsigned int immed = 0, immed2 = 0, temp;
++  unsigned long immed = 0, immed2 = 0, temp;
+   expressionS exp;
+   char name[20];
++  long immedl;
+ 
+   /* Drop leading whitespace.  */
+   while (ISSPACE (* str))
+@@ -1014,8 +1089,9 @@ md_assemble (char * str)
+            as_fatal (_("lmi pseudo instruction should not use a label in imm field"));
+          else if (streq (name, "smi"))
+            as_fatal (_("smi pseudo instruction should not use a label in imm field"));
+-
+-         if (reg2 == REG_ROSDP)
++          if(streq (name, "lli") || streq (name, "sli"))
++            opc = str_microblaze_64;
++         else if (reg2 == REG_ROSDP)
+            opc = str_microblaze_ro_anchor;
+          else if (reg2 == REG_RWSDP)
+            opc = str_microblaze_rw_anchor;
+@@ -1082,36 +1158,60 @@ md_assemble (char * str)
+               inst |= (immed << IMM_LOW) & IMM_MASK;
+             }
+        }
+-      else
+-       {
+-          temp = immed & 0xFFFF8000;
+-          if ((temp != 0) && (temp != 0xFFFF8000))
+-           {
++      else if (streq (name, "lli") || streq (name, "sli"))
++        {
++          temp = immed & 0xFFFFFF8000;
++          if (temp != 0 && temp != 0xFFFFFF8000)
++            {
+               /* Needs an immediate inst.  */
+              opcode1
+                = (struct op_code_struct *) str_hash_find (opcode_hash_control,
+-                                                          "imm");
++                                                          "imml");
+               if (opcode1 == NULL)
+                 {
+-                  as_bad (_("unknown opcode \"%s\""), "imm");
++                  as_bad (_("unknown opcode \"%s\""), "imml");
+                   return;
+                 }
+-
+               inst1 = opcode1->bit_sequence;
+-              inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
++             inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
+               output[0] = INST_BYTE0 (inst1);
+               output[1] = INST_BYTE1 (inst1);
+               output[2] = INST_BYTE2 (inst1);
+               output[3] = INST_BYTE3 (inst1);
+               output = frag_more (isize);
+-           }
+-         inst |= (reg1 << RD_LOW) & RD_MASK;
+-         inst |= (reg2 << RA_LOW) & RA_MASK;
+-         inst |= (immed << IMM_LOW) & IMM_MASK;
+-       }
++            }
++          inst |= (reg1 << RD_LOW) & RD_MASK;
++          inst |= (reg2 << RA_LOW) & RA_MASK;
++          inst |= (immed << IMM_LOW) & IMM_MASK;
++         }
++       else 
++        {
++           temp = immed & 0xFFFF8000;
++           if ((temp != 0) && (temp != 0xFFFF8000))
++            {
++               /* Needs an immediate inst.  */
++               opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imm");
++               if (opcode1 == NULL)
++                 {
++                   as_bad (_("unknown opcode \"%s\""), "imm");
++                   return;
++                 }
++
++               inst1 = opcode1->bit_sequence;
++               inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
++               output[0] = INST_BYTE0 (inst1);
++               output[1] = INST_BYTE1 (inst1);
++               output[2] = INST_BYTE2 (inst1);
++               output[3] = INST_BYTE3 (inst1);
++               output = frag_more (isize);
++            }
++          inst |= (reg1 << RD_LOW) & RD_MASK;
++          inst |= (reg2 << RA_LOW) & RA_MASK;
++          inst |= (immed << IMM_LOW) & IMM_MASK;
++        }
+       break;
+ 
+-    case INST_TYPE_RD_R1_IMM5:
++    case INST_TYPE_RD_R1_IMMS:
+       if (strcmp (op_end, ""))
+         op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
+       else
+@@ -1145,16 +1245,22 @@ md_assemble (char * str)
+           immed = exp.X_add_number;
+         }
+ 
+-      if (immed != (immed % 32))
++      if ((immed != (immed % 32)) &&
++          (opcode->instr == bslli || opcode->instr == bsrai || opcode->instr == bsrli))
+        {
+           as_warn (_("Shift value > 32. using <value %% 32>"));
+           immed = immed % 32;
+         }
++      else if (immed != (immed % 64))
++       {
++          as_warn (_("Shift value > 64. using <value %% 64>"));
++          immed = immed % 64;
++        }
+       inst |= (reg1 << RD_LOW) & RD_MASK;
+       inst |= (reg2 << RA_LOW) & RA_MASK;
+-      inst |= (immed << IMM_LOW) & IMM5_MASK;
++      inst |= (immed << IMM_LOW) & IMM6_MASK;
+       break;
+- case INST_TYPE_RD_R1_IMM5_IMM5:
++ case INST_TYPE_RD_R1_IMMW_IMMS:
+       if (strcmp (op_end, ""))
+         op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
+       else
+@@ -1178,7 +1284,7 @@ md_assemble (char * str)
+ 
+       /* Width immediate value.  */
+       if (strcmp (op_end, ""))
+-        op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
++        op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
+       else
+         as_fatal (_("Error in statement syntax"));
+       if (exp.X_op != O_constant)
+@@ -1190,6 +1296,8 @@ md_assemble (char * str)
+         immed = exp.X_add_number;
+       if (opcode->instr == bsefi && immed > 31)
+         as_fatal (_("Width value must be less than 32"));
++      else if (opcode->instr == bslefi && immed > 63)
++        as_fatal (_("Width value must be less than 64"));
+ 
+       /* Shift immediate value.  */
+       if (strcmp (op_end, ""))
+@@ -1206,23 +1314,31 @@ md_assemble (char * str)
+           output = frag_more (isize);
+           immed2 = exp.X_add_number;
+            }
+-      if (immed2 != (immed2 % 32))
+-           {
+-          as_warn (_("Shift value greater than 32. using <value %% 32>"));
++      if ((immed2 != (immed2 % 32)) && (opcode->instr == bsefi || opcode->instr == bsifi))
++       {
++          
++         as_warn (_("Shift value greater than 32. using <value %% 32>"));
+           immed2 = immed2 % 32;
+         }
++      else if (immed2 != (immed2 % 64))
++       {
++          as_warn (_("Shift value greater than 64. using <value %% 64>"));
++          immed2 = immed2 % 64;
++        }
+ 
+       /* Check combined value.  */
+-      if (immed + immed2 > 32)
++      if ((immed + immed2 > 32) && (opcode->instr == bsefi || opcode->instr == bsifi))
+         as_fatal (_("Width value + shift value must not be greater than 32"));
++      else if (immed + immed2 > 64)
++        as_fatal (_("Width value + shift value must not be greater than 64"));
+ 
+       inst |= (reg1 << RD_LOW) & RD_MASK;
+       inst |= (reg2 << RA_LOW) & RA_MASK;
+-      if (opcode->instr == bsefi)
+-        inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
++      if (opcode->instr == bsefi || opcode->instr == bslefi)
++        inst |= (immed & IMM6_MASK) << IMM_WIDTH_LOW; /* bsefi or bslefi */
+       else
+-        inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */
+-      inst |= (immed2 << IMM_LOW) & IMM5_MASK;
++        inst |= ((immed + immed2 - 1) & IMM6_MASK) << IMM_WIDTH_LOW; /* bsifi or bslifi */
++      inst |= (immed2 << IMM_LOW) & IMM6_MASK;
+       break;
+     case INST_TYPE_R1_R2:
+       if (strcmp (op_end, ""))
+@@ -1722,12 +1838,20 @@ md_assemble (char * str)
+     case INST_TYPE_IMM:
+       if (streq (name, "imm"))
+         as_fatal (_("An IMM instruction should not be present in the .s file"));
+-
+-      op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM);
++      if (microblaze_arch_size == 64)
++        op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++      else
++        op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM);
+ 
+       if (exp.X_op != O_constant)
+        {
+-          char *opc = NULL;
++         char *opc;
++          if (microblaze_arch_size == 64 && (streq (name, "breai") || 
++                streq (name, "breaid") || 
++                streq (name, "brai") || streq (name, "braid")))
++            opc = str_microblaze_64;
++         else
++            opc = NULL;
+           relax_substateT subtype;
+ 
+          if (exp.X_md != 0)
+@@ -1750,29 +1874,53 @@ md_assemble (char * str)
+           immed = exp.X_add_number;
+         }
+ 
+-
+-      temp = immed & 0xFFFF8000;
+-      if ((temp != 0) && (temp != 0xFFFF8000))
+-       {
+-          /* Needs an immediate inst.  */
+-          opcode1
+-           = (struct op_code_struct *) str_hash_find (opcode_hash_control,
+-                                                      "imm");
+-          if (opcode1 == NULL)
+-            {
+-              as_bad (_("unknown opcode \"%s\""), "imm");
+-              return;
++      if (microblaze_arch_size == 64 && (streq (name, "breai") || 
++            streq (name, "breaid") || 
++           streq (name, "brai") || streq (name, "braid")))
++        {
++          temp = immed & 0xFFFFFF8000;
++          if (temp != 0)
++           {
++              /* Needs an immediate inst.  */
++              opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++              if (opcode1 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imml");
++                  return;
++                }
++              inst1 = opcode1->bit_sequence;
++              inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
+             }
++          inst |= (immed << IMM_LOW) & IMM_MASK;
++       }
++      else
++       {
++          temp = immed & 0xFFFF8000;
++          if ((temp != 0) && (temp != 0xFFFF8000))
++           {
++              /* Needs an immediate inst.  */
++              opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imm");
++              if (opcode1 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imm");
++                  return;
++                }
+ 
+-          inst1 = opcode1->bit_sequence;
+-          inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
+-          output[0] = INST_BYTE0 (inst1);
+-          output[1] = INST_BYTE1 (inst1);
+-          output[2] = INST_BYTE2 (inst1);
+-          output[3] = INST_BYTE3 (inst1);
+-          output = frag_more (isize);
+-        }
+-      inst |= (immed << IMM_LOW) & IMM_MASK;
++              inst1 = opcode1->bit_sequence;
++              inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++            }
++          inst |= (immed << IMM_LOW) & IMM_MASK;
++       }
+       break;
+ 
+     case INST_TYPE_NONE:
+@@ -1903,6 +2051,7 @@ struct option md_longopts[] =
+   {"EL", no_argument, NULL, OPTION_EL},
+   {"mlittle-endian", no_argument, NULL, OPTION_EL},
+   {"mbig-endian", no_argument, NULL, OPTION_EB},
++  {"m64", no_argument, NULL, OPTION_M64},
+   { NULL,          no_argument, NULL, 0}
+ };
+ 
+@@ -1947,13 +2096,23 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
+       fragP->fr_fix += INST_WORD_SIZE * 2;
+       fragP->fr_var = 0;
+       break;
++    case DEFINED_64_OFFSET:
++      if (fragP->fr_symbol == GOT_symbol)
++        fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
++                fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64_GPC);
++      else
++        fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
++                fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64);
++      fragP->fr_fix += INST_WORD_SIZE * 2;
++      fragP->fr_var = 0;
++      break;
+     case DEFINED_ABS_SEGMENT:
+       if (fragP->fr_symbol == GOT_symbol)
+         fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
+                 fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64_GOTPC);
+       else
+         fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
+-                fragP->fr_offset, false, BFD_RELOC_64);
++                fragP->fr_offset, true, BFD_RELOC_64);
+       fragP->fr_fix += INST_WORD_SIZE * 2;
+       fragP->fr_var = 0;
+       break;
+@@ -2174,23 +2333,38 @@ md_apply_fix (fixS *   fixP,
+     case BFD_RELOC_64_PCREL:
+     case BFD_RELOC_64:
+     case BFD_RELOC_MICROBLAZE_64_TEXTREL:
++    case BFD_RELOC_MICROBLAZE_64:
+       /* Add an imm instruction.  First save the current instruction.  */
+       for (i = 0; i < INST_WORD_SIZE; i++)
+        buf[i + INST_WORD_SIZE] = buf[i];
++      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
++        {
++          /* Generate the imm instruction.  */
++          opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++          if (opcode1 == NULL)
++           {
++             as_bad (_("unknown opcode \"%s\""), "imml");
++             return;
++           }
+ 
+-      /* Generate the imm instruction.  */
+-      opcode1
+-       = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imm");
+-      if (opcode1 == NULL)
+-       {
+-         as_bad (_("unknown opcode \"%s\""), "imm");
+-         return;
+-       }
+-
+-      inst1 = opcode1->bit_sequence;
+-      if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+-       inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK;
+-
++           inst1 = opcode1->bit_sequence;
++           if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
++            inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++         }
++      else
++        {
++          /* Generate the imm instruction.  */
++          opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imm");
++          if (opcode1 == NULL)
++           {
++             as_bad (_("unknown opcode \"%s\""), "imm");
++             return;
++           }
++     
++          inst1 = opcode1->bit_sequence;
++          if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
++           inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK;
++         }
+       buf[0] = INST_BYTE0 (inst1);
+       buf[1] = INST_BYTE1 (inst1);
+       buf[2] = INST_BYTE2 (inst1);
+@@ -2219,6 +2393,7 @@ md_apply_fix (fixS *   fixP,
+       /* Fall through.  */
+ 
+     case BFD_RELOC_MICROBLAZE_64_GOTPC:
++    case BFD_RELOC_MICROBLAZE_64_GPC:
+     case BFD_RELOC_MICROBLAZE_64_GOT:
+     case BFD_RELOC_MICROBLAZE_64_PLT:
+     case BFD_RELOC_MICROBLAZE_64_GOTOFF:
+@@ -2226,13 +2401,17 @@ md_apply_fix (fixS *   fixP,
+       /* Add an imm instruction.  First save the current instruction.  */
+       for (i = 0; i < INST_WORD_SIZE; i++)
+        buf[i + INST_WORD_SIZE] = buf[i];
+-
+       /* Generate the imm instruction.  */
+-      opcode1
+-       = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imm");
++      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
++        opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++      else
++        opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imm");
+       if (opcode1 == NULL)
+        {
+-         as_bad (_("unknown opcode \"%s\""), "imm");
++         if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
++           as_bad (_("unknown opcode \"%s\""), "imml");
++          else
++           as_bad (_("unknown opcode \"%s\""), "imm");
+          return;
+        }
+ 
+@@ -2256,6 +2435,8 @@ md_apply_fix (fixS *   fixP,
+         moves code around due to relaxing.  */
+       if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
+        fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
++      else if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
++       fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
+       else if (fixP->fx_r_type == BFD_RELOC_32)
+        fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
+       else
+@@ -2298,6 +2479,32 @@ md_estimate_size_before_relax (fragS * fragP,
+           as_bad (_("Absolute PC-relative value in relaxation code.  Assembler error....."));
+           abort ();
+         }
++      else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type
++               && !S_IS_WEAK (fragP->fr_symbol))
++        {
++           if (fragP->fr_opcode != NULL) {
++            if(streq (fragP->fr_opcode, str_microblaze_64)) 
++             {
++               /* Used as an absolute value.  */
++              fragP->fr_subtype = DEFINED_64_OFFSET;
++               /* Variable part does not change.  */
++              fragP->fr_var = INST_WORD_SIZE;
++            }
++          else
++            {
++               fragP->fr_subtype = DEFINED_PC_OFFSET;
++              /* Don't know now whether we need an imm instruction.  */
++               fragP->fr_var = INST_WORD_SIZE;
++            }
++          }  
++          else
++            {
++               fragP->fr_subtype = DEFINED_PC_OFFSET;
++              /* Don't know now whether we need an imm instruction.  */
++               fragP->fr_var = INST_WORD_SIZE;
++            }
++        }
++#if 0
+       else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type &&
+                !S_IS_WEAK (fragP->fr_symbol))
+         {
+@@ -2305,6 +2512,7 @@ md_estimate_size_before_relax (fragS * fragP,
+           /* Don't know now whether we need an imm instruction.  */
+           fragP->fr_var = INST_WORD_SIZE;
+         }
++#endif
+       else if (S_IS_DEFINED (fragP->fr_symbol)
+               && (((S_GET_SEGMENT (fragP->fr_symbol))->flags & SEC_CODE) == 0))
+         {
+@@ -2316,7 +2524,14 @@ md_estimate_size_before_relax (fragS * fragP,
+         }
+       else
+        {
+-         fragP->fr_subtype = UNDEFINED_PC_OFFSET;
++         if (fragP->fr_opcode != NULL) {
++           if (streq (fragP->fr_opcode, str_microblaze_64)) 
++              fragP->fr_subtype = DEFINED_64_PC_OFFSET;
++           else
++             fragP->fr_subtype = UNDEFINED_PC_OFFSET;
++           }
++         else
++           fragP->fr_subtype = UNDEFINED_PC_OFFSET;
+          fragP->fr_var = INST_WORD_SIZE*2;
+        }
+       break;
+@@ -2395,6 +2610,33 @@ md_estimate_size_before_relax (fragS * fragP,
+               abort ();
+             }
+        }
++#if 0 //revisit
++      else if (streq (name, "lli") || streq (name, "sli"))
++       {
++          temp = immed & 0xFFFFFFFFFFFF8000;
++          if ((temp != 0) && (temp != 0xFFFFFFFFFFFF8000))
++           {
++              /* Needs an immediate inst.  */
++              opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++              if (opcode1 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imml");
++                  return;
++                }
++
++              inst1 = opcode1->bit_sequence;
++             inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++           }
++         inst |= (reg1 << RD_LOW) & RD_MASK;
++         inst |= (reg2 << RA_LOW) & RA_MASK;
++         inst |= (immed << IMM_LOW) & IMM_MASK;
++        }
++#endif
+       else
+        {
+          /* We know the abs value: Should never happen.  */
+@@ -2414,6 +2656,7 @@ md_estimate_size_before_relax (fragS * fragP,
+     case TLSLD_OFFSET:
+     case TLSTPREL_OFFSET:
+     case TLSDTPREL_OFFSET:
++    case DEFINED_64_OFFSET:
+       fragP->fr_var = INST_WORD_SIZE*2;
+       break;
+     case DEFINED_RO_SEGMENT:
+@@ -2467,7 +2710,7 @@ md_pcrel_from_section (fixS * fixp, segT sec ATTRIBUTE_UNUSED)
+   else
+     {
+       /* The case where we are going to resolve things... */
+-      if (fixp->fx_r_type == BFD_RELOC_64_PCREL)
++      if (fixp->fx_r_type == BFD_RELOC_64_PCREL ||fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64)
+         return  fixp->fx_where + fixp->fx_frag->fr_address + INST_WORD_SIZE;
+       else
+         return  fixp->fx_where + fixp->fx_frag->fr_address;
+@@ -2500,6 +2743,8 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+     case BFD_RELOC_MICROBLAZE_32_RWSDA:
+     case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM:
+     case BFD_RELOC_MICROBLAZE_64_GOTPC:
++    case BFD_RELOC_MICROBLAZE_64_GPC:
++    case BFD_RELOC_MICROBLAZE_64:
+     case BFD_RELOC_MICROBLAZE_64_GOT:
+     case BFD_RELOC_MICROBLAZE_64_PLT:
+     case BFD_RELOC_MICROBLAZE_64_GOTOFF:
+@@ -2515,6 +2760,143 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+     case BFD_RELOC_MICROBLAZE_64_TEXTREL:
+       code = fixp->fx_r_type;
+       break;
++    /* For 64-bit instructions */
++    case INST_TYPE_RD_R1_IMML:
++      if (strcmp (op_end, ""))
++       op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
++      else
++       {
++          as_fatal (_("Error in statement syntax"));
++          reg1 = 0;
++        }
++      if (strcmp (op_end, ""))
++       op_end = parse_reg (op_end + 1, &reg2);  /* Get r1.  */
++      else
++       {
++          as_fatal (_("Error in statement syntax"));
++          reg2 = 0;
++        }
++      if (strcmp (op_end, ""))
++       op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++      else
++       as_fatal (_("Error in statement syntax"));
++
++      /* Check for spl registers.  */
++      if (check_spl_reg (& reg1))
++       as_fatal (_("Cannot use special register with this instruction"));
++      if (check_spl_reg (& reg2))
++       as_fatal (_("Cannot use special register with this instruction"));
++
++      if (exp.X_op != O_constant)
++       {
++         char *opc = NULL;
++         //char *opc = str_microblaze_64;
++         relax_substateT subtype;
++
++         if (exp.X_md != 0)
++           subtype = get_imm_otype(exp.X_md);
++         else
++           subtype = opcode->inst_offset_type;
++
++         output = frag_var (rs_machine_dependent,
++                            isize * 2, /* maxm of 2 words.  */
++                            isize * 2, /* minm of 2 words.  */
++                            subtype,   /* PC-relative or not.  */
++                            exp.X_add_symbol,
++                            exp.X_add_number,
++                            (char *) opc);
++         immedl = 0L;
++        }
++      else
++       {
++         output = frag_more (isize);
++         immedl = exp.X_add_number;
++
++         opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++         if (opcode1 == NULL)
++           {
++             as_bad (_("unknown opcode \"%s\""), "imml");
++             return;
++           }
++
++         inst1 = opcode1->bit_sequence;
++         inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++         output[0] = INST_BYTE0 (inst1);
++         output[1] = INST_BYTE1 (inst1);
++         output[2] = INST_BYTE2 (inst1);
++         output[3] = INST_BYTE3 (inst1);
++         output = frag_more (isize);
++        }
++
++      inst |= (reg1 << RD_LOW) & RD_MASK;
++      inst |= (reg2 << RA_LOW) & RA_MASK;
++      inst |= (immedl << IMM_LOW) & IMM_MASK;
++      break;
++
++    case INST_TYPE_R1_IMML:
++      if (strcmp (op_end, ""))
++        op_end = parse_reg (op_end + 1, &reg1);  /* Get r1.  */
++      else
++       {
++          as_fatal (_("Error in statement syntax"));
++          reg1 = 0;
++        }
++      if (strcmp (op_end, ""))
++        op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++      else
++        as_fatal (_("Error in statement syntax"));
++
++      /* Check for spl registers.  */
++      if (check_spl_reg (&reg1))
++        as_fatal (_("Cannot use special register with this instruction"));
++
++      if (exp.X_op != O_constant)
++       {
++         //char *opc = NULL;
++          char *opc = str_microblaze_64;
++          relax_substateT subtype;
++
++         if (exp.X_md != 0)
++           subtype = get_imm_otype(exp.X_md);
++         else
++           subtype = opcode->inst_offset_type;
++
++         output = frag_var (rs_machine_dependent,
++                            isize * 2, /* maxm of 2 words.  */
++                            isize * 2, /* minm of 2 words.  */
++                            subtype,   /* PC-relative or not.  */
++                            exp.X_add_symbol,
++                            exp.X_add_number,
++                            (char *) opc);
++         immedl = 0L;
++       }
++      else
++       {
++          output = frag_more (isize);
++          immedl = exp.X_add_number;
++         opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++         if (opcode1 == NULL)
++           {
++             as_bad (_("unknown opcode \"%s\""), "imml");
++             return;
++           }
++
++          inst1 = opcode1->bit_sequence;
++         inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++        }
++
++      inst |= (reg1 << RA_LOW) & RA_MASK;
++      inst |= (immedl << IMM_LOW) & IMM_MASK;
++      break;
++
++    case INST_TYPE_IMML:
++      as_fatal (_("An IMML instruction should not be present in the .s file"));
++      break;
+ 
+     default:
+       switch (F (fixp->fx_size, fixp->fx_pcrel))
+@@ -2560,6 +2942,18 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+   return rel;
+ }
+ 
++/* Called by TARGET_FORMAT.  */
++const char *
++microblaze_target_format (void)
++{
++
++  if (microblaze_arch_size == 64)
++    return "elf64-microblazeel";
++  else 
++      return target_big_endian ? "elf32-microblaze" : "elf32-microblazeel";
++}
++
++
+ int
+ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+ {
+@@ -2573,6 +2967,10 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+     case OPTION_LITTLE:
+       target_big_endian = 0;
+       break;
++    case OPTION_M64:
++      //if (arg != NULL && strcmp (arg, "64") == 0)
++      microblaze_arch_size = 64;
++      break;
+     default:
+       return 0;
+     }
+@@ -2588,6 +2986,7 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
+   fprintf (stream, _(" MicroBlaze specific assembler options:\n"));
+   fprintf (stream, "  -%-23s%s\n", "mbig-endian", N_("assemble for a big endian cpu"));
+   fprintf (stream, "  -%-23s%s\n", "mlittle-endian", N_("assemble for a little endian cpu"));      
++  fprintf (stream, "  -%-23s%s\n", "m64", N_("generate 64-bit elf"));
+ }
+ 
+ 
+@@ -2625,7 +3024,10 @@ cons_fix_new_microblaze (fragS * frag,
+           r = BFD_RELOC_32;
+           break;
+         case 8:
+-          r = BFD_RELOC_64;
++          if (microblaze_arch_size == 64)
++            r = BFD_RELOC_32;
++          else
++            r = BFD_RELOC_64;
+           break;
+         default:
+           as_bad (_("unsupported BFD relocation size %u"), size);
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0023-Added-relocations-for-MB-X.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0023-Added-relocations-for-MB-X.patch
new file mode 100644
index 00000000..f92dd068
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0023-Added-relocations-for-MB-X.patch
@@ -0,0 +1,246 @@
+From fb4a4d6855092f5b0b201e40234782822cd63a66 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 11 Sep 2018 17:30:17 +0530
+Subject: [PATCH 23/53] Added relocations for MB-X
+
+Conflicts:
+        bfd/bfd-in2.h
+        gas/config/tc-microblaze.c
+
+Conflicts:
+        gas/config/tc-microblaze.c
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/libbfd.h               |  2 --
+ bfd/reloc.c                | 26 ++++++++-------
+ gas/config/tc-microblaze.c | 68 ++++++++++++--------------------------
+ 3 files changed, 36 insertions(+), 60 deletions(-)
+
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index 603ed8260cb..7a3e558d70a 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -3005,9 +3005,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
+   "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
+-  "BFD_RELOC_MICROBLAZE_64",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
+-  "BFD_RELOC_MICROBLAZE_64_GPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+   "BFD_RELOC_MICROBLAZE_64_PLT",
+   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index 6eb93e993f0..b6c9c22a0be 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6634,6 +6634,20 @@ ENUM
+ ENUMDOC
+   Address of a GOT entry.
+ 
++  This is a 64 bit reloc that stores 64-bit thread pointer relative offset
++  to two words (uses imml instruction).
++ENUM
++BFD_RELOC_MICROBLAZE_64,
++ENUMDOC
++ This is a 64 bit reloc that stores the 64 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
++ENUM
++BFD_RELOC_MICROBLAZE_64_PCREL,
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
+ ENUM
+   BFD_RELOC_MICROBLAZE_32_LO
+ ENUMDOC
+@@ -6671,12 +6685,6 @@ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative value in
+   two words (with an imm instruction).  No relocation is done here -
+   only used for relaxing.
+-ENUM
+-  BFD_RELOC_MICROBLAZE_64
+-ENUMDOC
+-  This is a 64 bit reloc that stores the 32 bit pc relative
+-  value in two words (with an imm instruction).  No relocation is
+-  done here - only used for relaxing
+ ENUM
+ BFD_RELOC_MICROBLAZE_64_PCREL,
+ ENUMDOC
+@@ -6689,12 +6697,6 @@ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imml instruction).  No relocation is
+   done here - only used for relaxing
+-ENUM
+-  BFD_RELOC_MICROBLAZE_64_GPC
+-ENUMDOC
+-  This is a 64 bit reloc that stores the 32 bit pc relative
+-  value in two words (with an imm instruction).  The relocation is
+-  PC-relative GOT offset
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_GOT
+ ENUMDOC
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 6640266cc47..29fb6360169 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -2096,23 +2096,29 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
+       fragP->fr_fix += INST_WORD_SIZE * 2;
+       fragP->fr_var = 0;
+       break;
++    case DEFINED_64_PC_OFFSET:
++      fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
++                fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_PCREL);
++      fragP->fr_fix += INST_WORD_SIZE * 2;
++      fragP->fr_var = 0;
++      break;
+     case DEFINED_64_OFFSET:
+       if (fragP->fr_symbol == GOT_symbol)
+         fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
+-                fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64_GPC);
++                fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64_GPC);
+       else
+         fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
+-                fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64);
++                fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64);
+       fragP->fr_fix += INST_WORD_SIZE * 2;
+       fragP->fr_var = 0;
+       break;
+     case DEFINED_ABS_SEGMENT:
+       if (fragP->fr_symbol == GOT_symbol)
+         fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
+-                fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64_GOTPC);
++                fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64_GOTPC);
+       else
+         fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
+-                fragP->fr_offset, true, BFD_RELOC_64);
++                fragP->fr_offset, false, BFD_RELOC_64);
+       fragP->fr_fix += INST_WORD_SIZE * 2;
+       fragP->fr_var = 0;
+       break;
+@@ -2334,10 +2340,12 @@ md_apply_fix (fixS *   fixP,
+     case BFD_RELOC_64:
+     case BFD_RELOC_MICROBLAZE_64_TEXTREL:
+     case BFD_RELOC_MICROBLAZE_64:
++    case BFD_RELOC_MICROBLAZE_64_PCREL:
+       /* Add an imm instruction.  First save the current instruction.  */
+       for (i = 0; i < INST_WORD_SIZE; i++)
+        buf[i + INST_WORD_SIZE] = buf[i];
+-      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
++      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64
++            || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
+         {
+           /* Generate the imm instruction.  */
+           opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
+@@ -2350,6 +2358,10 @@ md_apply_fix (fixS *   fixP,
+            inst1 = opcode1->bit_sequence;
+            if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+             inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
++             fixP->fx_r_type = BFD_RELOC_64; 
++           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
++             fixP->fx_r_type = BFD_RELOC_64_PCREL; 
+          }
+       else
+         {
+@@ -2435,8 +2447,6 @@ md_apply_fix (fixS *   fixP,
+         moves code around due to relaxing.  */
+       if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
+        fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
+-      else if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
+-       fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
+       else if (fixP->fx_r_type == BFD_RELOC_32)
+        fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
+       else
+@@ -2486,9 +2496,9 @@ md_estimate_size_before_relax (fragS * fragP,
+             if(streq (fragP->fr_opcode, str_microblaze_64)) 
+              {
+                /* Used as an absolute value.  */
+-              fragP->fr_subtype = DEFINED_64_OFFSET;
++              fragP->fr_subtype = DEFINED_64_PC_OFFSET;
+                /* Variable part does not change.  */
+-              fragP->fr_var = INST_WORD_SIZE;
++              fragP->fr_var = INST_WORD_SIZE*2;
+             }
+           else
+             {
+@@ -2504,15 +2514,6 @@ md_estimate_size_before_relax (fragS * fragP,
+                fragP->fr_var = INST_WORD_SIZE;
+             }
+         }
+-#if 0
+-      else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type &&
+-               !S_IS_WEAK (fragP->fr_symbol))
+-        {
+-          fragP->fr_subtype = DEFINED_PC_OFFSET;
+-          /* Don't know now whether we need an imm instruction.  */
+-          fragP->fr_var = INST_WORD_SIZE;
+-        }
+-#endif
+       else if (S_IS_DEFINED (fragP->fr_symbol)
+               && (((S_GET_SEGMENT (fragP->fr_symbol))->flags & SEC_CODE) == 0))
+         {
+@@ -2610,33 +2611,6 @@ md_estimate_size_before_relax (fragS * fragP,
+               abort ();
+             }
+        }
+-#if 0 //revisit
+-      else if (streq (name, "lli") || streq (name, "sli"))
+-       {
+-          temp = immed & 0xFFFFFFFFFFFF8000;
+-          if ((temp != 0) && (temp != 0xFFFFFFFFFFFF8000))
+-           {
+-              /* Needs an immediate inst.  */
+-              opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
+-              if (opcode1 == NULL)
+-                {
+-                  as_bad (_("unknown opcode \"%s\""), "imml");
+-                  return;
+-                }
+-
+-              inst1 = opcode1->bit_sequence;
+-             inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
+-              output[0] = INST_BYTE0 (inst1);
+-              output[1] = INST_BYTE1 (inst1);
+-              output[2] = INST_BYTE2 (inst1);
+-              output[3] = INST_BYTE3 (inst1);
+-              output = frag_more (isize);
+-           }
+-         inst |= (reg1 << RD_LOW) & RD_MASK;
+-         inst |= (reg2 << RA_LOW) & RA_MASK;
+-         inst |= (immed << IMM_LOW) & IMM_MASK;
+-        }
+-#endif
+       else
+        {
+          /* We know the abs value: Should never happen.  */
+@@ -2657,6 +2631,7 @@ md_estimate_size_before_relax (fragS * fragP,
+     case TLSTPREL_OFFSET:
+     case TLSDTPREL_OFFSET:
+     case DEFINED_64_OFFSET:
++    case DEFINED_64_PC_OFFSET:
+       fragP->fr_var = INST_WORD_SIZE*2;
+       break;
+     case DEFINED_RO_SEGMENT:
+@@ -2710,7 +2685,7 @@ md_pcrel_from_section (fixS * fixp, segT sec ATTRIBUTE_UNUSED)
+   else
+     {
+       /* The case where we are going to resolve things... */
+-      if (fixp->fx_r_type == BFD_RELOC_64_PCREL ||fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64)
++      if (fixp->fx_r_type == BFD_RELOC_64_PCREL ||fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
+         return  fixp->fx_where + fixp->fx_frag->fr_address + INST_WORD_SIZE;
+       else
+         return  fixp->fx_where + fixp->fx_frag->fr_address;
+@@ -2745,6 +2720,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+     case BFD_RELOC_MICROBLAZE_64_GOTPC:
+     case BFD_RELOC_MICROBLAZE_64_GPC:
+     case BFD_RELOC_MICROBLAZE_64:
++    case BFD_RELOC_MICROBLAZE_64_PCREL:
+     case BFD_RELOC_MICROBLAZE_64_GOT:
+     case BFD_RELOC_MICROBLAZE_64_PLT:
+     case BFD_RELOC_MICROBLAZE_64_GOTOFF:
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0024-Fixed-MB-x-relocation-issues-Added-imml-for-required.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0024-Fixed-MB-x-relocation-issues-Added-imml-for-required.patch
new file mode 100644
index 00000000..18698b02
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0024-Fixed-MB-x-relocation-issues-Added-imml-for-required.patch
@@ -0,0 +1,52 @@
+From 88f7a313f8e21021dacfc8da2c490a433f596fd8 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Fri, 28 Sep 2018 12:04:55 +0530
+Subject: [PATCH 24/53] -Fixed MB-x relocation issues -Added imml for required
+ MB-x instructions
+
+Conflicts:
+        bfd/elf64-microblaze.c
+        gas/config/tc-microblaze.c
+
+Conflicts:
+        gas/config/tc-microblaze.c
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 29fb6360169..e43ea82a2cc 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -363,7 +363,7 @@ microblaze_s_weakext (int ignore ATTRIBUTE_UNUSED)
+    Integer arg to pass to the function.  */
+ /* If the pseudo-op is not found in this table, it searches in the obj-elf.c,
+    and then in the read.c table.  */
+-pseudo_typeS md_pseudo_table[] =
++const pseudo_typeS md_pseudo_table[] =
+ {
+   {"lcomm", microblaze_s_lcomm, 1},
+   {"data8", cons, 1},      /* Same as byte.  */
+@@ -2357,7 +2357,7 @@ md_apply_fix (fixS *   fixP,
+ 
+            inst1 = opcode1->bit_sequence;
+            if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+-            inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++            inst1 |= ((val & 0xFFFFFF0000L) >> 16) & IMML_MASK;
+            if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
+              fixP->fx_r_type = BFD_RELOC_64; 
+            if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
+@@ -2946,6 +2946,8 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+     case OPTION_M64:
+       //if (arg != NULL && strcmp (arg, "64") == 0)
+       microblaze_arch_size = 64;
++      // UPSTREAM/REVISIT - md_pseudo_table is const
++      // md_pseudo_table[7].poc_val = 8;
+       break;
+     default:
+       return 0;
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0025-Fixed-address-computation-issues-with-64bit-address-.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0025-Fixed-address-computation-issues-with-64bit-address-.patch
new file mode 100644
index 00000000..d480388c
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0025-Fixed-address-computation-issues-with-64bit-address-.patch
@@ -0,0 +1,160 @@
+From 585f95d1510385ed3f67e76e2ad8f9a27b3ee32a Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 9 Oct 2018 10:14:22 +0530
+Subject: [PATCH 25/53] - Fixed address computation issues with 64bit address -
+ Fixed imml dissassamble issue
+
+Conflicts:
+        gas/config/tc-microblaze.c
+        opcodes/microblaze-dis.c
+
+Conflicts:
+        bfd/elf64-microblaze.c
+
+Conflicts:
+        bfd/elf64-microblaze.c
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elf64-microblaze.c     |  2 +-
+ gas/config/tc-microblaze.c | 74 +++++++++++++++++++++++++++++++++-----
+ 2 files changed, 67 insertions(+), 9 deletions(-)
+
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index ca92df647c9..9f542f55ebd 100755
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -2131,7 +2131,7 @@ microblaze_elf_relax_section (bfd *abfd,
+                efix = calc_fixup (target_address, 0, sec);
+ 
+             /* Validate the in-band val.  */
+-            val = bfd_get_32 (abfd, contents + irel->r_offset);
++            val = bfd_get_64 (abfd, contents + irel->r_offset);
+             if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
+                fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
+             }
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index e43ea82a2cc..544732649a5 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -372,7 +372,6 @@ const pseudo_typeS md_pseudo_table[] =
+   {"ent", s_func, 0}, /* Treat ent as function entry point.  */
+   {"end", microblaze_s_func, 1}, /* Treat end as function end point.  */
+   {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section.  */
+-   {"gpdword", s_rva, 8}, /* gpword label => store resolved label address in data section.  */
+   {"weakext", microblaze_s_weakext, 0},
+   {"rodata", microblaze_s_rdata, 0},
+   {"sdata2", microblaze_s_rdata, 1},
+@@ -2317,18 +2316,74 @@ md_apply_fix (fixS *   fixP,
+     case BFD_RELOC_RVA:
+     case BFD_RELOC_32_PCREL:
+     case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM:
++      /* Don't do anything if the symbol is not defined.  */
++      if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
++       {
++         if ((fixP->fx_r_type == BFD_RELOC_RVA) && (microblaze_arch_size == 64))
++            {
++             if (target_big_endian)
++               {
++                 buf[0] |= ((val >> 56) & 0xff);
++                 buf[1] |= ((val >> 48) & 0xff);
++                 buf[2] |= ((val >> 40) & 0xff);
++                 buf[3] |= ((val >> 32) & 0xff);
++                 buf[4] |= ((val >> 24) & 0xff);
++                 buf[5] |= ((val >> 16) & 0xff);
++                 buf[6] |= ((val >> 8) & 0xff);
++                 buf[7] |= (val & 0xff);
++               }
++             else
++               {
++                 buf[7] |= ((val >> 56) & 0xff);
++                 buf[6] |= ((val >> 48) & 0xff);
++                 buf[5] |= ((val >> 40) & 0xff);
++                 buf[4] |= ((val >> 32) & 0xff);
++                 buf[3] |= ((val >> 24) & 0xff);
++                 buf[2] |= ((val >> 16) & 0xff);
++                 buf[1] |= ((val >> 8) & 0xff);
++                 buf[0] |= (val & 0xff);
++               }
++           }
++         else {
++           if (target_big_endian)
++             {
++               buf[0] |= ((val >> 24) & 0xff);
++               buf[1] |= ((val >> 16) & 0xff);
++               buf[2] |= ((val >> 8) & 0xff);
++               buf[3] |= (val & 0xff);
++             }
++           else
++             {
++               buf[3] |= ((val >> 24) & 0xff);
++               buf[2] |= ((val >> 16) & 0xff);
++               buf[1] |= ((val >> 8) & 0xff);
++               buf[0] |= (val & 0xff);
++             }
++         }
++       }
++      break;
++    
++    case BFD_RELOC_MICROBLAZE_EA64:
+       /* Don't do anything if the symbol is not defined.  */
+       if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+        {
+          if (target_big_endian)
+            {
+-             buf[0] |= ((val >> 24) & 0xff);
+-             buf[1] |= ((val >> 16) & 0xff);
+-             buf[2] |= ((val >> 8) & 0xff);
+-             buf[3] |= (val & 0xff);
++             buf[0] |= ((val >> 56) & 0xff);
++             buf[1] |= ((val >> 48) & 0xff);
++             buf[2] |= ((val >> 40) & 0xff);
++             buf[3] |= ((val >> 32) & 0xff);
++             buf[4] |= ((val >> 24) & 0xff);
++             buf[5] |= ((val >> 16) & 0xff);
++             buf[6] |= ((val >> 8) & 0xff);
++             buf[7] |= (val & 0xff);
+            }
+          else
+            {
++             buf[7] |= ((val >> 56) & 0xff);
++             buf[6] |= ((val >> 48) & 0xff);
++             buf[5] |= ((val >> 40) & 0xff);
++             buf[4] |= ((val >> 32) & 0xff);
+              buf[3] |= ((val >> 24) & 0xff);
+              buf[2] |= ((val >> 16) & 0xff);
+              buf[1] |= ((val >> 8) & 0xff);
+@@ -2449,6 +2504,8 @@ md_apply_fix (fixS *   fixP,
+        fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
+       else if (fixP->fx_r_type == BFD_RELOC_32)
+        fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
++      else if(fixP->fx_r_type == BFD_RELOC_MICROBLAZE_EA64)
++        fixP->fx_r_type = BFD_RELOC_MICROBLAZE_EA64;
+       else
+        fixP->fx_r_type = BFD_RELOC_NONE;
+       fixP->fx_addsy = section_symbol (absolute_section);
+@@ -2719,6 +2776,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+     case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM:
+     case BFD_RELOC_MICROBLAZE_64_GOTPC:
+     case BFD_RELOC_MICROBLAZE_64_GPC:
++    case BFD_RELOC_MICROBLAZE_EA64:
+     case BFD_RELOC_MICROBLAZE_64:
+     case BFD_RELOC_MICROBLAZE_64_PCREL:
+     case BFD_RELOC_MICROBLAZE_64_GOT:
+@@ -3002,10 +3060,10 @@ cons_fix_new_microblaze (fragS * frag,
+           r = BFD_RELOC_32;
+           break;
+         case 8:
+-          if (microblaze_arch_size == 64)
++          /*if (microblaze_arch_size == 64)
+             r = BFD_RELOC_32;
+-          else
+-            r = BFD_RELOC_64;
++          else*/
++            r = BFD_RELOC_MICROBLAZE_EA64;
+           break;
+         default:
+           as_bad (_("unsupported BFD relocation size %u"), size);
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0026-Patch-MicroBlaze-Adding-new-relocation-to-support-64.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0026-Patch-MicroBlaze-Adding-new-relocation-to-support-64.patch
new file mode 100644
index 00000000..03d8e0b8
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0026-Patch-MicroBlaze-Adding-new-relocation-to-support-64.patch
@@ -0,0 +1,110 @@
+From d3fd5a77fa218f8f6c296337758d45cab61483fe Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 2 Nov 2021 17:28:24 +0530
+Subject: [PATCH 26/53] [Patch,MicroBlaze : Adding new relocation to support
+ 64bit rodata.
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c | 49 ++++++++++++++++++++++++++++++++++----
+ 1 file changed, 45 insertions(+), 4 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 544732649a5..c9757796ae8 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -1090,6 +1090,13 @@ md_assemble (char * str)
+            as_fatal (_("smi pseudo instruction should not use a label in imm field"));
+           if(streq (name, "lli") || streq (name, "sli"))
+             opc = str_microblaze_64;
++          else if ((microblaze_arch_size == 64) && ((streq (name, "lbui")
++                       || streq (name, "lhui") || streq (name, "lwi") || streq (name, "sbi")
++                       || streq (name, "shi") || streq (name, "swi"))))
++           {
++              opc = str_microblaze_64;
++             subtype = opcode->inst_offset_type;
++           }
+          else if (reg2 == REG_ROSDP)
+            opc = str_microblaze_ro_anchor;
+          else if (reg2 == REG_RWSDP)
+@@ -1157,7 +1164,10 @@ md_assemble (char * str)
+               inst |= (immed << IMM_LOW) & IMM_MASK;
+             }
+        }
+-      else if (streq (name, "lli") || streq (name, "sli"))
++      else if (streq (name, "lli") || streq (name, "sli") || ((microblaze_arch_size == 64)
++               && ((streq (name, "lbui")) || streq (name, "lhui")
++               || streq (name, "lwi") || streq (name, "sbi")
++                || streq (name, "shi") || streq (name, "swi"))))
+         {
+           temp = immed & 0xFFFFFF8000;
+           if (temp != 0 && temp != 0xFFFFFF8000)
+@@ -1773,6 +1783,11 @@ md_assemble (char * str)
+ 
+          if (exp.X_md != 0)
+            subtype = get_imm_otype(exp.X_md);
++          else if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai"))
++            {
++              opc = str_microblaze_64;
++             subtype = opcode->inst_offset_type;
++           }
+          else
+            subtype = opcode->inst_offset_type;
+ 
+@@ -1790,6 +1805,31 @@ md_assemble (char * str)
+           output = frag_more (isize);
+           immed = exp.X_add_number;
+         }
++      if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai"))
++        {
++          temp = immed & 0xFFFFFF8000;
++          if (temp != 0 && temp != 0xFFFFFF8000)
++            {
++              /* Needs an immediate inst.  */
++              opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++              if (opcode1 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imml");
++                  return;
++                }
++              inst1 = opcode1->bit_sequence;
++             inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++            }
++         inst |= (reg1 << RD_LOW) & RD_MASK;
++          inst |= (immed << IMM_LOW) & IMM_MASK;
++         }
++       else 
++        {
+ 
+       temp = immed & 0xFFFF8000;
+       if ((temp != 0) && (temp != 0xFFFF8000))
+@@ -1815,6 +1855,7 @@ md_assemble (char * str)
+ 
+       inst |= (reg1 << RD_LOW) & RD_MASK;
+       inst |= (immed << IMM_LOW) & IMM_MASK;
++        }
+       break;
+ 
+     case INST_TYPE_R2:
+@@ -3060,10 +3101,10 @@ cons_fix_new_microblaze (fragS * frag,
+           r = BFD_RELOC_32;
+           break;
+         case 8:
+-          /*if (microblaze_arch_size == 64)
+-            r = BFD_RELOC_32;
+-          else*/
++          if (microblaze_arch_size == 64)
+             r = BFD_RELOC_MICROBLAZE_EA64;
++          else
++            r = BFD_RELOC_64;
+           break;
+         default:
+           as_bad (_("unsupported BFD relocation size %u"), size);
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0027-Revert-ld-Remove-unused-expression-state-defsym-symb.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0027-Revert-ld-Remove-unused-expression-state-defsym-symb.patch
new file mode 100644
index 00000000..5a8992df
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0027-Revert-ld-Remove-unused-expression-state-defsym-symb.patch
@@ -0,0 +1,84 @@
+From e89c2729322ce147e8a5a5e7842944593b4dd474 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 27 Feb 2019 15:12:32 +0530
+Subject: [PATCH 27/53] Revert "ld: Remove unused expression state" --defsym
+ symbol=expression Create a global symbol in the output file, containing the
+ absolute address given by expression.
+
+This reverts commit 65f14869fd3fbee8ed4c4ca49de8aaa86dbc66cb.
+
+Conflicts:
+        ld/ChangeLog
+
+Conflicts:
+        ld/ldexp.c
+        ld/ldexp.h
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ ld/ldexp.c | 8 +++++---
+ ld/ldexp.h | 1 +
+ 2 files changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/ld/ldexp.c b/ld/ldexp.c
+index 3c8ab2d3589..525f3e4262c 100644
+--- a/ld/ldexp.c
++++ b/ld/ldexp.c
+@@ -1402,6 +1402,7 @@ static etree_type *
+ exp_assop (const char *dst,
+           etree_type *src,
+           enum node_tree_enum class,
++          bool defsym,
+           bool hidden)
+ {
+   etree_type *n;
+@@ -1413,6 +1414,7 @@ exp_assop (const char *dst,
+   n->assign.type.node_class = class;
+   n->assign.src = src;
+   n->assign.dst = dst;
++  n->assign.defsym = defsym;
+   n->assign.hidden = hidden;
+   return n;
+ }
+@@ -1422,7 +1424,7 @@ exp_assop (const char *dst,
+ etree_type *
+ exp_assign (const char *dst, etree_type *src, bool hidden)
+ {
+-  return exp_assop (dst, src, etree_assign, hidden);
++  return exp_assop (dst, src, etree_assign, false, hidden);
+ }
+ 
+ /* Handle --defsym command-line option.  */
+@@ -1430,7 +1432,7 @@ exp_assign (const char *dst, etree_type *src, bool hidden)
+ etree_type *
+ exp_defsym (const char *dst, etree_type *src)
+ {
+-  return exp_assop (dst, src, etree_assign, false);
++  return exp_assop (dst, src, etree_assign, true, false);
+ }
+ 
+ /* Handle PROVIDE.  */
+@@ -1438,7 +1440,7 @@ exp_defsym (const char *dst, etree_type *src)
+ etree_type *
+ exp_provide (const char *dst, etree_type *src, bool hidden)
+ {
+-  return exp_assop (dst, src, etree_provide, hidden);
++  return exp_assop (dst, src, etree_provide, false, hidden);
+ }
+ 
+ /* Handle ASSERT.  */
+diff --git a/ld/ldexp.h b/ld/ldexp.h
+index c779729e900..6d583e1b15a 100644
+--- a/ld/ldexp.h
++++ b/ld/ldexp.h
+@@ -66,6 +66,7 @@ typedef union etree_union {
+     node_type type;
+     const char *dst;
+     union etree_union *src;
++    bool defsym;
+     bool hidden;
+   } assign;
+   struct {
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0028-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0028-fixing-the-long-long-long-mingw-toolchain-issue.patch
new file mode 100644
index 00000000..675ce3ee
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0028-fixing-the-long-long-long-mingw-toolchain-issue.patch
@@ -0,0 +1,58 @@
+From 21eacbba925e2aaceaf3d3400030ae61a1aa4fef Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 29 Nov 2018 17:59:25 +0530
+Subject: [PATCH 28/53] fixing the long & long long mingw toolchain issue
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c | 10 +++++-----
+ opcodes/microblaze-opc.h   |  4 ++--
+ 2 files changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index c9757796ae8..a8194d175e1 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -754,7 +754,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max)
+ }
+ 
+  static char *
+-parse_imml (char * s, expressionS * e, long min, long max)
++parse_imml (char * s, expressionS * e, long long min, long long max)
+ {
+   char *new_pointer;
+   char *atp;
+@@ -805,11 +805,11 @@ parse_imml (char * s, expressionS * e, long min, long max)
+     ; /* An error message has already been emitted.  */
+   else if ((e->X_op != O_constant && e->X_op != O_symbol) )
+     as_fatal (_("operand must be a constant or a label"));
+-  else if ((e->X_op == O_constant) && ((long) e->X_add_number < min
+-                                      || (long) e->X_add_number > max))
++  else if ((e->X_op == O_constant) && ((long long) e->X_add_number < min
++                                      || (long long) e->X_add_number > max))
+     {
+-      as_fatal (_("operand must be absolute in range %ld..%ld, not %ld"),
+-                min, max, (long) e->X_add_number);
++      as_fatal (_("operand must be absolute in range %lld..%lld, not %lld"),
++                min, max, (long long) e->X_add_number);
+     }
+ 
+   if (atp)
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index d9d05721dae..f85f5a600cc 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -592,8 +592,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM6_WIDTH  ((int) 0x00000001)
+ #define MAX_IMM6_WIDTH  ((int) 0x00000040)
+ 
+-#define MIN_IMML  ((long) 0xffffff8000000000L)
+-#define MAX_IMML  ((long) 0x0000007fffffffffL)
++#define MIN_IMML  ((long long) 0xffffff8000000000L)
++#define MAX_IMML  ((long long) 0x0000007fffffffffL)
+ 
+ #endif /* MICROBLAZE_OPC */
+ 
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0029-Added-support-to-new-arithmetic-single-register-inst.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0029-Added-support-to-new-arithmetic-single-register-inst.patch
new file mode 100644
index 00000000..6199a4e5
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0029-Added-support-to-new-arithmetic-single-register-inst.patch
@@ -0,0 +1,371 @@
+From c0cff55375899b12045eef8f5755e68a598ee4ff Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Fri, 23 Aug 2019 16:18:43 +0530
+Subject: [PATCH 29/53] Added support to new arithmetic single register
+ instructions
+
+Conflicts:
+        opcodes/microblaze-dis.c
+
+Conflicts:
+        gas/config/tc-microblaze.c
+        opcodes/microblaze-dis.c
+
+Conflicts:
+        gas/config/tc-microblaze.c
+signed-off-by:Nagaraju <nmekala@xilinx.com>
+              Mahesh <mbodapat@xilinx.com>
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c | 147 ++++++++++++++++++++++++++++++++++++-
+ opcodes/microblaze-dis.c   |  11 +++
+ opcodes/microblaze-opc.h   |  43 ++++++++++-
+ opcodes/microblaze-opcm.h  |   5 +-
+ 4 files changed, 200 insertions(+), 6 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index a8194d175e1..3c9aec4c1f9 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -394,12 +394,33 @@ void
+ md_begin (void)
+ {
+   const struct op_code_struct * opcode;
++  const char *prev_name = "";
+ 
+   opcode_hash_control = str_htab_create ();
+ 
+   /* Insert unique names into hash table.  */
+-  for (opcode = microblaze_opcodes; opcode->name; opcode ++)
+-    str_hash_insert (opcode_hash_control, opcode->name, opcode, 0);
++  for (opcode = (struct microblaze_opcodes *)microblaze_opcodes; opcode->name; opcode ++)
++    {
++      if (strcmp (prev_name, opcode->name))
++       {
++         prev_name = (char *) opcode->name;
++          str_hash_insert (opcode_hash_control, opcode->name, opcode, 0);
++        }
++    }
++}
++
++static int
++is_reg (char * s)
++{
++  int is_reg = 0; 
++  /* Strip leading whitespace.  */
++  while (ISSPACE (* s))
++    ++ s;
++  if (TOLOWER (s[0]) == 'r')
++    {
++        is_reg =1;
++    }
++  return is_reg;
+ }
+ 
+ /* Try to parse a reg name.  */
+@@ -957,6 +978,7 @@ md_assemble (char * str)
+ {
+   char * op_start;
+   char * op_end;
++  char * temp_op_end;
+   struct op_code_struct * opcode, *opcode1;
+   char * output = NULL;
+   int nlen = 0;
+@@ -967,9 +989,10 @@ md_assemble (char * str)
+   unsigned reg3;
+   unsigned isize;
+   unsigned long immed = 0, immed2 = 0, temp;
+-  expressionS exp;
++  expressionS exp,exp1;
+   char name[20];
+   long immedl;
++  int reg=0;
+ 
+   /* Drop leading whitespace.  */
+   while (ISSPACE (* str))
+@@ -1000,7 +1023,78 @@ md_assemble (char * str)
+       as_bad (_("unknown opcode \"%s\""), name);
+       return;
+     }
+-
++   
++  if ((microblaze_arch_size == 64) && (streq (name, "addli") || streq (name, "addlic") ||
++        streq (name, "addlik") || streq (name, "addlikc") || streq (name, "rsubli") 
++       || streq (name, "rsublic") || streq (name, "rsublik") || streq (name, "rsublikc") 
++       || streq (name, "andli") || streq (name, "andnli") || streq (name, "orli") 
++       || streq (name, "xorli")))
++    {
++      temp_op_end = op_end;
++      if (strcmp (temp_op_end, ""))
++        temp_op_end = parse_reg (temp_op_end + 1, &reg1);  /* Get rd.  */
++      if (strcmp (temp_op_end, ""))
++        reg  = is_reg (temp_op_end + 1);
++      if (reg) 
++       {
++          
++         opcode->inst_type=INST_TYPE_RD_R1_IMML;
++          opcode->inst_offset_type = OPCODE_MASK_H;
++          if (streq (name, "addli"))
++           opcode->bit_sequence = ADDLI_MASK;
++          else if (streq (name, "addlic"))
++           opcode->bit_sequence = ADDLIC_MASK;
++          else if (streq (name, "addlik"))
++           opcode->bit_sequence = ADDLIK_MASK;
++          else if (streq (name, "addlikc"))
++           opcode->bit_sequence = ADDLIKC_MASK;
++          else if (streq (name, "rsubli"))
++           opcode->bit_sequence = RSUBLI_MASK;
++          else if (streq (name, "rsublic"))
++           opcode->bit_sequence = RSUBLIC_MASK;
++          else if (streq (name, "rsublik"))
++           opcode->bit_sequence = RSUBLIK_MASK;
++          else if (streq (name, "rsublikc"))
++           opcode->bit_sequence = RSUBLIKC_MASK;
++          else if (streq (name, "andli"))
++           opcode->bit_sequence = ANDLI_MASK;
++          else if (streq (name, "andnli"))
++           opcode->bit_sequence = ANDLNI_MASK;
++          else if (streq (name, "orli"))
++           opcode->bit_sequence = ORLI_MASK;
++          else if (streq (name, "xorli"))
++           opcode->bit_sequence = XORLI_MASK;
++       }
++      else
++        {
++         opcode->inst_type=INST_TYPE_RD_IMML;
++          opcode->inst_offset_type = OPCODE_MASK_LIMM;
++          if (streq (name, "addli"))
++           opcode->bit_sequence = ADDLI_ONE_REG_MASK;
++          else if (streq (name, "addlic"))
++           opcode->bit_sequence = ADDLIC_ONE_REG_MASK;
++          else if (streq (name, "addlik"))
++           opcode->bit_sequence = ADDLIK_ONE_REG_MASK;
++          else if (streq (name, "addlikc"))
++           opcode->bit_sequence = ADDLIKC_ONE_REG_MASK;
++          else if (streq (name, "rsubli"))
++           opcode->bit_sequence = RSUBLI_ONE_REG_MASK;
++          else if (streq (name, "rsublic"))
++           opcode->bit_sequence = RSUBLIC_ONE_REG_MASK;
++          else if (streq (name, "rsublik"))
++           opcode->bit_sequence = RSUBLIK_ONE_REG_MASK;
++          else if (streq (name, "rsublikc"))
++           opcode->bit_sequence = RSUBLIKC_ONE_REG_MASK;
++          else if (streq (name, "andli"))
++           opcode->bit_sequence = ANDLI_ONE_REG_MASK;
++          else if (streq (name, "andnli"))
++           opcode->bit_sequence = ANDLNI_ONE_REG_MASK;
++          else if (streq (name, "orli"))
++           opcode->bit_sequence = ORLI_ONE_REG_MASK;
++          else if (streq (name, "xorli"))
++           opcode->bit_sequence = XORLI_ONE_REG_MASK;
++        }
++    }
+   inst = opcode->bit_sequence;
+   isize = 4;
+ 
+@@ -1457,6 +1551,51 @@ md_assemble (char * str)
+       inst |= (immed << IMM_LOW) & IMM15_MASK;
+       break;
+ 
++    case INST_TYPE_RD_IMML:
++      if (strcmp (op_end, ""))
++        op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
++      else
++        {
++          as_fatal (_("Error in statement syntax"));
++          reg1 = 0;
++        }
++
++      if (strcmp (op_end, ""))
++        op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++      else
++        as_fatal (_("Error in statement syntax"));
++
++      /* Check for spl registers. */
++      if (check_spl_reg (&reg1))
++        as_fatal (_("Cannot use special register with this instruction"));
++      if (exp.X_op != O_constant)
++       {
++          char *opc = NULL;
++          relax_substateT subtype;
++
++          if (exp.X_md != 0)
++            subtype = get_imm_otype(exp.X_md);
++          else
++            subtype = opcode->inst_offset_type;
++
++          output = frag_var (rs_machine_dependent,
++                             isize * 2, 
++                             isize * 2,
++                             subtype,   
++                             exp.X_add_symbol,
++                             exp.X_add_number,
++                             (char *) opc);
++          immedl = 0L;
++       }               
++      else
++        {
++          output = frag_more (isize);
++          immed = exp.X_add_number;
++        }
++      inst |= (reg1 << RD_LOW) & RD_MASK;
++      inst |= (immed << IMM_LOW) & IMM16_MASK;
++      break;
++       
+     case INST_TYPE_R1_RFSL:
+       if (strcmp (op_end, ""))
+         op_end = parse_reg (op_end + 1, &reg1);  /* Get r1.  */
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 45262aef909..bdc6db79726 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -143,6 +143,14 @@ get_field_imm15 (struct string_buf *buf, long instr)
+   return p;
+ }
+ 
++get_field_imm16 (struct string_buf *buf, long instr)
++{
++  char *p = strbuf (buf);
++
++  sprintf (p, "%d", (short)((instr & IMM16_MASK) >> IMM_LOW));
++  return p;
++}
++
+ static char *
+ get_field_special (struct string_buf *buf, long instr,
+                   const struct op_code_struct *op)
+@@ -473,6 +481,9 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+          /* For mbar 16 or sleep insn.  */
+        case INST_TYPE_NONE:
+          break;
++       case INST_TYPE_RD_IMML:
++         print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst));
++          break;
+         /* For bit field insns.  */
+        case INST_TYPE_RD_R1_IMMW_IMMS:
+          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst),
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index f85f5a600cc..6228114698b 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -77,6 +77,7 @@
+ #define INST_TYPE_RD_R1_IMMW_IMMS  21
+ 
+ #define INST_TYPE_NONE 25
++#define INST_TYPE_RD_IMML 26
+ 
+ 
+ 
+@@ -92,6 +93,7 @@
+ #define IMMVAL_MASK_MFS 0x0000
+ 
+ #define OPCODE_MASK_H     0xFC000000 /* High 6 bits only.  */
++#define OPCODE_MASK_LIMM 0xFC1F0000 /* High 6 bits and 12-16 bits */
+ #define OPCODE_MASK_H1    0xFFE00000 /* High 11 bits.  */
+ #define OPCODE_MASK_H2    0xFC1F0000 /* High 6 and bits 20-16.  */
+ #define OPCODE_MASK_H12   0xFFFF0000 /* High 16.  */
+@@ -114,6 +116,33 @@
+ #define OPCODE_MASK_H34C  0xFC0007E0 /* High 6 bits and bits 21-26.  */
+ #define OPCODE_MASK_H8    0xFF000000 /* High 8 bits only.  */
+ 
++/*Defines to identify 64-bit single reg instructions */
++#define ADDLI_ONE_REG_MASK 0x68000000
++#define ADDLIC_ONE_REG_MASK 0x68020000
++#define ADDLIK_ONE_REG_MASK 0x68040000
++#define ADDLIKC_ONE_REG_MASK 0x68060000
++#define RSUBLI_ONE_REG_MASK 0x68010000
++#define RSUBLIC_ONE_REG_MASK 0x68030000
++#define RSUBLIK_ONE_REG_MASK 0x68050000
++#define RSUBLIKC_ONE_REG_MASK 0x68070000
++#define ORLI_ONE_REG_MASK 0x68100000
++#define ANDLI_ONE_REG_MASK 0x68110000
++#define XORLI_ONE_REG_MASK 0x68120000
++#define ANDLNI_ONE_REG_MASK 0x68130000
++#define ADDLI_MASK 0x20000000
++#define ADDLIC_MASK 0x28000000
++#define ADDLIK_MASK 0x30000000
++#define ADDLIKC_MASK 0x38000000
++#define RSUBLI_MASK 0x24000000
++#define RSUBLIC_MASK 0x2C000000
++#define RSUBLIK_MASK 0x34000000
++#define RSUBLIKC_MASK 0x3C000000
++#define ANDLI_MASK 0xA4000000
++#define ANDLNI_MASK 0xAC000000
++#define ORLI_MASK 0xA0000000
++#define XORLI_MASK 0xA8000000
++
++
+ /* New Mask for msrset, msrclr insns.  */
+ #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16.  */
+ /* Mask for mbar insn.  */
+@@ -122,7 +151,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 412
++#define MAX_OPCODES 424
+ 
+ const struct op_code_struct
+ {
+@@ -451,13 +480,21 @@ const struct op_code_struct
+   {"cmpl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
+   {"cmplu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
+   {"addli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68000000, OPCODE_MASK_LIMM, addli, arithmetic_inst },
+   {"rsubli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsubli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68010000, OPCODE_MASK_LIMM, rsubli, arithmetic_inst },
+   {"addlic",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68020000, OPCODE_MASK_LIMM, addlic, arithmetic_inst },
+   {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++    {"rsublic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68030000, OPCODE_MASK_LIMM, rsublic, arithmetic_inst },
+   {"addlik",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68040000, OPCODE_MASK_LIMM, addlik, arithmetic_inst },
+   {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsublik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68050000, OPCODE_MASK_LIMM, rsublik, arithmetic_inst },
+   {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68060000, OPCODE_MASK_LIMM, addlikc, arithmetic_inst },
+   {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },  /* Identical to 32-bit */
++  {"rsublikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68070000, OPCODE_MASK_LIMM, rsublikc, arithmetic_inst },
+   {"mull",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
+   {"bslll",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
+   {"bslra",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
+@@ -508,9 +545,13 @@ const struct op_code_struct
+   {"beaged",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
+   {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
+   {"orli",    INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"orli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68100000, OPCODE_MASK_LIMM, orli, arithmetic_inst },
+   {"andli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"andli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68110000, OPCODE_MASK_LIMM, andli, arithmetic_inst },
+   {"xorli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"xorli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68120000, OPCODE_MASK_LIMM, xorli, arithmetic_inst },
+   {"andnli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"andnli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68130000, OPCODE_MASK_LIMM, andnli, arithmetic_inst },
+   {"imml",    INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
+   {"breai",   INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
+   {"breaid",  INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 08ed44352ee..a57cabf905f 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -62,7 +62,9 @@ enum microblaze_instr
+   eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
+ 
+   /* 64-bit instructions */
+-  addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++  addl, addli, addlic, addlik, addlikc, rsubl, rsubli, rsublic, rsublik, rsublikc,
++  addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++  andli, andnli, orli, xorli,
+   bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
+   andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
+   brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
+@@ -167,5 +169,6 @@ enum microblaze_instr_type
+ 
+ /* Imm mask for msrset, msrclr instructions.  */
+ #define  IMM15_MASK 0x00007FFF
++#define IMM16_MASK 0x0000FFFF
+ 
+ #endif /* MICROBLAZE-OPCM */
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0030-double-imml-generation-for-64-bit-values.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0030-double-imml-generation-for-64-bit-values.patch
new file mode 100644
index 00000000..eb62eaeb
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0030-double-imml-generation-for-64-bit-values.patch
@@ -0,0 +1,545 @@
+From e4d7207d18e47a9ce5fbf57fc4faa370bf150284 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 26 Aug 2019 15:29:42 +0530
+Subject: [PATCH 30/53] double imml generation for 64 bit values.
+
+Conflicts:
+        gas/config/tc-microblaze.c
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c | 321 ++++++++++++++++++++++++++++++-------
+ opcodes/microblaze-opc.h   |   4 +-
+ 2 files changed, 262 insertions(+), 63 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 3c9aec4c1f9..4da765223be 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -979,7 +979,7 @@ md_assemble (char * str)
+   char * op_start;
+   char * op_end;
+   char * temp_op_end;
+-  struct op_code_struct * opcode, *opcode1;
++  struct op_code_struct * opcode, *opcode1, *opcode2;
+   char * output = NULL;
+   int nlen = 0;
+   int i;
+@@ -1163,7 +1163,12 @@ md_assemble (char * str)
+           reg2 = 0;
+         }
+       if (strcmp (op_end, ""))
++        {
++        if(microblaze_arch_size == 64)
++        op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++       else
+        op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM);
++       }
+       else
+        as_fatal (_("Error in statement syntax"));
+ 
+@@ -1263,26 +1268,51 @@ md_assemble (char * str)
+                || streq (name, "lwi") || streq (name, "sbi")
+                 || streq (name, "shi") || streq (name, "swi"))))
+         {
+-          temp = immed & 0xFFFFFF8000;
+-          if (temp != 0 && temp != 0xFFFFFF8000)
++          temp = ((long long)immed) & 0xFFFFFFFFFFFF8000;
++          if (temp != 0 && temp != 0xFFFFFFFFFFFF8000)
+             {
+               /* Needs an immediate inst.  */
+-             opcode1
+-               = (struct op_code_struct *) str_hash_find (opcode_hash_control,
+-                                                          "imml");
+-              if (opcode1 == NULL)
++          if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
++            {
++             opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++             if (opcode1 == NULL)
+                 {
+                   as_bad (_("unknown opcode \"%s\""), "imml");
+                   return;
+                 }
+               inst1 = opcode1->bit_sequence;
+-             inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+               output[0] = INST_BYTE0 (inst1);
+               output[1] = INST_BYTE1 (inst1);
+               output[2] = INST_BYTE2 (inst1);
+               output[3] = INST_BYTE3 (inst1);
+               output = frag_more (isize);
+             }
++         else 
++           {
++           opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++           opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++              if (opcode1 == NULL || opcode2 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imml");
++                  return;
++                }
++              inst1 = opcode2->bit_sequence;
++              inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++              inst1 = opcode1->bit_sequence;
++              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++            }
++         }
+           inst |= (reg1 << RD_LOW) & RD_MASK;
+           inst |= (reg2 << RA_LOW) & RA_MASK;
+           inst |= (immed << IMM_LOW) & IMM_MASK;
+@@ -1299,8 +1329,7 @@ md_assemble (char * str)
+                    as_bad (_("unknown opcode \"%s\""), "imm");
+                    return;
+                  }
+-
+-               inst1 = opcode1->bit_sequence;
++              inst1 = opcode1->bit_sequence;
+                inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
+                output[0] = INST_BYTE0 (inst1);
+                output[1] = INST_BYTE1 (inst1);
+@@ -1541,7 +1570,7 @@ md_assemble (char * str)
+         as_fatal (_("Cannot use special register with this instruction"));
+ 
+       if (exp.X_op != O_constant)
+-        as_fatal (_("Symbol used as immediate value for msrset/msrclr instructions"));
++        as_fatal (_("Symbol used as immediate value for arithmetic long instructions"));
+       else
+        {
+           output = frag_more (isize);
+@@ -1875,6 +1904,7 @@ md_assemble (char * str)
+       temp = immed & 0xFFFF8000;
+       if ((temp != 0) && (temp != 0xFFFF8000))
+        {
++
+           /* Needs an immediate inst.  */
+          opcode1
+            = (struct op_code_struct *) str_hash_find (opcode_hash_control,
+@@ -1907,7 +1937,12 @@ md_assemble (char * str)
+           reg1 = 0;
+         }
+       if (strcmp (op_end, ""))
++      {
++        if(microblaze_arch_size == 64)
++        op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++        else
+         op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM);
++      }
+       else
+         as_fatal (_("Error in statement syntax"));
+ 
+@@ -1946,30 +1981,55 @@ md_assemble (char * str)
+         }
+       if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai"))
+         {
+-          temp = immed & 0xFFFFFF8000;
+-          if (temp != 0 && temp != 0xFFFFFF8000)
++          temp = ((long long)immed) & 0xFFFFFFFFFFFF8000;
++          if (temp != 0 && temp != 0xFFFFFFFFFFFF8000)
+             {
+               /* Needs an immediate inst.  */
+-              opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++           if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
++           {
++            opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
+               if (opcode1 == NULL)
+                 {
+                   as_bad (_("unknown opcode \"%s\""), "imml");
+                   return;
+                 }
+               inst1 = opcode1->bit_sequence;
+-             inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+               output[0] = INST_BYTE0 (inst1);
+               output[1] = INST_BYTE1 (inst1);
+               output[2] = INST_BYTE2 (inst1);
+               output[3] = INST_BYTE3 (inst1);
+               output = frag_more (isize);
+             }
++          else {
++           opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++           opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++              if (opcode1 == NULL || opcode2 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imml");
++                  return;
++                }
++              inst1 = opcode2->bit_sequence;
++              inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++              inst1 = opcode1->bit_sequence;
++              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++          }
++         }
+          inst |= (reg1 << RD_LOW) & RD_MASK;
+           inst |= (immed << IMM_LOW) & IMM_MASK;
+          }
+        else 
+         {
+-
+       temp = immed & 0xFFFF8000;
+       if ((temp != 0) && (temp != 0xFFFF8000))
+        {
+@@ -2057,24 +2117,50 @@ md_assemble (char * str)
+             streq (name, "breaid") || 
+            streq (name, "brai") || streq (name, "braid")))
+         {
+-          temp = immed & 0xFFFFFF8000;
++          temp = immed & 0xFFFFFFFFFFFF8000;
+           if (temp != 0)
+            {
+               /* Needs an immediate inst.  */
+-              opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++         if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
++          {
++            opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
+               if (opcode1 == NULL)
+                 {
+                   as_bad (_("unknown opcode \"%s\""), "imml");
+                   return;
+                 }
+               inst1 = opcode1->bit_sequence;
+-              inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+               output[0] = INST_BYTE0 (inst1);
+               output[1] = INST_BYTE1 (inst1);
+               output[2] = INST_BYTE2 (inst1);
+               output[3] = INST_BYTE3 (inst1);
+               output = frag_more (isize);
+             }
++           else {
++           opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++           opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++              if (opcode1 == NULL || opcode2 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imml");
++                  return;
++                }
++              inst1 = opcode2->bit_sequence;
++              inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++              inst1 = opcode1->bit_sequence;
++              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++            }
++            }
+           inst |= (immed << IMM_LOW) & IMM_MASK;
+        }
+       else
+@@ -2394,8 +2480,8 @@ md_apply_fix (fixS *   fixP,
+   /* Note: use offsetT because it is signed, valueT is unsigned.  */
+   offsetT      val  = (offsetT) * valp;
+   int          i;
+-  struct op_code_struct * opcode1;
+-  unsigned long inst1;
++  struct op_code_struct * opcode1, * opcode2;
++  unsigned long inst1,inst2;
+ 
+   symname = fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : _("<unknown>");
+ 
+@@ -2576,30 +2662,75 @@ md_apply_fix (fixS *   fixP,
+     case BFD_RELOC_MICROBLAZE_64_TEXTREL:
+     case BFD_RELOC_MICROBLAZE_64:
+     case BFD_RELOC_MICROBLAZE_64_PCREL:
+-      /* Add an imm instruction.  First save the current instruction.  */
+-      for (i = 0; i < INST_WORD_SIZE; i++)
+-       buf[i + INST_WORD_SIZE] = buf[i];
+       if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64
+             || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
+         {
+           /* Generate the imm instruction.  */
+-          opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++           if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887)
++          {
++        /* Add an imm instruction.  First save the current instruction.  */
++        for (i = 0; i < INST_WORD_SIZE; i++)
++        buf[i + INST_WORD_SIZE] = buf[i];
++        opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
+           if (opcode1 == NULL)
+-           {
+-             as_bad (_("unknown opcode \"%s\""), "imml");
+-             return;
+-           }
++            {
++              as_bad (_("unknown opcode \"%s\""), "imml");
++              return;
++            }
+ 
+            inst1 = opcode1->bit_sequence;
+            if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+-            inst1 |= ((val & 0xFFFFFF0000L) >> 16) & IMML_MASK;
++             inst1 |= ((val & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
++             fixP->fx_r_type = BFD_RELOC_64;
++           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
++             fixP->fx_r_type = BFD_RELOC_64_PCREL;
++      buf[0] = INST_BYTE0 (inst1);
++      buf[1] = INST_BYTE1 (inst1);
++      buf[2] = INST_BYTE2 (inst1);
++      buf[3] = INST_BYTE3 (inst1);
++        }
++           else {
++      /* Add an imm instruction.  First save the current instruction.  */
++        for (i = 0; i < INST_WORD_SIZE; i++)
++        buf[i + INST_WORD_SIZE + 4] = buf[i];
++
++           opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++           opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++          if (opcode1 == NULL || opcode2 ==NULL)
++              {
++             as_bad (_("unknown opcode \"%s\""), "imml");
++              return;
++             }
++           inst1 = opcode2->bit_sequence;
++           if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
++             inst1 |= ((val & 0x000000FFFFFF0000L) >> 40) & IMML_MASK;
++           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
++             fixP->fx_r_type = BFD_RELOC_64;
++           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
++             fixP->fx_r_type = BFD_RELOC_64_PCREL;
++           inst2 = opcode1->bit_sequence;
++           if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
++             inst1 |= ((val & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+            if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
+-             fixP->fx_r_type = BFD_RELOC_64; 
++             fixP->fx_r_type = BFD_RELOC_64;
+            if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
+-             fixP->fx_r_type = BFD_RELOC_64_PCREL; 
++             fixP->fx_r_type = BFD_RELOC_64_PCREL;
++       buf[0] = INST_BYTE0 (inst1);
++       buf[1] = INST_BYTE1 (inst1);
++       buf[2] = INST_BYTE2 (inst1);
++       buf[3] = INST_BYTE3 (inst1);
++       buf[4] = INST_BYTE0 (inst2);
++       buf[5] = INST_BYTE1 (inst2);
++       buf[6] = INST_BYTE2 (inst2);
++       buf[7] = INST_BYTE3 (inst2);
++           }
+          }
+       else
+         {
++      /* Add an imm instruction.  First save the current instruction.  */
++        for (i = 0; i < INST_WORD_SIZE; i++)
++        buf[i + INST_WORD_SIZE] = buf[i];
+           /* Generate the imm instruction.  */
+           opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imm");
+           if (opcode1 == NULL)
+@@ -2611,12 +2742,11 @@ md_apply_fix (fixS *   fixP,
+           inst1 = opcode1->bit_sequence;
+           if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+            inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK;
+-         }
+       buf[0] = INST_BYTE0 (inst1);
+       buf[1] = INST_BYTE1 (inst1);
+       buf[2] = INST_BYTE2 (inst1);
+       buf[3] = INST_BYTE3 (inst1);
+-
++         }
+       /* Add the value only if the symbol is defined.  */
+       if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+        {
+@@ -2649,21 +2779,41 @@ md_apply_fix (fixS *   fixP,
+       for (i = 0; i < INST_WORD_SIZE; i++)
+        buf[i + INST_WORD_SIZE] = buf[i];
+       /* Generate the imm instruction.  */
+-      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
+-        opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) {
++           if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887)
++           {
++           for (i = 0; i < INST_WORD_SIZE; i++)
++           buf[i + INST_WORD_SIZE] = buf[i];
++           opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++          }
++           else {
++       for (i = 0; i < INST_WORD_SIZE; i++)
++        buf[i + INST_WORD_SIZE + 4] = buf[i]; 
++           opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++           opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++      inst2 = opcode2->bit_sequence;
++
++      /* We can fixup call to a defined non-global address
++ *          within the same section only.  */
++      buf[4] = INST_BYTE0 (inst2);
++      buf[5] = INST_BYTE1 (inst2);
++      buf[6] = INST_BYTE2 (inst2);
++      buf[7] = INST_BYTE3 (inst2);
++           }
++       }
+       else
+         opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imm");
+       if (opcode1 == NULL)
+        {
++      for (i = 0; i < INST_WORD_SIZE; i++)
++        buf[i + INST_WORD_SIZE] = buf[i];
+          if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
+            as_bad (_("unknown opcode \"%s\""), "imml");
+           else
+            as_bad (_("unknown opcode \"%s\""), "imm");
+          return;
+        }
+-
+       inst1 = opcode1->bit_sequence;
+-
+       /* We can fixup call to a defined non-global address
+         within the same section only.  */
+       buf[0] = INST_BYTE0 (inst1);
+@@ -3025,21 +3175,45 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+        {
+          output = frag_more (isize);
+          immedl = exp.X_add_number;
+-
+-         opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
+-         if (opcode1 == NULL)
+-           {
+-             as_bad (_("unknown opcode \"%s\""), "imml");
+-             return;
+-           }
+-
+-         inst1 = opcode1->bit_sequence;
+-         inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
+-         output[0] = INST_BYTE0 (inst1);
+-         output[1] = INST_BYTE1 (inst1);
+-         output[2] = INST_BYTE2 (inst1);
+-         output[3] = INST_BYTE3 (inst1);
+-         output = frag_more (isize);
++         if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887)
++            {
++             opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++             if (opcode1 == NULL)
++             {
++              as_bad (_("unknown opcode \"%s\""), "imml");
++              return;
++             }
++          inst1 = opcode1->bit_sequence;
++          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++        }
++           else {
++           opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++           opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++       if (opcode2 == NULL || opcode1 == NULL)
++            {
++              as_bad (_("unknown opcode \"%s\""), "imml");
++              return;
++            }
++          inst1 = opcode2->bit_sequence;
++          inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++          inst1 = opcode1->bit_sequence;
++          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++        }
+         }
+ 
+       inst |= (reg1 << RD_LOW) & RD_MASK;
+@@ -3088,20 +3262,45 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+        {
+           output = frag_more (isize);
+           immedl = exp.X_add_number;
+-         opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
+-         if (opcode1 == NULL)
+-           {
+-             as_bad (_("unknown opcode \"%s\""), "imml");
+-             return;
+-           }
+-
++          if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887)
++             {
++            opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++           if (opcode1 == NULL)
++            {
++              as_bad (_("unknown opcode \"%s\""), "imml");
++              return;
++            }
+           inst1 = opcode1->bit_sequence;
+-         inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+           output[0] = INST_BYTE0 (inst1);
+           output[1] = INST_BYTE1 (inst1);
+           output[2] = INST_BYTE2 (inst1);
+           output[3] = INST_BYTE3 (inst1);
+           output = frag_more (isize);
++          }
++           else {
++           opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++           opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++       if (opcode2 == NULL || opcode1 == NULL)
++            {
++              as_bad (_("unknown opcode \"%s\""), "imml");
++              return;
++            }
++          inst1 = opcode2->bit_sequence;
++          inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++          inst1 = opcode1->bit_sequence;
++          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++        }
+         }
+ 
+       inst |= (reg1 << RA_LOW) & RA_MASK;
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 6228114698b..f46fc76a94a 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -633,8 +633,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM6_WIDTH  ((int) 0x00000001)
+ #define MAX_IMM6_WIDTH  ((int) 0x00000040)
+ 
+-#define MIN_IMML  ((long long) 0xffffff8000000000L)
+-#define MAX_IMML  ((long long) 0x0000007fffffffffL)
++#define MIN_IMML  ((long long) -9223372036854775808)
++#define MAX_IMML  ((long long) 9223372036854775807)
+ 
+ #endif /* MICROBLAZE_OPC */
+ 
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0031-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0031-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch
new file mode 100644
index 00000000..5bc507ce
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0031-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch
@@ -0,0 +1,88 @@
+From 3cd07844b77691afeb675806cc4c73fe08d2c30e Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 3 Nov 2021 12:13:32 +0530
+Subject: [PATCH 31/53] Fixed bug in generation of IMML instruction for the
+
+new MB-64 instructions with single register.
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c | 50 +++++++++++++++++++++++++++++++++++---
+ 1 file changed, 47 insertions(+), 3 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 4da765223be..651d855c800 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -1614,12 +1614,56 @@ md_assemble (char * str)
+                              exp.X_add_symbol,
+                              exp.X_add_number,
+                              (char *) opc);
+-          immedl = 0L;
++          immed = 0L;
+        }               
+       else
+         {
+           output = frag_more (isize);
+           immed = exp.X_add_number;
++          temp = ((long long)immed) & 0xFFFFFFFFFFFF8000;
++          if (temp != 0 && temp != 0xFFFFFFFFFFFF8000 && temp != 0x8000)
++            {
++              /* Needs an immediate inst.  */
++           if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
++           {
++            opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++              if (opcode1 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imml");
++                  return;
++                }
++              inst1 = opcode1->bit_sequence;
++              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++            }
++          else {
++           opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++           opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++              if (opcode1 == NULL || opcode2 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imml");
++                  return;
++                }
++              inst1 = opcode2->bit_sequence;
++              inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++              inst1 = opcode1->bit_sequence;
++              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++          }
++         }
+         }
+       inst |= (reg1 << RD_LOW) & RD_MASK;
+       inst |= (immed << IMM_LOW) & IMM16_MASK;
+@@ -2117,8 +2161,8 @@ md_assemble (char * str)
+             streq (name, "breaid") || 
+            streq (name, "brai") || streq (name, "braid")))
+         {
+-          temp = immed & 0xFFFFFFFFFFFF8000;
+-          if (temp != 0)
++          temp = ((long long)immed) & 0xFFFFFFFFFFFF8000;
++          if (temp != 0 && temp != 0xFFFFFFFFFFFF8000 && temp != 0x8000)
+            {
+               /* Needs an immediate inst.  */
+          if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0032-This-patch-will-remove-imml-0-and-imml-1-instruction.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0032-This-patch-will-remove-imml-0-and-imml-1-instruction.patch
new file mode 100644
index 00000000..686c8827
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0032-This-patch-will-remove-imml-0-and-imml-1-instruction.patch
@@ -0,0 +1,38 @@
+From 6e672cb099ae9670a9be1d26e36fa33df5757191 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 16 Apr 2020 18:08:58 +0530
+Subject: [PATCH 32/53] This patch will remove imml 0 and imml -1 instructions
+ when the offset is less than 16 bit for Type A branch EA instructions.
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 651d855c800..ce0d3e26204 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -2129,9 +2129,7 @@ md_assemble (char * str)
+       if (exp.X_op != O_constant)
+        {
+          char *opc;
+-          if (microblaze_arch_size == 64 && (streq (name, "breai") || 
+-                streq (name, "breaid") || 
+-                streq (name, "brai") || streq (name, "braid")))
++          if (microblaze_arch_size == 64 && (streq (name, "brai") || streq (name, "braid")))
+             opc = str_microblaze_64;
+          else
+             opc = NULL;
+@@ -2707,7 +2705,7 @@ md_apply_fix (fixS *   fixP,
+     case BFD_RELOC_MICROBLAZE_64:
+     case BFD_RELOC_MICROBLAZE_64_PCREL:
+       if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64
+-            || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
++            || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL || (fixP->fx_r_type == BFD_RELOC_64_PCREL && microblaze_arch_size == 64))
+         {
+           /* Generate the imm instruction.  */
+            if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887)
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0033-Changing-the-long-to-long-long-as-in-Windows-long-is.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0033-Changing-the-long-to-long-long-as-in-Windows-long-is.patch
new file mode 100644
index 00000000..1dbeaf0e
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0033-Changing-the-long-to-long-long-as-in-Windows-long-is.patch
@@ -0,0 +1,32 @@
+From 0c29905801152c8b8230bcca00b49b945054586b Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilinx.com>
+Date: Tue, 20 Apr 2021 21:22:06 +0530
+Subject: [PATCH 33/53] Changing the long to long long as in Windows long is
+ 32-bit but we need the variable to be 64-bit
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+
+Conflicts:
+        gas/config/tc-microblaze.c
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index ce0d3e26204..dc87429a4e8 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -988,7 +988,7 @@ md_assemble (char * str)
+   unsigned reg2;
+   unsigned reg3;
+   unsigned isize;
+-  unsigned long immed = 0, immed2 = 0, temp;
++  unsigned long long immed = 0, immed2 = 0, temp;
+   expressionS exp,exp1;
+   char name[20];
+   long immedl;
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0034-gas-revert-moving-of-md_pseudo_table-from-const.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0034-gas-revert-moving-of-md_pseudo_table-from-const.patch
new file mode 100644
index 00000000..943d3158
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0034-gas-revert-moving-of-md_pseudo_table-from-const.patch
@@ -0,0 +1,62 @@
+From ec4fac4177c4364f52d1bc6ba53ffd971323cc22 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 8 Nov 2021 21:57:13 +0530
+Subject: [PATCH 34/53] gas: revert moving of md_pseudo_table from const
+
+The base system expect md_pseudo_table to be constant, Changing the
+definition will break other architectures when compiled with a
+unified source code.
+
+Patch reverts the change away from const, and implements a newer
+dynamic handler that passes the correct argument value based on word
+size.
+
+Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c | 15 ++++++++++++---
+ 1 file changed, 12 insertions(+), 3 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index dc87429a4e8..faa458af3a0 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -356,6 +356,17 @@ microblaze_s_weakext (int ignore ATTRIBUTE_UNUSED)
+   demand_empty_rest_of_line ();
+ }
+ 
++/* Handle the .gpword pseudo-op, Pass to s_rva */
++
++static void
++microblaze_s_gpword (int ignore ATTRIBUTE_UNUSED)
++{
++  int size = 4;
++  if (microblaze_arch_size == 64)
++    size = 8;
++  s_rva(size);
++}
++
+ /* This table describes all the machine specific pseudo-ops the assembler
+    has to support.  The fields are:
+    Pseudo-op name without dot
+@@ -371,7 +382,7 @@ const pseudo_typeS md_pseudo_table[] =
+   {"data32", cons, 4},     /* Same as word.  */
+   {"ent", s_func, 0}, /* Treat ent as function entry point.  */
+   {"end", microblaze_s_func, 1}, /* Treat end as function end point.  */
+-  {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section.  */
++  {"gpword", microblaze_s_gpword, 0}, /* gpword label => store resolved label address in data section.  */
+   {"weakext", microblaze_s_weakext, 0},
+   {"rodata", microblaze_s_rdata, 0},
+   {"sdata2", microblaze_s_rdata, 1},
+@@ -3425,8 +3436,6 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+     case OPTION_M64:
+       //if (arg != NULL && strcmp (arg, "64") == 0)
+       microblaze_arch_size = 64;
+-      // UPSTREAM/REVISIT - md_pseudo_table is const
+-      // md_pseudo_table[7].poc_val = 8;
+       break;
+     default:
+       return 0;
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch
new file mode 100644
index 00000000..c3ff9baf
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch
@@ -0,0 +1,44 @@
+From 2148cf1617fe1168ea747346d407e2ece94e163a Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 8 Nov 2021 22:01:23 +0530
+Subject: [PATCH 35/53] ld/emulparams/elf64microblaze: Fix emulation generation
+
+Compilation fails when building ld-new with:
+
+ldemul.o:(.data.rel+0x820): undefined reference to `ld_elf64microblazeel_emulation'
+ldemul.o:(.data.rel+0x828): undefined reference to `ld_elf64microblaze_emulation'
+
+The error appears to be that the elf64 files were referencing the elf32 emulation.
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ ld/emulparams/elf64microblaze.sh   | 2 +-
+ ld/emulparams/elf64microblazeel.sh | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/ld/emulparams/elf64microblaze.sh b/ld/emulparams/elf64microblaze.sh
+index 9c7b0eb7080..7b4c7c411bd 100644
+--- a/ld/emulparams/elf64microblaze.sh
++++ b/ld/emulparams/elf64microblaze.sh
+@@ -19,5 +19,5 @@ NOP=0x80000000
+ #$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
+ #OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
+ 
+-TEMPLATE_NAME=elf32
++TEMPLATE_NAME=elf
+ #GENERATE_SHLIB_SCRIPT=yes
+diff --git a/ld/emulparams/elf64microblazeel.sh b/ld/emulparams/elf64microblazeel.sh
+index 9c7b0eb7080..7b4c7c411bd 100644
+--- a/ld/emulparams/elf64microblazeel.sh
++++ b/ld/emulparams/elf64microblazeel.sh
+@@ -19,5 +19,5 @@ NOP=0x80000000
+ #$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
+ #OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
+ 
+-TEMPLATE_NAME=elf32
++TEMPLATE_NAME=elf
+ #GENERATE_SHLIB_SCRIPT=yes
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch
new file mode 100644
index 00000000..fd03fc4c
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch
@@ -0,0 +1,79 @@
+From 9d691c146a484002e678babb0d40a9387272cb97 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 24 Jan 2022 16:04:07 +0530
+Subject: [PATCH 36/53] Invalid data offsets (pointer) after relaxation.
+ Proposed patch from community member (dednev@rambler.ru) against 2021.1
+ [CR-1115232]
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elf32-microblaze.c | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 7e7c4bf471d..0ba7e36aa5f 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -2176,6 +2176,9 @@ microblaze_elf_relax_section (bfd *abfd,
+                 {
+                   unsigned int val;
+ 
++                 if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                   continue;
++
+                   isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+                   /* hax: We only do the following fixup for debug location lists.  */
+@@ -2215,6 +2218,9 @@ microblaze_elf_relax_section (bfd *abfd,
+               }
+               if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)// || ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64)
+                 {
++                 if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                   continue;
++
+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+                  /* Look at the reloc only if the value has been resolved.  */
+@@ -2247,6 +2253,9 @@ microblaze_elf_relax_section (bfd *abfd,
+                    }
+                  else if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_SYM_OP_SYM)
+                    {
++                     if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                       continue;
++
+                      isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+                      /* Look at the reloc only if the value has been resolved.  */
+@@ -2284,6 +2293,9 @@ microblaze_elf_relax_section (bfd *abfd,
+                       || (ELF32_R_TYPE (irelscan->r_info)
+                           == (int) R_MICROBLAZE_TEXTREL_32_LO))
+                {
++                 if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                   continue;
++
+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+                  /* Look at the reloc only if the value has been resolved.  */
+@@ -2330,6 +2342,9 @@ microblaze_elf_relax_section (bfd *abfd,
+                  || (ELF32_R_TYPE (irelscan->r_info)
+                              == (int) R_MICROBLAZE_TEXTREL_64))
+                {
++                 if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                   continue;
++
+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+                  /* Look at the reloc only if the value has been resolved.  */
+@@ -2364,6 +2379,9 @@ microblaze_elf_relax_section (bfd *abfd,
+                }
+              else if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_PCREL)
+                {
++                 if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                   continue;
++
+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+                  /* Look at the reloc only if the value has been resolved.  */
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch
new file mode 100644
index 00000000..2e632939
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch
@@ -0,0 +1,107 @@
+From 36e578efe3e94a6c13b21c364d818d0a8fd675ca Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 24 Jan 2022 16:59:19 +0530
+Subject: [PATCH 37/53] Double free with ld --no-keep-memory. Proposed patches
+ from the community member (dednev@rambler.ru) for 2021.1. [CR-1115233]
+
+Conflicts:
+        bfd/elf32-microblaze.c
+        bfd/elf64-microblaze.c
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elf32-microblaze.c | 40 ++++++++++++++++++++++------------------
+ 1 file changed, 22 insertions(+), 18 deletions(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 0ba7e36aa5f..1ff552a151b 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1882,10 +1882,8 @@ microblaze_elf_relax_section (bfd *abfd,
+ {
+   Elf_Internal_Shdr *symtab_hdr;
+   Elf_Internal_Rela *internal_relocs;
+-  Elf_Internal_Rela *free_relocs = NULL;
+   Elf_Internal_Rela *irel, *irelend;
+   bfd_byte *contents = NULL;
+-  bfd_byte *free_contents = NULL;
+   int rel_count;
+   unsigned int shndx;
+   size_t i, sym_index;
+@@ -1929,8 +1927,6 @@ microblaze_elf_relax_section (bfd *abfd,
+   internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory);
+   if (internal_relocs == NULL)
+     goto error_return;
+-  if (! link_info->keep_memory)
+-    free_relocs = internal_relocs;
+ 
+   sdata->relax_count = 0;
+   sdata->relax = (struct relax_table *) bfd_malloc ((sec->reloc_count + 1)
+@@ -1958,7 +1954,6 @@ microblaze_elf_relax_section (bfd *abfd,
+              contents = (bfd_byte *) bfd_malloc (sec->size);
+              if (contents == NULL)
+                goto error_return;
+-             free_contents = contents;
+ 
+              if (!bfd_get_section_contents (abfd, sec, contents,
+                                             (file_ptr) 0, sec->size))
+@@ -2475,25 +2470,26 @@ microblaze_elf_relax_section (bfd *abfd,
+        }
+ 
+       elf_section_data (sec)->relocs = internal_relocs;
+-      free_relocs = NULL;
+ 
+       elf_section_data (sec)->this_hdr.contents = contents;
+-      free_contents = NULL;
+ 
+       symtab_hdr->contents = (bfd_byte *) isymbuf;
+     }
+ 
+-  free (free_relocs);
+-  free_relocs = NULL;
++  if (internal_relocs != NULL
++      && elf_section_data (sec)->relocs != internal_relocs)
++    free (internal_relocs);
+ 
+-  if (free_contents != NULL)
+-    {
+-      if (!link_info->keep_memory)
+-       free (free_contents);
++  if (contents != NULL
++      && elf_section_data (sec)->this_hdr.contents != contents)
++   {
++      if (! link_info->keep_memory)
++       free (contents);
+       else
+-       /* Cache the section contents for elf_link_input_bfd.  */
+-       elf_section_data (sec)->this_hdr.contents = contents;
+-      free_contents = NULL;
++       {
++         /* Cache the section contents for elf_link_input_bfd.  */
++         elf_section_data (sec)->this_hdr.contents = contents;
++       }
+     }
+ 
+   if (sdata->relax_count == 0)
+@@ -2507,8 +2503,16 @@ microblaze_elf_relax_section (bfd *abfd,
+   return true;
+ 
+  error_return:
+-  free (free_relocs);
+-  free (free_contents);
++ 
++  if (isymbuf != NULL
++      && symtab_hdr->contents != (unsigned char *) isymbuf)
++    free (isymbuf);
++  if (internal_relocs != NULL
++      && elf_section_data (sec)->relocs != internal_relocs)
++    free (internal_relocs);
++  if (contents != NULL
++      && elf_section_data (sec)->this_hdr.contents != contents)
++    free (contents);
+   free (sdata->relax);
+   sdata->relax = NULL;
+   sdata->relax_count = 0;
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0038-MB-binutils-Upstream-port-issues.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0038-MB-binutils-Upstream-port-issues.patch
new file mode 100644
index 00000000..cfa1a49e
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0038-MB-binutils-Upstream-port-issues.patch
@@ -0,0 +1,99 @@
+From b960fb122b35cb327b9db8fd1bb835899b24d106 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sun, 28 Nov 2021 17:17:15 +0530
+Subject: [PATCH 38/53] MB binutils Upstream port issues.
+
+It's resolving the seg faults with ADDLIK
+Conflicts:
+        bfd/elf64-microblaze.c
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c |  2 +-
+ opcodes/microblaze-dis.c   | 12 ++++++------
+ opcodes/microblaze-opc.h   |  2 +-
+ 3 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index faa458af3a0..686b1a00177 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -404,7 +404,7 @@ const pseudo_typeS md_pseudo_table[] =
+ void
+ md_begin (void)
+ {
+-  const struct op_code_struct * opcode;
++  struct op_code_struct * opcode;
+   const char *prev_name = "";
+ 
+   opcode_hash_control = str_htab_create ();
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index bdc6db79726..d61d6bcfeba 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -153,7 +153,7 @@ get_field_imm16 (struct string_buf *buf, long instr)
+ 
+ static char *
+ get_field_special (struct string_buf *buf, long instr,
+-                  const struct op_code_struct *op)
++                  struct op_code_struct *op)
+ {
+   char *p = strbuf (buf);
+   char *spr;
+@@ -226,11 +226,11 @@ get_field_special (struct string_buf *buf, long instr,
+ static unsigned long
+ read_insn_microblaze (bfd_vma memaddr,
+                      struct disassemble_info *info,
+-                     const struct op_code_struct **opr)
++                     struct op_code_struct **opr)
+ {
+   unsigned char       ibytes[4];
+   int                 status;
+-  const struct op_code_struct *op;
++  struct op_code_struct *op;
+   unsigned long inst;
+ 
+   status = info->read_memory_func (memaddr, ibytes, 4, info);
+@@ -266,7 +266,7 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+   fprintf_ftype print_func = info->fprintf_func;
+   void *stream = info->stream;
+   unsigned long inst, prev_inst;
+-  const struct op_code_struct *op, *pop;
++  struct op_code_struct *op, *pop;
+   int immval = 0;
+   bool immfound = false;
+   static bfd_vma prev_insn_addr = -1;  /* Init the prev insn addr.  */
+@@ -518,7 +518,7 @@ get_insn_microblaze (long inst,
+                     enum microblaze_instr_type *insn_type,
+                     short *delay_slots)
+ {
+-  const struct op_code_struct *op;
++  struct op_code_struct *op;
+   *isunsignedimm = false;
+ 
+   /* Just a linear search of the table.  */
+@@ -560,7 +560,7 @@ microblaze_get_target_address (long inst, bool immfound, int immval,
+                               bool *targetvalid,
+                               bool *unconditionalbranch)
+ {
+-  const struct op_code_struct *op;
++  struct op_code_struct *op;
+   long targetaddr = 0;
+ 
+   *unconditionalbranch = false;
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index f46fc76a94a..9f6d5456701 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -153,7 +153,7 @@
+ 
+ #define MAX_OPCODES 424
+ 
+-const struct op_code_struct
++struct op_code_struct
+ {
+   const char * name;
+   short inst_type;            /* Registers and immediate values involved.  */
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0039-Initial-port-of-core-reading-support-Added-support-f.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0039-Initial-port-of-core-reading-support-Added-support-f.patch
new file mode 100644
index 00000000..06fefe2f
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0039-Initial-port-of-core-reading-support-Added-support-f.patch
@@ -0,0 +1,89 @@
+From ac87f4a6b9e35083a0403f188b61a317b53cfdbc Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 10 Oct 2022 16:37:53 +0530
+Subject: [PATCH 39/53] Initial port of core reading support Added support for
+ reading notes in linux core dumps Support for reading of PRSTATUS and PSINFO
+ information for rebuilding ".reg" sections of core dumps at run time.
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/microblaze-linux-tdep.c | 11 +++++++++++
+ gdb/microblaze-tdep.c       | 37 +++++++++++++++++++++++++++++++++++++
+ 2 files changed, 48 insertions(+)
+
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index f34b0fa9fd4..babc9020f0f 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -193,6 +193,17 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+   set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
+   set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
+ 
++  /* BFD target for core files.  */
++  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++  else
++    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++
++
++  /* Shared library handling.  */
++  set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
++  set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
++
+   /* Enable TLS support.  */
+   set_gdbarch_fetch_tls_load_module_address (gdbarch,
+                                              svr4_fetch_objfile_link_map);
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index f9cb3dfda33..fdea9721b17 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -957,6 +957,43 @@ make_regs (struct gdbarch *arch)
+ }
+ #endif
+ 
++void
++microblaze_supply_gregset (const struct regset *regset,
++                        struct regcache *regcache,
++                        int regnum, const void *gregs)
++{
++  const unsigned int *regs = (const unsigned int *)gregs;
++  if (regnum >= 0)
++    regcache->raw_supply (regnum, regs + regnum);
++
++  if (regnum == -1) {
++    int i;
++
++    for (i = 0; i < 50; i++) {
++      regcache->raw_supply (i, regs + i);
++    }
++  }
++}
++
++
++/* Return the appropriate register set for the core section identified
++   by SECT_NAME and SECT_SIZE.  */
++
++static void
++microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
++                                     iterate_over_regset_sections_cb *cb,
++                                     void *cb_data,
++                                     const struct regcache *regcache)
++{
++  struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch);
++
++  cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data);
++
++  cb(".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
++}
++
++
++
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ {
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch
new file mode 100644
index 00000000..85ae3f02
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch
@@ -0,0 +1,185 @@
+From fc4d292d4154cad199cbe1635790867c98a84fc6 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 14 Mar 2024 10:41:33 +0530
+Subject: [PATCH 40/53] Fix build issues after Xilinx 2023.2 binutils merge
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/bfd-in2.h            | 10 ------
+ gdb/microblaze-tdep.c    | 71 ++++++++++++++--------------------------
+ opcodes/microblaze-dis.c | 10 ------
+ 3 files changed, 25 insertions(+), 66 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 8b2815d7303..cfab5c99b76 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -6456,11 +6456,6 @@ done here - only used for relaxing  */
+  *   +done here - only used for relaxing  */
+     BFD_RELOC_MICROBLAZE_64_PCREL,
+ 
+-/* This is a 64 bit reloc that stores the 32 bit relative
+- *  +value in two words (with an imml instruction).  No relocation is
+- *   +done here - only used for relaxing  */
+-    BFD_RELOC_MICROBLAZE_64,
+-
+ /* This is a 64 bit reloc that stores the 32 bit relative
+  *  +value in two words (with an imml instruction).  No relocation is
+  *   +done here - only used for relaxing  */
+@@ -6486,11 +6481,6 @@ value in two words (with an imml instruction).  The relocation is
+ PC-relative GOT offset  */
+   BFD_RELOC_MICROBLAZE_64_GPC,
+ 
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
+-value in two words (with an imml instruction).  The relocation is
+-PC-relative GOT offset  */
+-  BFD_RELOC_MICROBLAZE_64_GPC,
+-
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  The relocation is
+ GOT offset  */
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index fdea9721b17..d83e508b82b 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -70,6 +70,7 @@ static const char *microblaze_abi_string;
+ static const char *const microblaze_abi_strings[] = {
+   "auto",
+   "m64",
++  NULL
+ };
+ 
+ enum microblaze_abi
+@@ -105,7 +106,7 @@ global_microblaze_abi (void)
+     if (microblaze_abi_strings[i] == microblaze_abi_string)
+       return (enum microblaze_abi) i;
+ 
+-//  internal_error (__FILE__, __LINE__, _("unknown ABI string"));
++  internal_error (__FILE__, __LINE__, _("unknown ABI string"));
+ }
+ 
+ static void
+@@ -894,16 +895,31 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
+ }
+ 
+ static void
+-microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
++microblaze_register_g_packet_guesses (struct gdbarch *gdbarch, enum microblaze_abi abi)
+ {
+ 
+-  register_remote_g_packet_guess (gdbarch,
+-                                 4 * MICROBLAZE_NUM_CORE_REGS,
+-                                 tdesc_microblaze64);
++  if (abi == MICROBLAZE_ABI_M64) 
++    {
++
++      register_remote_g_packet_guess (gdbarch,
++                                     8 * MICROBLAZE_NUM_CORE_REGS,
++                                     tdesc_microblaze64);
++
++      register_remote_g_packet_guess (gdbarch,
++                                     8 * MICROBLAZE_NUM_REGS,
++                                     tdesc_microblaze64_with_stack_protect);
++    } 
++  else 
++    {
++
++      register_remote_g_packet_guess (gdbarch,
++                                     4 * MICROBLAZE_NUM_CORE_REGS,
++                                     tdesc_microblaze);
+ 
+-  register_remote_g_packet_guess (gdbarch,
+-                                 4 * MICROBLAZE_NUM_REGS,
+-                                 tdesc_microblaze64_with_stack_protect);
++      register_remote_g_packet_guess (gdbarch,
++                                     4 * MICROBLAZE_NUM_REGS,
++                                     tdesc_microblaze_with_stack_protect);
++    }
+ }
+ 
+ void
+@@ -957,43 +973,6 @@ make_regs (struct gdbarch *arch)
+ }
+ #endif
+ 
+-void
+-microblaze_supply_gregset (const struct regset *regset,
+-                        struct regcache *regcache,
+-                        int regnum, const void *gregs)
+-{
+-  const unsigned int *regs = (const unsigned int *)gregs;
+-  if (regnum >= 0)
+-    regcache->raw_supply (regnum, regs + regnum);
+-
+-  if (regnum == -1) {
+-    int i;
+-
+-    for (i = 0; i < 50; i++) {
+-      regcache->raw_supply (i, regs + i);
+-    }
+-  }
+-}
+-
+-
+-/* Return the appropriate register set for the core section identified
+-   by SECT_NAME and SECT_SIZE.  */
+-
+-static void
+-microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
+-                                     iterate_over_regset_sections_cb *cb,
+-                                     void *cb_data,
+-                                     const struct regcache *regcache)
+-{
+-  struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch);
+-
+-  cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data);
+-
+-  cb(".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
+-}
+-
+-
+-
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ {
+@@ -1134,7 +1113,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ 
+   set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc);
+ 
+-  //microblaze_register_g_packet_guesses (gdbarch);
++  // microblaze_register_g_packet_guesses (gdbarch, microblaze_abi);
+ 
+   frame_base_set_default (gdbarch, &microblaze_frame_base);
+ 
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index d61d6bcfeba..692c977ac00 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -466,10 +466,6 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+          print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
+                      get_field_r2 (&buf, inst));
+           break;
+-        case INST_TYPE_IMML:
+-         print_func (stream, "\t%s", get_field_imml (&buf, inst));
+-          /* TODO: Also print symbol */
+-         break;
+        case INST_TYPE_RD_IMM15:
+          print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
+                      get_field_imm15 (&buf, inst));
+@@ -484,12 +480,6 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+        case INST_TYPE_RD_IMML:
+          print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst));
+           break;
+-        /* For bit field insns.  */
+-       case INST_TYPE_RD_R1_IMMW_IMMS:
+-         print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst),
+-                  get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+-         break;
+-        /* For bit field insns.  */
+        case INST_TYPE_RD_R1_IMMW_IMMS:
+           print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+             break;
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0041-disable-truncated-register-warning-gdb-remote.c.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0041-disable-truncated-register-warning-gdb-remote.c.patch
new file mode 100644
index 00000000..5a7e4dc3
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0041-disable-truncated-register-warning-gdb-remote.c.patch
@@ -0,0 +1,26 @@
+From 0dc1b1aebeba31dff808a20fcc6444c9acfb99a3 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 14 Mar 2024 15:44:56 +0530
+Subject: [PATCH 41/53] disable truncated register warning (gdb/remote.c)
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/remote.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gdb/remote.c b/gdb/remote.c
+index 72f14e28f54..cb99e5bc7b1 100644
+--- a/gdb/remote.c
++++ b/gdb/remote.c
+@@ -8857,7 +8857,7 @@ remote_target::process_g_packet (struct regcache *regcache)
+          if (rsa->regs[i].pnum == -1)
+            continue;
+ 
+-         if (offset >= sizeof_g_packet)
++         if (offset >= sizeof_g_packet || (offset + reg_size > sizeof_g_packet))
+            rsa->regs[i].in_g_packet = 0;
+          else if (offset + reg_size > sizeof_g_packet)
+            error (_("Truncated register %d in remote 'g' packet"), i);
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch
new file mode 100644
index 00000000..88aefa2f
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch
@@ -0,0 +1,42 @@
+From 81f86c3d6f787a9694e1c95625736f7c921b74df Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 28 Mar 2024 10:20:48 +0530
+Subject: [PATCH 42/53] Fix unresolved conflicts from binutils_2_42_merge
+
+opcodes/microblaze-dis.c
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ opcodes/microblaze-dis.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 692c977ac00..912fa31be79 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -478,11 +478,16 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+        case INST_TYPE_NONE:
+          break;
+        case INST_TYPE_RD_IMML:
+-         print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst));
+-          break;
+-       case INST_TYPE_RD_R1_IMMW_IMMS:
+-          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+-            break;
++         print_func (stream, "\t%s, %s", 
++                 get_field_rd (&buf, inst), get_field_imm16 (&buf, inst));
++         break;
++       case INST_TYPE_RD_R1_IMMW_IMMS:
++         print_func (stream, "\t%s, %s, %s, %s", 
++                 get_field_rd (&buf, inst),
++                 get_field_r1(&buf, inst),
++                 get_field_immw (&buf, inst), 
++                 get_field_imms (&buf, inst));
++         break;
+        /* For tuqula instruction */
+        case INST_TYPE_RD:
+          print_func (stream, "\t%s", get_field_rd (&buf, inst));
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch
new file mode 100644
index 00000000..c5fa72d8
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch
@@ -0,0 +1,177 @@
+From a949ac58b5a3e6cbef03fc431f64052827fc9640 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 28 Mar 2024 10:59:40 +0530
+Subject: [PATCH 43/53] microblaze_gdbarch_init: set microblaze_abi based on
+ wanted_abi and found_abi
+
+Earlier found_abi was declared but not set, instead gdbarch_info info
+was checked every time. Also, microblaze_abi remained undefined for 32-bit
+machines. As a result, gdb would show 64-bit registers when connecting
+to 32-bit targets with all register values garbled (r5 ended up in r2).
+This defect is fixed. found_abi is set from gdbarch_info, microblaze_abi
+is set based on wanted_abi and found_abi. Now upon connecting to a 32-bit
+remote target (mb-qemu) registers have the correct 32-bit size.
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/microblaze-tdep.c | 73 +++++++++++++++++++------------------------
+ 1 file changed, 33 insertions(+), 40 deletions(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index d83e508b82b..6dcdeee76b3 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -116,7 +116,7 @@ show_microblaze_abi (struct ui_file *file,
+                const char *ignored_value)
+ {
+       enum microblaze_abi global_abi = global_microblaze_abi ();
+-      enum microblaze_abi actual_abi = microblaze_abi (target_gdbarch ());
++      enum microblaze_abi actual_abi = microblaze_abi (current_inferior ()->arch ());
+       const char *actual_abi_str = microblaze_abi_strings[actual_abi];
+ 
+ #if 1 
+@@ -203,6 +203,13 @@ microblaze_register_name (struct gdbarch *gdbarch, int regnum)
+ static struct type *
+ microblaze_register_type (struct gdbarch *gdbarch, int regnum)
+ {
++
++  int mb_reg_size = microblaze_abi_regsize(gdbarch);
++
++  if (gdbarch_debug)
++    gdb_printf (gdb_stdlog, "microblaze_register_type: reg_size = %d\n",
++                        mb_reg_size);
++
+   if (regnum == MICROBLAZE_SP_REGNUM)
+     return builtin_type (gdbarch)->builtin_data_ptr;
+ 
+@@ -980,34 +987,38 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   enum microblaze_abi microblaze_abi, found_abi, wanted_abi;
+   const struct target_desc *tdesc = info.target_desc;
+ 
++  /* If there is already a candidate, use it.  */
++  arches = gdbarch_list_lookup_by_info (arches, &info);
++  if ((arches != NULL) && (microblaze_abi != MICROBLAZE_ABI_M64))
++    return arches->gdbarch;
++
+  /* What has the user specified from the command line?  */
+   wanted_abi = global_microblaze_abi ();
+   if (gdbarch_debug)
+     gdb_printf (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n",
+                         wanted_abi);
++
++  found_abi = MICROBLAZE_ABI_AUTO;
++
++  if (info.bfd_arch_info->mach == bfd_mach_microblaze64) 
++    found_abi = MICROBLAZE_ABI_M64;
++
+   if (wanted_abi != MICROBLAZE_ABI_AUTO)
+     microblaze_abi = wanted_abi;
+-
+-  /* If there is already a candidate, use it.  */
+-  arches = gdbarch_list_lookup_by_info (arches, &info);
+-  if ((arches != NULL) && (microblaze_abi != MICROBLAZE_ABI_M64))
+-    return arches->gdbarch;
++  else
++    microblaze_abi = found_abi;
+ 
+   if (microblaze_abi == MICROBLAZE_ABI_M64)
+     {
+-          tdesc = tdesc_microblaze64;
+-          reg_size = 8;
++      tdesc = tdesc_microblaze64;
++      reg_size = 8;
+     }
+-  if (tdesc == NULL)
++  else 
+     {
+-      if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) 
+-        {
+-         tdesc = tdesc_microblaze64;
+-          reg_size = 8;
+-       }
+-      else
+-       tdesc = tdesc_microblaze;
++      tdesc = tdesc_microblaze;
++      reg_size = 4;
+     }
++
+   /* Check any target description for validity.  */
+   if (tdesc_has_registers (tdesc))
+     {
+@@ -1015,7 +1026,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+       int valid_p;
+       int i;
+ 
+-      if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64))
++      if (microblaze_abi == MICROBLAZE_ABI_M64)
+         feature = tdesc_find_feature (tdesc,
+                                     "org.gnu.gdb.microblaze64.core");
+       else
+@@ -1029,7 +1040,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+       for (i = 0; i < MICROBLAZE_NUM_REGS; i++)
+         valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), i,
+                                             microblaze_register_names[i]);
+-      if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64))
++      if (microblaze_abi == MICROBLAZE_ABI_M64)
+         feature = tdesc_find_feature (tdesc,
+                                     "org.gnu.gdb.microblaze64.stack-protect");
+       else
+@@ -1075,15 +1086,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   
+   /* Register set.  
+   make_regs (gdbarch); */
+-  switch (info.bfd_arch_info->mach)
+-    {
+-    case bfd_mach_microblaze64:
+-      set_gdbarch_ptr_bit (gdbarch, 64);
+-    break;
+-    }
+-  if(microblaze_abi == MICROBLAZE_ABI_M64)
++  if (microblaze_abi == MICROBLAZE_ABI_M64)
+     set_gdbarch_ptr_bit (gdbarch, 64);
+-  
++  else
++    set_gdbarch_ptr_bit (gdbarch, 32);
++
+   /* Map Dwarf2 registers to GDB registers.  */
+   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum);
+ 
+@@ -1105,8 +1112,6 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+                                       microblaze_breakpoint::bp_from_kind);
+ //  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
+ 
+-//  set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+-
+   set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+ 
+   set_gdbarch_frame_args_skip (gdbarch, 8);
+@@ -1145,9 +1150,6 @@ _initialize_microblaze_tdep ()
+ 
+   gdbarch_register (bfd_arch_microblaze, microblaze_gdbarch_init);
+ 
+-// static struct cmd_list_element *setmicroblazecmdlist = NULL;
+-// static struct cmd_list_element *showmicroblazecmdlist = NULL;
+-
+   /* Add root prefix command for all "set microblaze"/"show microblaze" commands.  */
+  
+   add_setshow_prefix_cmd ("microblaze", no_class,
+@@ -1155,15 +1157,6 @@ _initialize_microblaze_tdep ()
+                         _("Various microblaze specific commands."),
+                         &setmicroblazecmdlist,&showmicroblazecmdlist,
+                         &setlist,&showlist);
+-#if 0
+-  add_prefix_cmd ("microblaze", no_class, set_microblaze_command,
+-                  _("Various microblaze specific commands."),
+-                  &setmicroblazecmdlist, "set microblaze ", 0, &setlist);
+-
+-  add_prefix_cmd ("microblaze", no_class, show_microblaze_command,
+-                  _("Various microblaze specific commands."),
+-                  &showmicroblazecmdlist, "show microblaze ", 0, &showlist);
+-#endif
+ 
+   /* Allow the user to override the ABI.  */
+   add_setshow_enum_cmd ("abi", class_obscure, microblaze_abi_strings,
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch
new file mode 100644
index 00000000..a22fdb26
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch
@@ -0,0 +1,32 @@
+From 70d94c8a627a91b7a59d99abf5c137f650a687d3 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 28 Mar 2024 11:36:32 +0530
+Subject: [PATCH 44/53] Start bfd_mach_microblaze values from 0 (0,1) instead
+ of (1,2)
+
+Before 64-bit support there was only bfd_mach_microblaze (implicitly set to 0),
+setting microblaze_mach_microblaze64 to 1
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/archures.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/bfd/archures.c b/bfd/archures.c
+index b9db26627ea..604e65b7256 100644
+--- a/bfd/archures.c
++++ b/bfd/archures.c
+@@ -515,8 +515,8 @@ DESCRIPTION
+ .  bfd_arch_lm32,      {* Lattice Mico32.  *}
+ .#define bfd_mach_lm32         1
+ .  bfd_arch_microblaze,{* Xilinx MicroBlaze.  *}
+-.#define bfd_mach_microblaze   1
+-.#define bfd_mach_microblaze64 2
++.#define bfd_mach_microblaze   0
++.#define bfd_mach_microblaze64 1
+ .  bfd_arch_kvx,        {* Kalray VLIW core of the MPPA processor family *}
+ .#define bfd_mach_kv3_unknown       0
+ .#define bfd_mach_kv3_1             1
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch
new file mode 100644
index 00000000..a9f96637
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch
@@ -0,0 +1,61 @@
+From 8fd6902a818f28422bd98b18ff3f0fe9b872e5cf Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 28 Mar 2024 15:37:11 +0530
+Subject: [PATCH 45/53] Fix build issues - bfd/reloc.c add missing relocs used
+ elsewhere
+
+        BFD_RELOC_MICROBLAZE_EA64
+        BFD_RELOC_MICROBLAZE_64_GPC
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/reloc.c | 16 +++++++++++-----
+ 1 file changed, 11 insertions(+), 5 deletions(-)
+
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index b6c9c22a0be..86ca1283582 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6637,13 +6637,19 @@ ENUMDOC
+   This is a 64 bit reloc that stores 64-bit thread pointer relative offset
+   to two words (uses imml instruction).
+ ENUM
+-BFD_RELOC_MICROBLAZE_64,
++BFD_RELOC_MICROBLAZE_64
+ ENUMDOC
+  This is a 64 bit reloc that stores the 64 bit pc relative
+  value in two words (with an imml instruction).  No relocation is
+  done here - only used for relaxing
+ ENUM
+-BFD_RELOC_MICROBLAZE_64_PCREL,
++BFD_RELOC_MICROBLAZE_EA64
++ENUMDOC
++ This is a 64 bit reloc that stores the 64 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
++ENUM
++BFD_RELOC_MICROBLAZE_64_PCREL
+ ENUMDOC
+  This is a 32 bit reloc that stores the 32 bit pc relative
+  value in two words (with an imml instruction).  No relocation is
+@@ -6686,13 +6692,13 @@ ENUMDOC
+   two words (with an imm instruction).  No relocation is done here -
+   only used for relaxing.
+ ENUM
+-BFD_RELOC_MICROBLAZE_64_PCREL,
++BFD_RELOC_MICROBLAZE_64_GOTPC
+ ENUMDOC
+- This is a 32 bit reloc that stores the 32 bit pc relative
++ This is a 64 bit reloc that stores the 32 bit pc relative
+  value in two words (with an imml instruction).  No relocation is
+  done here - only used for relaxing
+ ENUM
+-  BFD_RELOC_MICROBLAZE_64_GOTPC
++  BFD_RELOC_MICROBLAZE_64_GPC
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imml instruction).  No relocation is
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch
new file mode 100644
index 00000000..3e6be541
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch
@@ -0,0 +1,116 @@
+From 84bb72aa81dddd5f21ac49ddf7b38bce74942cdf Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 28 Mar 2024 15:47:56 +0530
+Subject: [PATCH 46/53] Regenerate - bfd/bfd-in2.h bfd/libbfd.h
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/bfd-in2.h | 70 +++++++++++++++++++++++++--------------------------
+ 1 file changed, 35 insertions(+), 35 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index cfab5c99b76..96949605e50 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -1771,8 +1771,8 @@ enum bfd_architecture
+   bfd_arch_lm32,      /* Lattice Mico32.  */
+ #define bfd_mach_lm32          1
+   bfd_arch_microblaze,/* Xilinx MicroBlaze.  */
+-#define bfd_mach_microblaze    1
+-#define bfd_mach_microblaze64  2
++#define bfd_mach_microblaze    0
++#define bfd_mach_microblaze64  1
+   bfd_arch_kvx,        /* Kalray VLIW core of the MPPA processor family */
+ #define bfd_mach_kv3_unknown       0
+ #define bfd_mach_kv3_1             1
+@@ -6426,8 +6426,23 @@ enum bfd_reloc_code_real
+   /* Address of a GOT entry.  */
+   BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT,
+ 
+-  /* This is a 32 bit reloc for the microblaze that stores the low 16
+-     bits of a value.  */
++  /* This is a 64 bit reloc that stores the 64 bit pc relative
++  value in two words (with an imml instruction).  No relocation is
++  done here - only used for relaxing  */
++  BFD_RELOC_MICROBLAZE_64,
++
++  /* This is a 64 bit reloc that stores the 64 bit pc relative
++  value in two words (with an imml instruction).  No relocation is
++  done here - only used for relaxing  */
++  BFD_RELOC_MICROBLAZE_EA64,
++
++  /* This is a 32 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imml instruction).  No relocation is
++  done here - only used for relaxing  */
++  BFD_RELOC_MICROBLAZE_64_PCREL,
++
++  /* This is a 32 bit reloc for the microblaze that stores the
++  low 16 bits of a value  */
+   BFD_RELOC_MICROBLAZE_32_LO,
+ 
+   /* This is a 32 bit pc-relative reloc for the microblaze that stores
+@@ -6446,44 +6461,29 @@ enum bfd_reloc_code_real
+      the form "Symbol Op Symbol".  */
+   BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
+ 
+-/* This is a 32 bit reloc that stores the 32 bit pc relative
+-value in two words (with an imm instruction).  No relocation is
+-done here - only used for relaxing  */
++  /* This is a 32 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imm instruction).  No relocation is
++  done here - only used for relaxing  */
+   BFD_RELOC_MICROBLAZE_32_NONE,
+ 
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
+- *  +value in two words (with an imml instruction).  No relocation is
+- *   +done here - only used for relaxing  */
+-    BFD_RELOC_MICROBLAZE_64_PCREL,
+-
+-/* This is a 64 bit reloc that stores the 32 bit relative
+- *  +value in two words (with an imml instruction).  No relocation is
+- *   +done here - only used for relaxing  */
+-    BFD_RELOC_MICROBLAZE_EA64,
+-
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
+- *  +value in two words (with an imm instruction).  No relocation is
+- *   +done here - only used for relaxing  */
+-    BFD_RELOC_MICROBLAZE_64_NONE,
+-
+-  /* This is a 64 bit reloc that stores the 32 bit pc relative value in
+-     two words (with an imm instruction).  No relocation is done here
+-     only used for relaxing  */
+-    BFD_RELOC_MICROBLAZE_64,
++  /* This is a 32 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imml instruction).  No relocation is
++  done here - only used for relaxing  */
++  BFD_RELOC_MICROBLAZE_64_NONE,
+ 
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
+-value in two words (with an imm instruction).  The relocation is
+-PC-relative GOT offset  */
++  /* This is a 64 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imm instruction).  The relocation is
++  PC-relative GOT offset  */
+   BFD_RELOC_MICROBLAZE_64_GOTPC,
+ 
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
+-value in two words (with an imml instruction).  The relocation is
+-PC-relative GOT offset  */
++  /* This is a 64 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imml instruction).  No relocation is
++  done here - only used for relaxing  */
+   BFD_RELOC_MICROBLAZE_64_GPC,
+ 
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
+-value in two words (with an imm instruction).  The relocation is
+-GOT offset  */
++  /* This is a 64 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imm instruction).  The relocation is
++  GOT offset  */
+   BFD_RELOC_MICROBLAZE_64_GOT,
+ 
+   /* This is a 64 bit reloc that stores the 32 bit pc relative value in
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch
new file mode 100644
index 00000000..bf82b0ef
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch
@@ -0,0 +1,32 @@
+From 8deda21efd527564a262dc07a519f8bd03095b3c Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 28 Mar 2024 16:32:22 +0530
+Subject: [PATCH 47/53] gdb/remote.c - revert earlier change to
+ process_g_packet
+
+When connecting to remote target, gdb (microblaze-xilinx-elf) was
+generating Truncated register 29 error when parsing the g packet,
+workaround added being reverted.
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/remote.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gdb/remote.c b/gdb/remote.c
+index cb99e5bc7b1..72f14e28f54 100644
+--- a/gdb/remote.c
++++ b/gdb/remote.c
+@@ -8857,7 +8857,7 @@ remote_target::process_g_packet (struct regcache *regcache)
+          if (rsa->regs[i].pnum == -1)
+            continue;
+ 
+-         if (offset >= sizeof_g_packet || (offset + reg_size > sizeof_g_packet))
++         if (offset >= sizeof_g_packet)
+            rsa->regs[i].in_g_packet = 0;
+          else if (offset + reg_size > sizeof_g_packet)
+            error (_("Truncated register %d in remote 'g' packet"), i);
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch
new file mode 100644
index 00000000..6c40a7e4
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch
@@ -0,0 +1,465 @@
+From e372266dde792b03fb1754769a9615c818336171 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Mon, 1 Apr 2024 16:21:28 +0530
+Subject: [PATCH 48/53] Fix build issues after Xilinx 2023.2 binutils patch
+ merge
+
+binutils/readelf.c - duplicate case statement
+gas/config/tc-microblaze.c - Missing , between array elements
+gas/config/tc-microblaze.c - A whole hunk ended up in wrong function/switch
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/libbfd.h               |   6 +-
+ binutils/readelf.c         |   5 -
+ gas/config/tc-microblaze.c | 375 +++++++++++++++++++------------------
+ 3 files changed, 192 insertions(+), 194 deletions(-)
+
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index 7a3e558d70a..5f78d16db18 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -2998,6 +2998,9 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+   "BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21",
+   "BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12",
+   "BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT",
++  "BFD_RELOC_MICROBLAZE_64",
++  "BFD_RELOC_MICROBLAZE_EA64",
++  "BFD_RELOC_MICROBLAZE_64_PCREL",
+   "BFD_RELOC_MICROBLAZE_32_LO",
+   "BFD_RELOC_MICROBLAZE_32_LO_PCREL",
+   "BFD_RELOC_MICROBLAZE_32_ROSDA",
+@@ -3006,13 +3009,12 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+   "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
++  "BFD_RELOC_MICROBLAZE_64_GPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+   "BFD_RELOC_MICROBLAZE_64_PLT",
+   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
+   "BFD_RELOC_MICROBLAZE_32_GOTOFF",
+   "BFD_RELOC_MICROBLAZE_COPY",
+-  "BFD_RELOC_MICROBLAZE_64",
+-  "BFD_RELOC_MICROBLAZE_64_PCREL",
+   "BFD_RELOC_MICROBLAZE_64_TLS",
+   "BFD_RELOC_MICROBLAZE_64_TLSGD",
+   "BFD_RELOC_MICROBLAZE_64_TLSLD",
+diff --git a/binutils/readelf.c b/binutils/readelf.c
+index 3ca9f3697d1..5e4ad6ea6ad 100644
+--- a/binutils/readelf.c
++++ b/binutils/readelf.c
+@@ -15288,11 +15288,6 @@ is_8bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
+              || reloc_type == 9 /* R_MICROBLAZE_64_NONE.  */);
+     default:
+       return false;
+-    /* REVISIT microblaze-binutils-merge */
+-    case EM_MICROBLAZE:
+-      return reloc_type == 33 /* R_MICROBLAZE_32_NONE.  */
+-             || reloc_type == 0 /* R_MICROBLAZE_NONE.  */
+-             || reloc_type == 9; /* R_MICROBLAZE_64_NONE.  */
+     }
+ }
+ 
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 686b1a00177..d3d1e334bb5 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -118,7 +118,7 @@ const relax_typeS md_relax_table[] =
+   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 15: TLSGOTTPREL_OFFSET.  */
+   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 16: TLSTPREL_OFFSET.  */
+   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 17: TEXT_OFFSET.  */
+-  { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }   /* 18: TEXT_PC_OFFSET.  */
++  { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 18: TEXT_PC_OFFSET.  */
+   { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 },   /* 19: DEFINED_64_OFFSET.  */
+   { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE*2, 0 }   /* 20: DEFINED_64_PC_OFFSET.  */
+ };
+@@ -2263,6 +2263,193 @@ md_assemble (char * str)
+       inst |= (immed << IMM_MBAR);
+       break;
+ 
++    /* For 64-bit instructions */
++    case INST_TYPE_RD_R1_IMML:
++      if (strcmp (op_end, ""))
++       op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
++      else
++       {
++          as_fatal (_("Error in statement syntax"));
++          reg1 = 0;
++        }
++      if (strcmp (op_end, ""))
++       op_end = parse_reg (op_end + 1, &reg2);  /* Get r1.  */
++      else
++       {
++          as_fatal (_("Error in statement syntax"));
++          reg2 = 0;
++        }
++      if (strcmp (op_end, ""))
++       op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++      else
++       as_fatal (_("Error in statement syntax"));
++
++      /* Check for spl registers.  */
++      if (check_spl_reg (& reg1))
++       as_fatal (_("Cannot use special register with this instruction"));
++      if (check_spl_reg (& reg2))
++       as_fatal (_("Cannot use special register with this instruction"));
++
++      if (exp.X_op != O_constant)
++       {
++         char *opc = NULL;
++         //char *opc = str_microblaze_64;
++         relax_substateT subtype;
++
++         if (exp.X_md != 0)
++           subtype = get_imm_otype(exp.X_md);
++         else
++           subtype = opcode->inst_offset_type;
++
++         output = frag_var (rs_machine_dependent,
++                            isize * 2, /* maxm of 2 words.  */
++                            isize * 2, /* minm of 2 words.  */
++                            subtype,   /* PC-relative or not.  */
++                            exp.X_add_symbol,
++                            exp.X_add_number,
++                            (char *) opc);
++         immedl = 0L;
++        }
++      else
++       {
++         output = frag_more (isize);
++         immedl = exp.X_add_number;
++         if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887)
++            {
++             opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++             if (opcode1 == NULL)
++             {
++              as_bad (_("unknown opcode \"%s\""), "imml");
++              return;
++             }
++          inst1 = opcode1->bit_sequence;
++          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++        }
++           else {
++           opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++           opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++       if (opcode2 == NULL || opcode1 == NULL)
++            {
++              as_bad (_("unknown opcode \"%s\""), "imml");
++              return;
++            }
++          inst1 = opcode2->bit_sequence;
++          inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++          inst1 = opcode1->bit_sequence;
++          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++        }
++        }
++
++      inst |= (reg1 << RD_LOW) & RD_MASK;
++      inst |= (reg2 << RA_LOW) & RA_MASK;
++      inst |= (immedl << IMM_LOW) & IMM_MASK;
++      break;
++
++    case INST_TYPE_R1_IMML:
++      if (strcmp (op_end, ""))
++        op_end = parse_reg (op_end + 1, &reg1);  /* Get r1.  */
++      else
++       {
++          as_fatal (_("Error in statement syntax"));
++          reg1 = 0;
++        }
++      if (strcmp (op_end, ""))
++        op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++      else
++        as_fatal (_("Error in statement syntax"));
++
++      /* Check for spl registers.  */
++      if (check_spl_reg (&reg1))
++        as_fatal (_("Cannot use special register with this instruction"));
++
++      if (exp.X_op != O_constant)
++       {
++         //char *opc = NULL;
++          char *opc = str_microblaze_64;
++          relax_substateT subtype;
++
++         if (exp.X_md != 0)
++           subtype = get_imm_otype(exp.X_md);
++         else
++           subtype = opcode->inst_offset_type;
++
++         output = frag_var (rs_machine_dependent,
++                            isize * 2, /* maxm of 2 words.  */
++                            isize * 2, /* minm of 2 words.  */
++                            subtype,   /* PC-relative or not.  */
++                            exp.X_add_symbol,
++                            exp.X_add_number,
++                            (char *) opc);
++         immedl = 0L;
++       }
++      else
++       {
++          output = frag_more (isize);
++          immedl = exp.X_add_number;
++          if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887)
++             {
++            opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++           if (opcode1 == NULL)
++            {
++              as_bad (_("unknown opcode \"%s\""), "imml");
++              return;
++            }
++          inst1 = opcode1->bit_sequence;
++          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++          }
++           else {
++           opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++           opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
++       if (opcode2 == NULL || opcode1 == NULL)
++            {
++              as_bad (_("unknown opcode \"%s\""), "imml");
++              return;
++            }
++          inst1 = opcode2->bit_sequence;
++          inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++          inst1 = opcode1->bit_sequence;
++          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++        }
++        }
++
++      inst |= (reg1 << RA_LOW) & RA_MASK;
++      inst |= (immedl << IMM_LOW) & IMM_MASK;
++      break;
++
++    case INST_TYPE_IMML:
++      as_fatal (_("An IMML instruction should not be present in the .s file"));
++      break;
++
+     default:
+       as_fatal (_("unimplemented opcode \"%s\""), name);
+     }
+@@ -3177,192 +3364,6 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+     case BFD_RELOC_MICROBLAZE_64_TEXTREL:
+       code = fixp->fx_r_type;
+       break;
+-    /* For 64-bit instructions */
+-    case INST_TYPE_RD_R1_IMML:
+-      if (strcmp (op_end, ""))
+-       op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
+-      else
+-       {
+-          as_fatal (_("Error in statement syntax"));
+-          reg1 = 0;
+-        }
+-      if (strcmp (op_end, ""))
+-       op_end = parse_reg (op_end + 1, &reg2);  /* Get r1.  */
+-      else
+-       {
+-          as_fatal (_("Error in statement syntax"));
+-          reg2 = 0;
+-        }
+-      if (strcmp (op_end, ""))
+-       op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
+-      else
+-       as_fatal (_("Error in statement syntax"));
+-
+-      /* Check for spl registers.  */
+-      if (check_spl_reg (& reg1))
+-       as_fatal (_("Cannot use special register with this instruction"));
+-      if (check_spl_reg (& reg2))
+-       as_fatal (_("Cannot use special register with this instruction"));
+-
+-      if (exp.X_op != O_constant)
+-       {
+-         char *opc = NULL;
+-         //char *opc = str_microblaze_64;
+-         relax_substateT subtype;
+-
+-         if (exp.X_md != 0)
+-           subtype = get_imm_otype(exp.X_md);
+-         else
+-           subtype = opcode->inst_offset_type;
+-
+-         output = frag_var (rs_machine_dependent,
+-                            isize * 2, /* maxm of 2 words.  */
+-                            isize * 2, /* minm of 2 words.  */
+-                            subtype,   /* PC-relative or not.  */
+-                            exp.X_add_symbol,
+-                            exp.X_add_number,
+-                            (char *) opc);
+-         immedl = 0L;
+-        }
+-      else
+-       {
+-         output = frag_more (isize);
+-         immedl = exp.X_add_number;
+-         if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887)
+-            {
+-             opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
+-             if (opcode1 == NULL)
+-             {
+-              as_bad (_("unknown opcode \"%s\""), "imml");
+-              return;
+-             }
+-          inst1 = opcode1->bit_sequence;
+-          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+-          output[0] = INST_BYTE0 (inst1);
+-          output[1] = INST_BYTE1 (inst1);
+-          output[2] = INST_BYTE2 (inst1);
+-          output[3] = INST_BYTE3 (inst1);
+-          output = frag_more (isize);
+-        }
+-           else {
+-           opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
+-           opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
+-       if (opcode2 == NULL || opcode1 == NULL)
+-            {
+-              as_bad (_("unknown opcode \"%s\""), "imml");
+-              return;
+-            }
+-          inst1 = opcode2->bit_sequence;
+-          inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
+-          output[0] = INST_BYTE0 (inst1);
+-          output[1] = INST_BYTE1 (inst1);
+-          output[2] = INST_BYTE2 (inst1);
+-          output[3] = INST_BYTE3 (inst1);
+-          output = frag_more (isize);
+-          inst1 = opcode1->bit_sequence;
+-          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+-          output[0] = INST_BYTE0 (inst1);
+-          output[1] = INST_BYTE1 (inst1);
+-          output[2] = INST_BYTE2 (inst1);
+-          output[3] = INST_BYTE3 (inst1);
+-          output = frag_more (isize);
+-        }
+-        }
+-
+-      inst |= (reg1 << RD_LOW) & RD_MASK;
+-      inst |= (reg2 << RA_LOW) & RA_MASK;
+-      inst |= (immedl << IMM_LOW) & IMM_MASK;
+-      break;
+-
+-    case INST_TYPE_R1_IMML:
+-      if (strcmp (op_end, ""))
+-        op_end = parse_reg (op_end + 1, &reg1);  /* Get r1.  */
+-      else
+-       {
+-          as_fatal (_("Error in statement syntax"));
+-          reg1 = 0;
+-        }
+-      if (strcmp (op_end, ""))
+-        op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
+-      else
+-        as_fatal (_("Error in statement syntax"));
+-
+-      /* Check for spl registers.  */
+-      if (check_spl_reg (&reg1))
+-        as_fatal (_("Cannot use special register with this instruction"));
+-
+-      if (exp.X_op != O_constant)
+-       {
+-         //char *opc = NULL;
+-          char *opc = str_microblaze_64;
+-          relax_substateT subtype;
+-
+-         if (exp.X_md != 0)
+-           subtype = get_imm_otype(exp.X_md);
+-         else
+-           subtype = opcode->inst_offset_type;
+-
+-         output = frag_var (rs_machine_dependent,
+-                            isize * 2, /* maxm of 2 words.  */
+-                            isize * 2, /* minm of 2 words.  */
+-                            subtype,   /* PC-relative or not.  */
+-                            exp.X_add_symbol,
+-                            exp.X_add_number,
+-                            (char *) opc);
+-         immedl = 0L;
+-       }
+-      else
+-       {
+-          output = frag_more (isize);
+-          immedl = exp.X_add_number;
+-          if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887)
+-             {
+-            opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
+-           if (opcode1 == NULL)
+-            {
+-              as_bad (_("unknown opcode \"%s\""), "imml");
+-              return;
+-            }
+-          inst1 = opcode1->bit_sequence;
+-          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+-          output[0] = INST_BYTE0 (inst1);
+-          output[1] = INST_BYTE1 (inst1);
+-          output[2] = INST_BYTE2 (inst1);
+-          output[3] = INST_BYTE3 (inst1);
+-          output = frag_more (isize);
+-          }
+-           else {
+-           opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
+-           opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
+-       if (opcode2 == NULL || opcode1 == NULL)
+-            {
+-              as_bad (_("unknown opcode \"%s\""), "imml");
+-              return;
+-            }
+-          inst1 = opcode2->bit_sequence;
+-          inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
+-          output[0] = INST_BYTE0 (inst1);
+-          output[1] = INST_BYTE1 (inst1);
+-          output[2] = INST_BYTE2 (inst1);
+-          output[3] = INST_BYTE3 (inst1);
+-          output = frag_more (isize);
+-          inst1 = opcode1->bit_sequence;
+-          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+-          output[0] = INST_BYTE0 (inst1);
+-          output[1] = INST_BYTE1 (inst1);
+-          output[2] = INST_BYTE2 (inst1);
+-          output[3] = INST_BYTE3 (inst1);
+-          output = frag_more (isize);
+-        }
+-        }
+-
+-      inst |= (reg1 << RA_LOW) & RA_MASK;
+-      inst |= (immedl << IMM_LOW) & IMM_MASK;
+-      break;
+-
+-    case INST_TYPE_IMML:
+-      as_fatal (_("An IMML instruction should not be present in the .s file"));
+-      break;
+ 
+     default:
+       switch (F (fixp->fx_size, fixp->fx_pcrel))
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0049-When-unwinding-pc-value-adjust-return-pc-value.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0049-When-unwinding-pc-value-adjust-return-pc-value.patch
new file mode 100644
index 00000000..f7869532
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0049-When-unwinding-pc-value-adjust-return-pc-value.patch
@@ -0,0 +1,92 @@
+From 21527b2edc1359417cc7978558167ef9c8c92afd Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Wed, 1 May 2024 11:12:32 +0530
+Subject: [PATCH 49/53] When unwinding pc value, adjust return pc value
+
+A call (branch and link) instruction can include a delay slot, the
+value of pc stored in the link register for Microblaze architecture
+is the pc value corresponding to last executed instruction (call)
+in the caller. The return instruction (branch reg) includes an
+offset of 8 so that when function returns execution continues from
+the address at : link register + 8, as the instruction in delay slot
+(link register + 4) is already executed at the time of call.
+
+Handle this by adjusting pc value during unwind-pc.
+
+Basically restoring code to do this that seems to have been removed
+as part of a gdb patch (gdb patch #8, Xilinx Yocto 2023.2)
+
+That patch caused hundreds of regressions in gdb testuite, including
+gdb.base/advance.exp, which is now fixed.
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/microblaze-tdep.c | 24 ++++++++++++++++++------
+ 1 file changed, 18 insertions(+), 6 deletions(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 6dcdeee76b3..2507cfe540f 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -523,6 +523,12 @@ microblaze_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame)
+ {
+   CORE_ADDR pc;
+   pc=frame_unwind_register_unsigned (next_frame, MICROBLAZE_PC_REGNUM);
++  /* For sentinel frame, return address is actual PC.  For other frames,
++     return address is pc+8.  This is a workaround because gcc does not
++     generate correct return address in CIE.  */
++  if (frame_relative_level (next_frame) >= 0)
++    pc = pc + 8;
++  microblaze_debug ("unwind pc = 0x%x\n", (int) pc);
+   return pc;
+ }
+ 
+@@ -615,6 +621,7 @@ microblaze_frame_prev_register (frame_info_ptr this_frame,
+   struct microblaze_frame_cache *cache =
+     microblaze_frame_cache (this_frame, this_cache);
+ 
++#if 1
+ if ((regnum == MICROBLAZE_SP_REGNUM &&
+       cache->register_offsets[MICROBLAZE_SP_REGNUM])
+       || (regnum == MICROBLAZE_FP_REGNUM &&
+@@ -625,15 +632,22 @@ if ((regnum == MICROBLAZE_SP_REGNUM &&
+ 
+ if (regnum == MICROBLAZE_PC_REGNUM)
+ {
+-      regnum = 15;
++      regnum = MICROBLAZE_PREV_PC_REGNUM;
++
++      microblaze_debug ("prev pc is r15 @ frame offset 0x%x\n",
++                         (int) cache->register_offsets[regnum] );
++
+       return frame_unwind_got_memory (this_frame, regnum,
+                                       cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM]);
+-
+ }
++
+ if (regnum == MICROBLAZE_SP_REGNUM)
+         regnum = 1;
+-#if 0
+ 
++  return trad_frame_get_prev_register (this_frame, cache->saved_regs,
++ regnum);
++
++#else
+   if (cache->frameless_p)
+     {
+       if (regnum == MICROBLAZE_PC_REGNUM)
+@@ -646,9 +660,7 @@ if (regnum == MICROBLAZE_SP_REGNUM)
+   else
+     return trad_frame_get_prev_register (this_frame, cache->saved_regs,
+                                         regnum);
+-#endif
+-  return trad_frame_get_prev_register (this_frame, cache->saved_regs,
+-                                       regnum); 
++#endif 
+ }
+ 
+ static const struct frame_unwind microblaze_frame_unwind =
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0050-info-reg-pc-does-not-print-symbolic-value.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0050-info-reg-pc-does-not-print-symbolic-value.patch
new file mode 100644
index 00000000..c9bca41d
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0050-info-reg-pc-does-not-print-symbolic-value.patch
@@ -0,0 +1,116 @@
+From 54a6eedd59d70a80be5dc8b4a5abe642113ea291 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 9 May 2024 11:30:22 +0530
+Subject: [PATCH 50/53] info reg pc does not print symbolic value
+
+Problem - Test gdb.base/pc-fp.exp fails
+Fix - Change feature/microblaze-core.xml add type=code_ptr for pc
+
+Files changed
+        features/microblaze-core.xml
+        features/microblaze.c (generated)
+        features/microblaze-with-stack-protect.c (generated)
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/features/microblaze-core.xml             |  4 ++--
+ gdb/features/microblaze-with-stack-protect.c | 10 ++++++----
+ gdb/features/microblaze.c                    |  8 ++++----
+ 3 files changed, 12 insertions(+), 10 deletions(-)
+
+diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml
+index 4d77d9d898f..f49d048fc73 100644
+--- a/gdb/features/microblaze-core.xml
++++ b/gdb/features/microblaze-core.xml
+@@ -8,7 +8,7 @@
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze.core">
+   <reg name="r0" bitsize="32" regnum="0"/>
+-  <reg name="r1" bitsize="32"/>
++  <reg name="r1" bitsize="32" type="data_ptr"/>
+   <reg name="r2" bitsize="32"/>
+   <reg name="r3" bitsize="32"/>
+   <reg name="r4" bitsize="32"/>
+@@ -39,7 +39,7 @@
+   <reg name="r29" bitsize="32"/>
+   <reg name="r30" bitsize="32"/>
+   <reg name="r31" bitsize="32"/>
+-  <reg name="rpc" bitsize="32"/>
++  <reg name="rpc" bitsize="32" type="code_ptr"/>
+   <reg name="rmsr" bitsize="32"/>
+   <reg name="rear" bitsize="32"/>
+   <reg name="resr" bitsize="32"/>
+diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c
+index 8ab9565a047..95e3eed1a4e 100644
+--- a/gdb/features/microblaze-with-stack-protect.c
++++ b/gdb/features/microblaze-with-stack-protect.c
+@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+ 
+   feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core");
+   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
+   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
+@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
+   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
+@@ -70,10 +70,12 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+   tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+-
+-  feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.stack-protect");
+   tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int");
+ 
++  feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.stack-protect");
++  tdesc_create_reg (feature, "slr", 59, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "shr", 60, 1, NULL, 32, "int");
++
+   tdesc_microblaze_with_stack_protect = result.release ();
+ }
+diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c
+index ed12e5bcfd2..ff4865b2acc 100644
+--- a/gdb/features/microblaze.c
++++ b/gdb/features/microblaze.c
+@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void)
+ 
+   feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core");
+   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
+   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
+@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void)
+   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
+   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
+@@ -70,8 +70,8 @@ initialize_tdesc_microblaze (void)
+   tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
+-  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int");
+ 
+   tdesc_microblaze = result.release ();
+ }
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0051-Wrong-target-description-accepted-by-microblaze-arch.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0051-Wrong-target-description-accepted-by-microblaze-arch.patch
new file mode 100644
index 00000000..65993021
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0051-Wrong-target-description-accepted-by-microblaze-arch.patch
@@ -0,0 +1,51 @@
+From 80f3d1ca2ece1ef143f00365b938e0d0b575d239 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 9 May 2024 11:34:04 +0530
+Subject: [PATCH 51/53] Wrong target description accepted by microblaze
+ architecture
+
+Fix - Modify microblaze_gdbarch_init, set tdesc only when it is NULL
+
+Files changed - gdb/microblaze-tdep.c
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/microblaze-tdep.c | 21 ++++++++++++---------
+ 1 file changed, 12 insertions(+), 9 deletions(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 2507cfe540f..cc80e4f0e6b 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -1020,15 +1020,18 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   else
+     microblaze_abi = found_abi;
+ 
+-  if (microblaze_abi == MICROBLAZE_ABI_M64)
+-    {
+-      tdesc = tdesc_microblaze64;
+-      reg_size = 8;
+-    }
+-  else 
+-    {
+-      tdesc = tdesc_microblaze;
+-      reg_size = 4;
++  if (tdesc == NULL) 
++    { 
++       if (microblaze_abi == MICROBLAZE_ABI_M64)
++         {
++           tdesc = tdesc_microblaze64;
++           reg_size = 8;
++         }
++       else 
++         {
++           tdesc = tdesc_microblaze;
++           reg_size = 4;
++         }
+     }
+ 
+   /* Check any target description for validity.  */
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0052-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0052-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch
new file mode 100644
index 00000000..f358e45e
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0052-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch
@@ -0,0 +1,42 @@
+From 2e4370f257fae84d18d1f6ef3a756795d77d5707 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 23 May 2024 16:02:59 +0530
+Subject: [PATCH 52/53] Merge gdb/microblaze-linux-tdep.c to gdb-14 and fix
+ compilation issues.
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/microblaze-linux-tdep.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index babc9020f0f..00112b8f540 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -48,10 +48,12 @@ microblaze_debug (const char *fmt, ...)
+   if (microblaze_debug_flag)
+     {
+        va_list args;
++       string_file file (gdb_stdout->can_emit_style_escape ());
+ 
+        va_start (args, fmt);
+        printf_unfiltered ("MICROBLAZE LINUX: ");
+-       vprintf_unfiltered (fmt, args);
++       file.vprintf (fmt, args);
++       gdb_stdout->puts_unfiltered (file.string ().c_str ());
+        va_end (args);
+     }
+ }
+@@ -145,7 +147,7 @@ static void
+ microblaze_linux_init_abi (struct gdbarch_info info,
+                           struct gdbarch *gdbarch)
+ {
+-  struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *)  gdbarch_tdep (gdbarch);
++  struct microblaze_gdbarch_tdep *tdep = gdbarch_tdep<microblaze_gdbarch_tdep> (gdbarch);
+ 
+   tdep->sizeof_gregset = 200;
+ 
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0053-Roll-back-an-improvement-which-inlines-target_gdbarc.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0053-Roll-back-an-improvement-which-inlines-target_gdbarc.patch
new file mode 100644
index 00000000..f7d32927
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0053-Roll-back-an-improvement-which-inlines-target_gdbarc.patch
@@ -0,0 +1,29 @@
+From 13146f53b89c03b086e883e1f4bd9e14c32e6943 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Fri, 19 Jul 2024 12:39:24 +0530
+Subject: [PATCH 53/53] Roll back an improvement which inlines target_gdbarch
+ () inherited from binutils 2.42 merge that causes compilation issues on gdb
+ 14.2
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/microblaze-tdep.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index cc80e4f0e6b..86dedafdbd6 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -116,7 +116,7 @@ show_microblaze_abi (struct ui_file *file,
+                const char *ignored_value)
+ {
+       enum microblaze_abi global_abi = global_microblaze_abi ();
+-      enum microblaze_abi actual_abi = microblaze_abi (current_inferior ()->arch ());
++      enum microblaze_abi actual_abi = microblaze_abi ( target_gdbarch () );
+       const char *actual_abi_str = microblaze_abi_strings[actual_abi];
+ 
+ #if 1 
+-- 
+2.34.1
+
diff --git a/meta-vitis-tc/conf/machine/microblaze-tc.conf b/meta-vitis-tc/conf/machine/microblaze-tc.conf
index 8e9d9500..38e0b01b 100644
--- a/meta-vitis-tc/conf/machine/microblaze-tc.conf
+++ b/meta-vitis-tc/conf/machine/microblaze-tc.conf
@@ -37,7 +37,7 @@ MULTILIBS += "multilib:libmbbsmfpd"
 MULTILIBS += "multilib:libmbbspm"
 MULTILIBS += "multilib:libmbbspfpd"
 MULTILIBS += "multilib:libmbbspmfpd"
-#MULTILIBS += "multilib:libmblem64"
+MULTILIBS += "multilib:libmblem64"
 MULTILIBS += "multilib:libmblebs"
 MULTILIBS += "multilib:libmblep"
 MULTILIBS += "multilib:libmblem"
@@ -53,21 +53,21 @@ MULTILIBS += "multilib:libmblebsmfpd"
 MULTILIBS += "multilib:libmblebspm"
 MULTILIBS += "multilib:libmblebspfpd"
 MULTILIBS += "multilib:libmblebspmfpd"
-#MULTILIBS += "multilib:libmblem64bs"
-#MULTILIBS += "multilib:libmblem64p"
-#MULTILIBS += "multilib:libmblem64m"
-#MULTILIBS += "multilib:libmblem64fpd"
-#MULTILIBS += "multilib:libmblem64mfpd"
-#MULTILIBS += "multilib:libmblem64pm"
-#MULTILIBS += "multilib:libmblem64pfpd"
-#MULTILIBS += "multilib:libmblem64pmfpd"
-#MULTILIBS += "multilib:libmblem64bsp"
-#MULTILIBS += "multilib:libmblem64bsm"
-#MULTILIBS += "multilib:libmblem64bsfpd"
-#MULTILIBS += "multilib:libmblem64bsmfpd"
-#MULTILIBS += "multilib:libmblem64bspm"
-#MULTILIBS += "multilib:libmblem64bspfpd"
-#MULTILIBS += "multilib:libmblem64bspmfpd"
+MULTILIBS += "multilib:libmblem64bs"
+MULTILIBS += "multilib:libmblem64p"
+MULTILIBS += "multilib:libmblem64m"
+MULTILIBS += "multilib:libmblem64fpd"
+MULTILIBS += "multilib:libmblem64mfpd"
+MULTILIBS += "multilib:libmblem64pm"
+MULTILIBS += "multilib:libmblem64pfpd"
+MULTILIBS += "multilib:libmblem64pmfpd"
+MULTILIBS += "multilib:libmblem64bsp"
+MULTILIBS += "multilib:libmblem64bsm"
+MULTILIBS += "multilib:libmblem64bsfpd"
+MULTILIBS += "multilib:libmblem64bsmfpd"
+MULTILIBS += "multilib:libmblem64bspm"
+MULTILIBS += "multilib:libmblem64bspfpd"
+MULTILIBS += "multilib:libmblem64bspmfpd"
 
 
 # Base configuration