meta-microblaze: gdb: Update to latest version

Signed-off-by: Mark Hatle <mark.hatle@amd.com>

47 files changed, 5280 insertions, 2771 deletions

diff --git a/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc b/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc
index d3618229..151e7c25 100644
--- a/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc
+++ b/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc
@@ -4,14 +4,51 @@ LTTNGUST:microblaze = ""
 # Add MicroBlaze patches
 FILESEXTRAPATHS:append := ":${THISDIR}/gdb"
 
+# Our changes are all local, no real patch-status
+ERROR_QA:remove = "patch-status"
+
 SRC_URI:append:microblaze = " \
-     file://0001-Add-initial-port-of-linux-gdbserver.patch \
-     file://0002-Patch-MicroBlaze-Initial-port-of-core-reading-suppor.patch \
-     file://0003-Fix-debug-message-when-register-is-unavailable.patch \
-     file://0004-Patch-MicroBlaze-MicroBlaze-native-gdb-port.patch \
-     file://0005-Patch-microblaze-Adding-64-bit-MB-support.patch \
-     file://0006-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch \
-     file://0007-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch \
-     file://0008-Patch-MicroBlaze.patch \
-     file://0009-gdb-gdserver-Fix-ABI-settings-for-gdbserver.patch \
+     file://0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch \
+     file://0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch \
+     file://0003-Initial-port-of-core-reading-support-Added-support-f.patch \
+     file://0004-Fix-debug-message-when-register-is-unavailable.patch \
+     file://0005-MicroBlaze-native-gdb-port.patch \
+     file://0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch \
+     file://0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch \
+     file://0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch \
+     file://0009-Depth-Total-number-of-inline-functions-refer-inline-.patch \
+     file://0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch \
+     file://0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch \
+     file://0013-Disable-the-warning-message-for-eh_frame_hdr.patch \
+     file://0015-upstream-change-to-garbage-collection-sweep-causes-m.patch \
+     file://0016-Add-new-bit-field-instructions.patch \
+     file://0019-initial-support-for-MicroBlaze-64-bit-m64.patch \
+     file://0020-initial-support-for-MicroBlaze-64-bit-m64.patch \
+     file://0021-Added-relocations-for-MB-X.patch \
+     file://0022-initial-support-for-MicroBlaze-64-bit-m64.patch \
+     file://0023-Added-relocations-for-MB-X.patch \
+     file://0025-Fixed-address-computation-issues-with-64bit-address-.patch \
+     file://0028-fixing-the-long-long-long-mingw-toolchain-issue.patch \
+     file://0029-Added-support-to-new-arithmetic-single-register-inst.patch \
+     file://0030-double-imml-generation-for-64-bit-values.patch \
+     file://0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch \
+     file://0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch \
+     file://0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch \
+     file://0038-MB-binutils-Upstream-port-issues.patch \
+     file://0039-Initial-port-of-core-reading-support-Added-support-f.patch \
+     file://0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch \
+     file://0041-disable-truncated-register-warning-gdb-remote.c.patch \
+     file://0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch \
+     file://0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch \
+     file://0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch \
+     file://0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch \
+     file://0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch \
+     file://0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch \
+     file://0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch \
+     file://0049-Add-back-R_MICROBLAZE_NONE-for-linker-relaxation-pro.patch \
+     file://0050-When-unwinding-pc-value-adjust-return-pc-value.patch \
+     file://0051-info-reg-pc-does-not-print-symbolic-value.patch \
+     file://0052-Wrong-target-description-accepted-by-microblaze-arch.patch \
+     file://0053-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch \
+     file://0054-Roll-back-an-improvement-which-inlines-target_gdbarc.patch \
      "
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch
new file mode 100644
index 00000000..bf7b3363
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch
@@ -0,0 +1,42 @@
+From fc4e376f932514d9e5e3c04a18952d5900334c09 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 10 Oct 2022 15:07:22 +0530
+Subject: [PATCH 01/54] Add initial port of linux gdbserver add
+ gdb_proc_service_h to gdbserver microblaze-linux
+
+gdbserver needs to initialise the microblaze registers
+
+other archs use this step to run a *_arch_setup() to carry out all
+architecture specific setup - may need to add in future
+
+ * add linux-ptrace.o to gdbserver configure
+ * Update breakpoint opcode
+ * fix segfault on connecting gdbserver
+ * add microblaze_linux_memory_remove_breakpoint
+ * add set_solib_svr4_fetch_link_map_offsets
+ * add set_gdbarch_fetch_tls_load_module_address
+ * Force reading of r0 as 0, prevent stores
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdbserver/Makefile.in | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gdbserver/Makefile.in b/gdbserver/Makefile.in
+index b597515d428..faf32cd9d42 100644
+--- a/gdbserver/Makefile.in
++++ b/gdbserver/Makefile.in
+@@ -180,6 +180,7 @@ SFILES = \
+        $(srcdir)/linux-loongarch-low.cc \
+        $(srcdir)/linux-low.cc \
+        $(srcdir)/linux-m68k-low.cc \
++        $(srcdir)/linux-microblaze-low.cc \
+        $(srcdir)/linux-mips-low.cc \
+        $(srcdir)/linux-nios2-low.cc \
+        $(srcdir)/linux-or1k-low.cc \
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch
index 050bdde5..02b42cbd 100644
--- a/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver.patch
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch
@@ -1,7 +1,7 @@
-From baac387700a72407b3994bfd0a03825112c9745f Mon Sep 17 00:00:00 2001
+From fa91dbd8c23e519760213f32de572cbf98ad6bc3 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 10 Oct 2022 15:07:22 +0530
-Subject: [PATCH 1/8] Add initial port of linux gdbserver add
+Subject: [PATCH 02/54] Add initial port of linux gdbserver add
  gdb_proc_service_h to gdbserver microblaze-linux
 
 gdbserver needs to initialise the microblaze registers
@@ -17,11 +17,10 @@ architecture specific setup - may need to add in future
  * add set_gdbarch_fetch_tls_load_module_address
  * Force reading of r0 as 0, prevent stores
 
-Upstream-Status: Pending
-
 Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
 Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
 Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
 ---
  gdb/configure.host                  |   2 +
  gdb/features/Makefile               |   1 +
@@ -31,10 +30,9 @@ Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
  gdb/microblaze-tdep.h               |   4 +-
  gdb/regformats/microblaze-linux.dat |  64 +++++++
  gdb/regformats/reg-microblaze.dat   |  41 +++++
- gdbserver/Makefile.in               |   1 +
  gdbserver/configure.srv             |  10 ++
  gdbserver/linux-microblaze-low.cc   | 269 ++++++++++++++++++++++++++++
- 11 files changed, 466 insertions(+), 3 deletions(-)
+ 10 files changed, 465 insertions(+), 3 deletions(-)
  create mode 100644 gdb/features/microblaze-linux.xml
  create mode 100644 gdb/regformats/microblaze-linux.dat
  create mode 100644 gdb/regformats/reg-microblaze.dat
@@ -61,7 +59,7 @@ index da71675b201..877537d06ef 100644
  mips*-*-netbsdaout* | mips*-*-knetbsd*-gnu)
                         gdb_host=nbsd ;;
 diff --git a/gdb/features/Makefile b/gdb/features/Makefile
-index 68e17d0085d..fc3196864c9 100644
+index 32341f71815..0af9d67c2f7 100644
 --- a/gdb/features/Makefile
 +++ b/gdb/features/Makefile
 @@ -46,6 +46,7 @@
@@ -92,7 +90,7 @@ index 00000000000..688a3f83d1e
 +  <xi:include href="microblaze-core.xml"/>
 +</target>
 diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
-index daa7ddf7e4d..5748556a556 100644
+index ae33cb5c014..9160b4ad464 100644
 --- a/gdb/microblaze-linux-tdep.c
 +++ b/gdb/microblaze-linux-tdep.c
 @@ -37,6 +37,22 @@
@@ -152,7 +150,7 @@ index daa7ddf7e4d..5748556a556 100644
  
  void _initialize_microblaze_linux_tdep ();
 diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
-index 3d5dd669341..3e8e8fe35b9 100644
+index f254a54305c..28a647e940b 100644
 --- a/gdb/microblaze-tdep.c
 +++ b/gdb/microblaze-tdep.c
 @@ -128,7 +128,38 @@ microblaze_fetch_instruction (CORE_ADDR pc)
@@ -195,7 +193,7 @@ index 3d5dd669341..3e8e8fe35b9 100644
  
  /* Allocate and initialize a frame cache.  */
  
-@@ -716,6 +747,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+@@ -714,6 +745,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
                                        microblaze_breakpoint::kind_from_pc);
    set_gdbarch_sw_breakpoint_from_kind (gdbarch,
                                        microblaze_breakpoint::bp_from_kind);
@@ -203,14 +201,14 @@ index 3d5dd669341..3e8e8fe35b9 100644
  
    set_gdbarch_frame_args_skip (gdbarch, 8);
  
-@@ -756,4 +788,5 @@ When non-zero, microblaze specific debugging is enabled."),
+@@ -754,4 +786,5 @@ When non-zero, microblaze specific debugging is enabled."),
                              NULL,
                              &setdebuglist, &showdebuglist);
  
 +
  }
 diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
-index 4d90e8785dc..53fcb2297e6 100644
+index 892e5b3b849..e9f57e97c26 100644
 --- a/gdb/microblaze-tdep.h
 +++ b/gdb/microblaze-tdep.h
 @@ -118,6 +118,8 @@ struct microblaze_frame_cache
@@ -340,23 +338,11 @@ index 00000000000..bd8a4384424
 +32:fsr
 +32:slr
 +32:shr
-diff --git a/gdbserver/Makefile.in b/gdbserver/Makefile.in
-index 47648b8d962..55a5f5b81ae 100644
---- a/gdbserver/Makefile.in
-+++ b/gdbserver/Makefile.in
-@@ -178,6 +178,7 @@ SFILES = \
-        $(srcdir)/linux-ia64-low.cc \
-        $(srcdir)/linux-low.cc \
-        $(srcdir)/linux-m68k-low.cc \
-+       $(srcdir)/linux-microblaze-low.cc \
-        $(srcdir)/linux-mips-low.cc \
-        $(srcdir)/linux-nios2-low.cc \
-        $(srcdir)/linux-or1k-low.cc \
 diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv
-index 6e09b0eeb79..1817f1f04fb 100644
+index 9e861a75088..11ce617e72f 100644
 --- a/gdbserver/configure.srv
 +++ b/gdbserver/configure.srv
-@@ -145,6 +145,16 @@ case "${gdbserver_host}" in
+@@ -159,6 +159,16 @@ case "${gdbserver_host}" in
                         srv_linux_regsets=yes
                         srv_linux_thread_db=yes
                         ;;
@@ -649,5 +635,5 @@ index 00000000000..bf9eecc41ab
 +}
 +
 -- 
-2.37.1 (Apple Git-137.1)
+2.34.1
 
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0003-Fix-debug-message-when-register-is-unavailable.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0003-Fix-debug-message-when-register-is-unavailable.patch
deleted file mode 100644
index d8ba6fca..00000000
--- a/meta-microblaze/recipes-devtools/gdb/gdb/0003-Fix-debug-message-when-register-is-unavailable.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 6ecb1de66a6a5f55e69c9b108a3d5a85b0ebf315 Mon Sep 17 00:00:00 2001
-From: Nathan Rossi <nathan.rossi@petalogix.com>
-Date: Tue, 8 May 2012 18:11:17 +1000
-Subject: [PATCH 3/8] Fix debug message when register is unavailable
-
-Upstream-Status: Pending
-
-Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
-
-Conflicts:
-        gdb/frame.c
----
- gdb/frame.c | 21 ++++++++++++++-------
- 1 file changed, 14 insertions(+), 7 deletions(-)
-
-diff --git a/gdb/frame.c b/gdb/frame.c
-index ce95cf8343b..c49ab9feab2 100644
---- a/gdb/frame.c
-+++ b/gdb/frame.c
-@@ -1261,13 +1261,20 @@ frame_unwind_register_value (frame_info *next_frame, int regnum)
-          else
-            {
-              int i;
--             gdb::array_view<const gdb_byte> buf = value_contents (value);
--
--             fprintf_unfiltered (&debug_file, " bytes=");
--             fprintf_unfiltered (&debug_file, "[");
--             for (i = 0; i < register_size (gdbarch, regnum); i++)
--               fprintf_unfiltered (&debug_file, "%02x", buf[i]);
--             fprintf_unfiltered (&debug_file, "]");
-+             const gdb_byte *buf = NULL;
-+             if (value_entirely_available(value)) {
-+               gdb::array_view<const gdb_byte> buf = value_contents (value);
-+             }
-+
-+             fprintf_unfiltered (gdb_stdlog, " bytes=");
-+             fprintf_unfiltered (gdb_stdlog, "[");
-+             if (buf != NULL) {
-+               for (i = 0; i < register_size (gdbarch, regnum); i++)
-+                 fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
-+             } else {
-+               fprintf_unfiltered (gdb_stdlog, "unavailable");
-+             }
-+             fprintf_unfiltered (gdb_stdlog, "]");
-            }
-        }
- 
--- 
-2.37.1 (Apple Git-137.1)
-
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0002-Patch-MicroBlaze-Initial-port-of-core-reading-suppor.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0003-Initial-port-of-core-reading-support-Added-support-f.patch
index f7af2a62..6e86a773 100644
--- a/meta-microblaze/recipes-devtools/gdb/gdb/0002-Patch-MicroBlaze-Initial-port-of-core-reading-suppor.patch
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0003-Initial-port-of-core-reading-support-Added-support-f.patch
@@ -1,16 +1,14 @@
-From 7da397cae8c0f8826184d6e12fda9ccd11f92753 Mon Sep 17 00:00:00 2001
+From 118ce6c252a56ca592a7fdd40919522be00d5fb4 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 10 Oct 2022 16:37:53 +0530
-Subject: [PATCH 2/8] [Patch,MicroBlaze]: Initial port of core reading support
- Added support for reading notes in linux core dumps Support for reading of
- PRSTATUS and PSINFO information for rebuilding ".reg" sections of core dumps
- at run time.
-
-Upstream-Status: Pending
+Subject: [PATCH 03/54] Initial port of core reading support Added support for
+ reading notes in linux core dumps Support for reading of PRSTATUS and PSINFO
+ information for rebuilding ".reg" sections of core dumps at run time.
 
 Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
 Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
 Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
 ---
  bfd/elf32-microblaze.c      | 84 +++++++++++++++++++++++++++++++++++++
  gdb/configure.tgt           |  2 +-
@@ -20,10 +18,10 @@ Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
  5 files changed, 177 insertions(+), 2 deletions(-)
 
 diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index d09b3f7095d..d3b3c66cf00 100644
+index a7e81c70fc8..487ddeafc5a 100644
 --- a/bfd/elf32-microblaze.c
 +++ b/bfd/elf32-microblaze.c
-@@ -713,6 +713,87 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
+@@ -754,6 +754,87 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
    return _bfd_elf_is_local_label_name (abfd, name);
  }
  
@@ -111,7 +109,7 @@ index d09b3f7095d..d3b3c66cf00 100644
  /* ELF linker hash entry.  */
  
  struct elf32_mb_link_hash_entry
-@@ -3434,4 +3515,7 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
+@@ -3480,4 +3561,7 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
  #define elf_backend_size_dynamic_sections      microblaze_elf_size_dynamic_sections
  #define elf_backend_add_symbol_hook            microblaze_elf_add_symbol_hook
  
@@ -120,10 +118,10 @@ index d09b3f7095d..d3b3c66cf00 100644
 +
  #include "elf32-target.h"
 diff --git a/gdb/configure.tgt b/gdb/configure.tgt
-index 0705ccf32b8..7ea186481f3 100644
+index 47a674201f9..d0673abd2b8 100644
 --- a/gdb/configure.tgt
 +++ b/gdb/configure.tgt
-@@ -400,7 +400,7 @@ mep-*-*)
+@@ -415,7 +415,7 @@ mep-*-*)
  
  microblaze*-linux-*|microblaze*-*-linux*)
         # Target: Xilinx MicroBlaze running Linux
@@ -133,7 +131,7 @@ index 0705ccf32b8..7ea186481f3 100644
         ;;
  microblaze*-*-*)
 diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
-index 5748556a556..d6197c49dfd 100644
+index 9160b4ad464..17bcb50fd4f 100644
 --- a/gdb/microblaze-linux-tdep.c
 +++ b/gdb/microblaze-linux-tdep.c
 @@ -36,6 +36,7 @@
@@ -179,10 +177,10 @@ index 5748556a556..d6197c49dfd 100644
    set_gdbarch_fetch_tls_load_module_address (gdbarch,
                                               svr4_fetch_objfile_link_map);
 diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
-index 3e8e8fe35b9..ccd37d085d6 100644
+index 28a647e940b..6ab36bd746b 100644
 --- a/gdb/microblaze-tdep.c
 +++ b/gdb/microblaze-tdep.c
-@@ -666,6 +666,43 @@ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
+@@ -665,6 +665,43 @@ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
                                   tdesc_microblaze_with_stack_protect);
  }
  
@@ -226,9 +224,9 @@ index 3e8e8fe35b9..ccd37d085d6 100644
  static struct gdbarch *
  microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
  {
-@@ -718,6 +755,10 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-   microblaze_gdbarch_tdep *tdep = new microblaze_gdbarch_tdep;
-   gdbarch = gdbarch_alloc (&info, tdep);
+@@ -716,6 +753,10 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   gdbarch *gdbarch
+     = gdbarch_alloc (&info, gdbarch_tdep_up (new microblaze_gdbarch_tdep));
  
 +  tdep->gregset = NULL;
 +  tdep->sizeof_gregset = 0;
@@ -237,7 +235,7 @@ index 3e8e8fe35b9..ccd37d085d6 100644
    set_gdbarch_long_double_bit (gdbarch, 128);
  
    set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS);
-@@ -766,6 +807,13 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+@@ -764,6 +805,13 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
    frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
    if (tdesc_data != NULL)
      tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data));
@@ -252,7 +250,7 @@ index 3e8e8fe35b9..ccd37d085d6 100644
    return gdbarch;
  }
 diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
-index 53fcb2297e6..2e853d84d72 100644
+index e9f57e97c26..738da4f0531 100644
 --- a/gdb/microblaze-tdep.h
 +++ b/gdb/microblaze-tdep.h
 @@ -23,8 +23,23 @@
@@ -267,7 +265,7 @@ index 53fcb2297e6..2e853d84d72 100644
 +   unsigned int pregs[16];
 +};
 +
- struct microblaze_gdbarch_tdep : gdbarch_tdep
+ struct microblaze_gdbarch_tdep : gdbarch_tdep_base
  {
 +  int dummy;           // declare something.
 +
@@ -299,5 +297,5 @@ index 53fcb2297e6..2e853d84d72 100644
  
  #endif /* microblaze-tdep.h */
 -- 
-2.37.1 (Apple Git-137.1)
+2.34.1
 
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0004-Fix-debug-message-when-register-is-unavailable.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0004-Fix-debug-message-when-register-is-unavailable.patch
new file mode 100644
index 00000000..1e6aff76
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0004-Fix-debug-message-when-register-is-unavailable.patch
@@ -0,0 +1,45 @@
+From a027a1ce861f93bd00d814d6aef28414069330a1 Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan.rossi@petalogix.com>
+Date: Tue, 8 May 2012 18:11:17 +1000
+Subject: [PATCH 04/54] Fix debug message when register is unavailable
+
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+
+Conflicts:
+        gdb/frame.c
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/frame.c | 14 +++++++++++---
+ 1 file changed, 11 insertions(+), 3 deletions(-)
+
+diff --git a/gdb/frame.c b/gdb/frame.c
+index 87fb3d7a2d5..c4d967e01d5 100644
+--- a/gdb/frame.c
++++ b/gdb/frame.c
+@@ -1313,12 +1313,20 @@ frame_unwind_register_value (frame_info_ptr next_frame, int regnum)
+          else
+            {
+              int i;
+-             gdb::array_view<const gdb_byte> buf = value->contents ();
++
++             const gdb_byte *buf = NULL;
++             if (value_entirely_available(value)) {
++               gdb::array_view<const gdb_byte> buf = value->contents ();
++             }
+ 
+              gdb_printf (&debug_file, " bytes=");
+              gdb_printf (&debug_file, "[");
+-             for (i = 0; i < register_size (gdbarch, regnum); i++)
+-               gdb_printf (&debug_file, "%02x", buf[i]);
++             if (buf != NULL) {
++               for (i = 0; i < register_size (gdbarch, regnum); i++)
++                 gdb_printf (&debug_file, "%02x", buf[i]);
++             } else {
++               gdb_printf (&debug_file, "unavailable");
++             }
+              gdb_printf (&debug_file, "]");
+            }
+        }
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0004-Patch-MicroBlaze-MicroBlaze-native-gdb-port.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0005-MicroBlaze-native-gdb-port.patch
index 08b0ae17..a9c6aee4 100644
--- a/meta-microblaze/recipes-devtools/gdb/gdb/0004-Patch-MicroBlaze-MicroBlaze-native-gdb-port.patch
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0005-MicroBlaze-native-gdb-port.patch
@@ -1,13 +1,11 @@
-From 8d05b79cda7617f228fa4bb6e5147689b662699e Mon Sep 17 00:00:00 2001
+From 2e84106b932f40eeaa4ae40b441b9eb7b713b2fa Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 10 Oct 2022 18:53:46 +0530
-Subject: [PATCH 4/8] [Patch,MicroBlaze] : MicroBlaze native gdb port.
+Subject: [PATCH 05/54] MicroBlaze native gdb port.
 
 signed-off-by : Mahesh Bodapati <mbodapat@amd.com>
-Upstream-Status: Pending
-
-Signed-off-by: Mark Hatle <mark.hatle@amd.com>
 
+Signed-off-by: Aayush Misra <aayushm@amd.com>
 ---
  gdb/Makefile.in                 |   2 +
  gdb/configure.nat               |   4 +
@@ -23,10 +21,10 @@ Signed-off-by: Mark Hatle <mark.hatle@amd.com>
  create mode 100644 gdb/microblaze-linux-tdep.h
 
 diff --git a/gdb/Makefile.in b/gdb/Makefile.in
-index aecab41eeb8..fb63e1662c1 100644
+index 9c0a0bff2cd..1ad975b50ae 100644
 --- a/gdb/Makefile.in
 +++ b/gdb/Makefile.in
-@@ -1374,6 +1374,7 @@ HFILES_NO_SRCDIR = \
+@@ -1406,6 +1406,7 @@ HFILES_NO_SRCDIR = \
         memory-map.h \
         memrange.h \
         microblaze-tdep.h \
@@ -34,7 +32,7 @@ index aecab41eeb8..fb63e1662c1 100644
         mips-linux-tdep.h \
         mips-netbsd-tdep.h \
         mips-tdep.h \
-@@ -2249,6 +2250,7 @@ ALLDEPFILES = \
+@@ -1754,6 +1755,7 @@ ALLDEPFILES = \
         m68k-linux-nat.c \
         m68k-linux-tdep.c \
         m68k-tdep.c \
@@ -43,10 +41,10 @@ index aecab41eeb8..fb63e1662c1 100644
         microblaze-tdep.c \
         mingw-hdep.c \
 diff --git a/gdb/configure.nat b/gdb/configure.nat
-index b45519fd116..256c666e760 100644
+index 1dc4206b69c..05003e57020 100644
 --- a/gdb/configure.nat
 +++ b/gdb/configure.nat
-@@ -270,6 +270,10 @@ case ${gdb_host} in
+@@ -274,6 +274,10 @@ case ${gdb_host} in
                 # Host: Motorola m68k running GNU/Linux.
                 NATDEPFILES="${NATDEPFILES} m68k-linux-nat.o"
                 ;;
@@ -144,378 +142,378 @@ index 00000000000..267e12f6d59
 +}
 diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c
 new file mode 100755
-index 00000000000..6b9daa23120
+index 00000000000..a348001a3e2
 --- /dev/null
 +++ b/gdb/microblaze-linux-nat.c
 @@ -0,0 +1,366 @@
-+/* Native-dependent code for GNU/Linux MicroBlaze.

-+   Copyright (C) 2021 Free Software Foundation, Inc.

-+

-+   This file is part of GDB.

-+

-+   This program is free software; you can redistribute it and/or modify

-+   it under the terms of the GNU General Public License as published by

-+   the Free Software Foundation; either version 3 of the License, or

-+   (at your option) any later version.

-+

-+   This program is distributed in the hope that it will be useful,

-+   but WITHOUT ANY WARRANTY; without even the implied warranty of

-+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

-+   GNU General Public License for more details.

-+

-+   You should have received a copy of the GNU General Public License

-+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

-+

-+#include "defs.h"

-+#include "arch-utils.h"

-+#include "dis-asm.h"

-+#include "frame.h"

-+#include "trad-frame.h"

-+#include "symtab.h"

-+#include "value.h"

-+#include "gdbcmd.h"

-+#include "breakpoint.h"

-+#include "inferior.h"

-+#include "gdbthread.h"

-+#include "gdbcore.h"

-+#include "regcache.h"

-+#include "regset.h"

-+#include "target.h"

-+#include "frame.h"

-+#include "frame-base.h"

-+#include "frame-unwind.h"

-+#include "osabi.h"

-+#include "gdbsupport/gdb_assert.h"

-+#include <string.h>

-+#include "target-descriptions.h"

-+#include "opcodes/microblaze-opcm.h"

-+#include "opcodes/microblaze-dis.h"

-+#include "gregset.h"

-+

-+#include "linux-nat.h"

-+#include "linux-tdep.h"

-+#include "target-descriptions.h"

-+

-+#include <sys/user.h>

-+#include <sys/ioctl.h>

-+#include <sys/uio.h>

-+#include "gdbsupport/gdb_wait.h"

-+#include <fcntl.h>

-+#include <sys/procfs.h>

-+#include "nat/gdb_ptrace.h"

-+#include "nat/linux-ptrace.h"

-+#include "inf-ptrace.h"

-+#include <algorithm>

-+#include <unordered_map>

-+#include <list>

-+#include <sys/ptrace.h>

-+

-+/* Prototypes for supply_gregset etc. */

-+#include "gregset.h"

-+

-+#include "microblaze-tdep.h"

-+#include "microblaze-linux-tdep.h"

-+#include "inferior.h"

-+

-+#include "elf/common.h"

-+

-+#include "auxv.h"

-+#include "linux-tdep.h"

-+

-+#include <sys/ptrace.h>

-+

-+

-+//int have_ptrace_getsetregs=1;

-+

-+/* MicroBlaze Linux native additions to the default linux support.  */

-+

-+class microblaze_linux_nat_target final : public linux_nat_target

-+{

-+public:

-+  /* Add our register access methods.  */

-+  void fetch_registers (struct regcache *regcache, int regnum) override;

-+  void store_registers (struct regcache *regcache, int regnum) override;

-+

-+  /* Read suitable target description.  */

-+  const struct target_desc *read_description () override;

-+};

-+

-+static microblaze_linux_nat_target the_microblaze_linux_nat_target;

-+

-+static int

-+microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)

-+{

-+  int u_addr = -1;

-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

-+  /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace

-+ *      interface, and not the wordsize of the program's ABI.  */

-+  int wordsize = sizeof (long);

-+

-+  /* General purpose registers occupy 1 slot each in the buffer.  */

-+  if (regno >= MICROBLAZE_R0_REGNUM

-+      && regno <= MICROBLAZE_FSR_REGNUM)

-+    u_addr = ((regno - MICROBLAZE_R0_REGNUM)* wordsize);

-+

-+  return u_addr;

-+}

-+

-+/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1)

-+   from regset GREGS into REGCACHE.  */

-+

-+static void

-+supply_gregset_regnum (struct regcache *regcache, const prgregset_t *gregs,

-+                      int regnum)

-+{

-+  int i;

-+  const elf_greg_t *regp = *gregs;

-+  /* Access all registers */

-+  if (regnum == -1)

-+    {

-+      /* We fill the general purpose registers.  */

-+      for (i = MICROBLAZE_R0_REGNUM + 1; i < MICROBLAZE_FSR_REGNUM; i++)

-+       regcache->raw_supply (i, regp + i);

-+

-+      /* Supply MICROBLAZE_PC_REGNUM from index 32.  */

-+      regcache->raw_supply (MICROBLAZE_PC_REGNUM, regp + 32);

-+

-+      /* Fill the inaccessible zero register with zero.  */

-+      regcache->raw_supply_zeroed (0);

-+    }

-+  else if (regnum == MICROBLAZE_R0_REGNUM)

-+    regcache->raw_supply_zeroed (0);

-+  else if (regnum == MICROBLAZE_PC_REGNUM)

-+    regcache->raw_supply (MICROBLAZE_PC_REGNUM, regp + 32);

-+  else if (regnum > MICROBLAZE_R0_REGNUM && regnum < MICROBLAZE_FSR_REGNUM)

-+    regcache->raw_supply (regnum, regp + regnum);

-+}

-+

-+/* Copy all general purpose registers from regset GREGS into REGCACHE.  */

-+

-+void

-+supply_gregset (struct regcache *regcache, const prgregset_t *gregs)

-+{

-+  supply_gregset_regnum (regcache, gregs, -1);

-+}

-+

-+/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1)

-+   from REGCACHE into regset GREGS.  */

-+

-+void

-+fill_gregset (const struct regcache *regcache, prgregset_t *gregs, int regnum)

-+{

-+  elf_greg_t *regp = *gregs;

-+  if (regnum == -1)

-+    {

-+      /* We fill the general purpose registers.  */

-+      for (int i = MICROBLAZE_R0_REGNUM + 1; i < MICROBLAZE_FSR_REGNUM; i++)

-+       regcache->raw_collect (i, regp + i);

-+

-+      regcache->raw_collect (MICROBLAZE_PC_REGNUM, regp + 32);

-+    }

-+  else if (regnum == MICROBLAZE_R0_REGNUM)

-+    /* Nothing to do here.  */

-+    ;

-+  else if (regnum > MICROBLAZE_R0_REGNUM && regnum < MICROBLAZE_FSR_REGNUM)

-+    regcache->raw_collect (regnum, regp + regnum);

-+  else if (regnum == MICROBLAZE_PC_REGNUM)

-+    regcache->raw_collect (MICROBLAZE_PC_REGNUM, regp + 32);

-+}

-+

-+/* Transfering floating-point registers between GDB, inferiors and cores.

-+   Since MicroBlaze floating-point registers are the same as GPRs these do

-+   nothing.  */

-+

-+void

-+supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregs)

-+{

-+}

-+

-+void

-+fill_fpregset (const struct regcache *regcache,

-+              gdb_fpregset_t *fpregs, int regno)

-+{

-+}

-+

-+

-+static void

-+fetch_register (struct regcache *regcache, int tid, int regno)

-+{

-+  struct gdbarch *gdbarch = regcache->arch ();

-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

-+  /* This isn't really an address.  But ptrace thinks of it as one.  */

-+  CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);

-+  int bytes_transferred;

-+  char buf[MICROBLAZE_MAX_REGISTER_SIZE];

-+

-+  if (regaddr == -1)

-+  {

-+    memset (buf, '\0', register_size (gdbarch, regno));   /* Supply zeroes */

-+    regcache->raw_supply (regno, buf);

-+    return;

-+  }

-+

-+  /* Read the raw register using sizeof(long) sized chunks.  On a

-+ *      32-bit platform, 64-bit floating-point registers will require two

-+ *           transfers.  */

-+  for (bytes_transferred = 0;

-+       bytes_transferred < register_size (gdbarch, regno);

-+       bytes_transferred += sizeof (long))

-+  {

-+    long l;

-+

-+    errno = 0;

-+    l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);

-+    if (errno == EIO)

-+    {

-+      printf("ptrace io error\n");

-+    }

-+    regaddr += sizeof (long);

-+    if (errno != 0)

-+    {

-+      char message[128];

-+      sprintf (message, "reading register %s (#%d)",

-+               gdbarch_register_name (gdbarch, regno), regno);

-+      perror_with_name (message);

-+    }

-+    memcpy (&buf[bytes_transferred], &l, sizeof (l));

-+  }

-+

-+  /* Now supply the register.  Keep in mind that the regcache's idea

-+ *      of the register's size may not be a multiple of sizeof

-+ *           (long).  */

-+  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)

-+  {

-+    /* Little-endian values are always found at the left end of the

-+ *        bytes transferred.  */

-+    regcache->raw_supply (regno, buf);

-+  }

-+  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)

-+  {

-+    /* Big-endian values are found at the right end of the bytes

-+ *        transferred.  */

-+    size_t padding = (bytes_transferred - register_size (gdbarch, regno));

-+    regcache->raw_supply (regno, buf + padding);

-+  }

-+  else

-+    internal_error (__FILE__, __LINE__,

-+                    _("fetch_register: unexpected byte order: %d"),

-+                    gdbarch_byte_order (gdbarch));

-+}

-+

-+

-+/* This is a wrapper for the fetch_all_gp_regs function.  It is

-+ * responsible for verifying if this target has the ptrace request

-+ * that can be used to fetch all general-purpose registers at one

-+ * shot.  If it doesn't, then we should fetch them using the

-+ * old-fashioned way, which is to iterate over the registers and

-+ * request them one by one.  */

-+static void

-+fetch_gp_regs (struct regcache *regcache, int tid)

-+{

-+  int i;

-+/* If we've hit this point, it doesn't really matter which

-+   architecture we are using.  We just need to read the

-+   registers in the "old-fashioned way".  */

-+  for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)

-+    fetch_register (regcache, tid, i);

-+}

-+

-+/* Return a target description for the current target.  */

-+

-+const struct target_desc *

-+microblaze_linux_nat_target::read_description ()

-+{

-+  return tdesc_microblaze_linux;

-+}

-+

-+/* Fetch REGNUM (or all registers if REGNUM == -1) from the target

-+   into REGCACHE using PTRACE_GETREGSET.  */

-+

-+void

-+microblaze_linux_nat_target::fetch_registers (struct regcache * regcache,

-+                                              int regno)

-+{

-+  /* Get the thread id for the ptrace call.  */

-+  int tid = regcache->ptid ().lwp ();

-+//int tid = get_ptrace_pid (regcache->ptid());

-+#if 1 

-+  if (regno == -1)

-+#endif

-+    fetch_gp_regs (regcache, tid);

-+#if 1

-+  else

-+    fetch_register (regcache, tid, regno);

-+#endif

-+}

-+

-+

-+/* Store REGNUM (or all registers if REGNUM == -1) to the target

-+   from REGCACHE using PTRACE_SETREGSET.  */

-+

-+void

-+microblaze_linux_nat_target::store_registers (struct regcache *regcache, int regno)

-+{

-+  int tid;

-+

-+  tid = get_ptrace_pid (regcache->ptid ());

-+

-+ struct gdbarch *gdbarch = regcache->arch ();

-+  /* This isn't really an address.  But ptrace thinks of it as one.  */

-+  CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);

-+  int i;

-+  size_t bytes_to_transfer;

-+  char buf[MICROBLAZE_MAX_REGISTER_SIZE];

-+

-+  if (regaddr == -1)

-+    return;

-+

-+  /* First collect the register.  Keep in mind that the regcache's

-+ *      idea of the register's size may not be a multiple of sizeof

-+ *           (long).  */

-+  memset (buf, 0, sizeof buf);

-+  bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));

-+  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)

-+  {

-+    /* Little-endian values always sit at the left end of the buffer.  */

-+    regcache->raw_collect (regno, buf);

-+  }

-+  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)

-+  {

-+    /* Big-endian values sit at the right end of the buffer.  */

-+    size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));

-+    regcache->raw_collect (regno, buf + padding);

-+  }

-+

-+ for (i = 0; i < bytes_to_transfer; i += sizeof (long))

-+  { 

-+    long l;

-+

-+    memcpy (&l, &buf[i], sizeof (l));

-+    errno = 0;

-+    ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);

-+    regaddr += sizeof (long);

-+

-+    if (errno != 0)

-+    { 

-+      char message[128];

-+      sprintf (message, "writing register %s (#%d)",

-+               gdbarch_register_name (gdbarch, regno), regno);

-+      perror_with_name (message);

-+    }

-+  }

-+}

-+

-+void _initialize_microblaze_linux_nat (void);

-+

-+void

-+_initialize_microblaze_linux_nat (void)

-+{

-+  /* Register the target.  */

-+  linux_target = &the_microblaze_linux_nat_target;

-+  add_inf_child_target (linux_target);

-+}

++/* Native-dependent code for GNU/Linux MicroBlaze.
++   Copyright (C) 2021 Free Software Foundation, Inc.
++
++   This file is part of GDB.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
++
++#include "defs.h"
++#include "arch-utils.h"
++#include "dis-asm.h"
++#include "frame.h"
++#include "trad-frame.h"
++#include "symtab.h"
++#include "value.h"
++#include "gdbcmd.h"
++#include "breakpoint.h"
++#include "inferior.h"
++#include "gdbthread.h"
++#include "gdbcore.h"
++#include "regcache.h"
++#include "regset.h"
++#include "target.h"
++#include "frame.h"
++#include "frame-base.h"
++#include "frame-unwind.h"
++#include "osabi.h"
++#include "gdbsupport/gdb_assert.h"
++#include <string.h>
++#include "target-descriptions.h"
++#include "opcodes/microblaze-opcm.h"
++#include "opcodes/microblaze-dis.h"
++#include "gregset.h"
++
++#include "linux-nat.h"
++#include "linux-tdep.h"
++#include "target-descriptions.h"
++
++#include <sys/user.h>
++#include <sys/ioctl.h>
++#include <sys/uio.h>
++#include "gdbsupport/gdb_wait.h"
++#include <fcntl.h>
++#include <sys/procfs.h>
++#include "nat/gdb_ptrace.h"
++#include "nat/linux-ptrace.h"
++#include "inf-ptrace.h"
++#include <algorithm>
++#include <unordered_map>
++#include <list>
++#include <sys/ptrace.h>
++
++/* Prototypes for supply_gregset etc. */
++#include "gregset.h"
++
++#include "microblaze-tdep.h"
++#include "microblaze-linux-tdep.h"
++#include "inferior.h"
++
++#include "elf/common.h"
++
++#include "auxv.h"
++#include "linux-tdep.h"
++
++#include <sys/ptrace.h>
++
++
++//int have_ptrace_getsetregs=1;
++
++/* MicroBlaze Linux native additions to the default linux support.  */
++
++class microblaze_linux_nat_target final : public linux_nat_target
++{
++public:
++  /* Add our register access methods.  */
++  void fetch_registers (struct regcache *regcache, int regnum) override;
++  void store_registers (struct regcache *regcache, int regnum) override;
++
++  /* Read suitable target description.  */
++  const struct target_desc *read_description () override;
++};
++
++static microblaze_linux_nat_target the_microblaze_linux_nat_target;
++
++static int
++microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
++{
++  int u_addr = -1;
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
++ *      interface, and not the wordsize of the program's ABI.  */
++  int wordsize = sizeof (long);
++
++  /* General purpose registers occupy 1 slot each in the buffer.  */
++  if (regno >= MICROBLAZE_R0_REGNUM
++      && regno <= MICROBLAZE_FSR_REGNUM)
++    u_addr = ((regno - MICROBLAZE_R0_REGNUM)* wordsize);
++
++  return u_addr;
++}
++
++/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1)
++   from regset GREGS into REGCACHE.  */
++
++static void
++supply_gregset_regnum (struct regcache *regcache, const prgregset_t *gregs,
++                      int regnum)
++{
++  int i;
++  const elf_greg_t *regp = *gregs;
++  /* Access all registers */
++  if (regnum == -1)
++    {
++      /* We fill the general purpose registers.  */
++      for (i = MICROBLAZE_R0_REGNUM + 1; i < MICROBLAZE_FSR_REGNUM; i++)
++       regcache->raw_supply (i, regp + i);
++
++      /* Supply MICROBLAZE_PC_REGNUM from index 32.  */
++      regcache->raw_supply (MICROBLAZE_PC_REGNUM, regp + 32);
++
++      /* Fill the inaccessible zero register with zero.  */
++      regcache->raw_supply_zeroed (0);
++    }
++  else if (regnum == MICROBLAZE_R0_REGNUM)
++    regcache->raw_supply_zeroed (0);
++  else if (regnum == MICROBLAZE_PC_REGNUM)
++    regcache->raw_supply (MICROBLAZE_PC_REGNUM, regp + 32);
++  else if (regnum > MICROBLAZE_R0_REGNUM && regnum < MICROBLAZE_FSR_REGNUM)
++    regcache->raw_supply (regnum, regp + regnum);
++}
++
++/* Copy all general purpose registers from regset GREGS into REGCACHE.  */
++
++void
++supply_gregset (struct regcache *regcache, const prgregset_t *gregs)
++{
++  supply_gregset_regnum (regcache, gregs, -1);
++}
++
++/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1)
++   from REGCACHE into regset GREGS.  */
++
++void
++fill_gregset (const struct regcache *regcache, prgregset_t *gregs, int regnum)
++{
++  elf_greg_t *regp = *gregs;
++  if (regnum == -1)
++    {
++      /* We fill the general purpose registers.  */
++      for (int i = MICROBLAZE_R0_REGNUM + 1; i < MICROBLAZE_FSR_REGNUM; i++)
++       regcache->raw_collect (i, regp + i);
++
++      regcache->raw_collect (MICROBLAZE_PC_REGNUM, regp + 32);
++    }
++  else if (regnum == MICROBLAZE_R0_REGNUM)
++    /* Nothing to do here.  */
++    ;
++  else if (regnum > MICROBLAZE_R0_REGNUM && regnum < MICROBLAZE_FSR_REGNUM)
++    regcache->raw_collect (regnum, regp + regnum);
++  else if (regnum == MICROBLAZE_PC_REGNUM)
++    regcache->raw_collect (MICROBLAZE_PC_REGNUM, regp + 32);
++}
++
++/* Transfering floating-point registers between GDB, inferiors and cores.
++   Since MicroBlaze floating-point registers are the same as GPRs these do
++   nothing.  */
++
++void
++supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregs)
++{
++}
++
++void
++fill_fpregset (const struct regcache *regcache,
++              gdb_fpregset_t *fpregs, int regno)
++{
++}
++
++
++static void
++fetch_register (struct regcache *regcache, int tid, int regno)
++{
++  struct gdbarch *gdbarch = regcache->arch ();
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  /* This isn't really an address.  But ptrace thinks of it as one.  */
++  CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
++  int bytes_transferred;
++  char buf[MICROBLAZE_MAX_REGISTER_SIZE];
++
++  if (regaddr == -1)
++  {
++    memset (buf, '\0', register_size (gdbarch, regno));   /* Supply zeroes */
++    regcache->raw_supply (regno, buf);
++    return;
++  }
++
++  /* Read the raw register using sizeof(long) sized chunks.  On a
++ *      32-bit platform, 64-bit floating-point registers will require two
++ *           transfers.  */
++  for (bytes_transferred = 0;
++       bytes_transferred < register_size (gdbarch, regno);
++       bytes_transferred += sizeof (long))
++  {
++    long l;
++
++    errno = 0;
++    l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
++    if (errno == EIO)
++    {
++      printf("ptrace io error\n");
++    }
++    regaddr += sizeof (long);
++    if (errno != 0)
++    {
++      char message[128];
++      sprintf (message, "reading register %s (#%d)",
++               gdbarch_register_name (gdbarch, regno), regno);
++      perror_with_name (message);
++    }
++    memcpy (&buf[bytes_transferred], &l, sizeof (l));
++  }
++
++  /* Now supply the register.  Keep in mind that the regcache's idea
++ *      of the register's size may not be a multiple of sizeof
++ *           (long).  */
++  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
++  {
++    /* Little-endian values are always found at the left end of the
++ *        bytes transferred.  */
++    regcache->raw_supply (regno, buf);
++  }
++  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++  {
++    /* Big-endian values are found at the right end of the bytes
++ *        transferred.  */
++    size_t padding = (bytes_transferred - register_size (gdbarch, regno));
++    regcache->raw_supply (regno, buf + padding);
++  }
++  else
++    internal_error (__FILE__, __LINE__,
++                    _("fetch_register: unexpected byte order: %d"),
++                    gdbarch_byte_order (gdbarch));
++}
++
++
++/* This is a wrapper for the fetch_all_gp_regs function.  It is
++ * responsible for verifying if this target has the ptrace request
++ * that can be used to fetch all general-purpose registers at one
++ * shot.  If it doesn't, then we should fetch them using the
++ * old-fashioned way, which is to iterate over the registers and
++ * request them one by one.  */
++static void
++fetch_gp_regs (struct regcache *regcache, int tid)
++{
++  int i;
++/* If we've hit this point, it doesn't really matter which
++   architecture we are using.  We just need to read the
++   registers in the "old-fashioned way".  */
++  for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
++    fetch_register (regcache, tid, i);
++}
++
++/* Return a target description for the current target.  */
++
++const struct target_desc *
++microblaze_linux_nat_target::read_description ()
++{
++  return tdesc_microblaze_linux;
++}
++
++/* Fetch REGNUM (or all registers if REGNUM == -1) from the target
++   into REGCACHE using PTRACE_GETREGSET.  */
++
++void
++microblaze_linux_nat_target::fetch_registers (struct regcache * regcache,
++                                              int regno)
++{
++  /* Get the thread id for the ptrace call.  */
++  int tid = regcache->ptid ().lwp ();
++//int tid = get_ptrace_pid (regcache->ptid());
++#if 1 
++  if (regno == -1)
++#endif
++    fetch_gp_regs (regcache, tid);
++#if 1
++  else
++    fetch_register (regcache, tid, regno);
++#endif
++}
++
++
++/* Store REGNUM (or all registers if REGNUM == -1) to the target
++   from REGCACHE using PTRACE_SETREGSET.  */
++
++void
++microblaze_linux_nat_target::store_registers (struct regcache *regcache, int regno)
++{
++  int tid;
++
++  tid = get_ptrace_pid (regcache->ptid ());
++
++ struct gdbarch *gdbarch = regcache->arch ();
++  /* This isn't really an address.  But ptrace thinks of it as one.  */
++  CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
++  int i;
++  size_t bytes_to_transfer;
++  char buf[MICROBLAZE_MAX_REGISTER_SIZE];
++
++  if (regaddr == -1)
++    return;
++
++  /* First collect the register.  Keep in mind that the regcache's
++ *      idea of the register's size may not be a multiple of sizeof
++ *           (long).  */
++  memset (buf, 0, sizeof buf);
++  bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
++  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
++  {
++    /* Little-endian values always sit at the left end of the buffer.  */
++    regcache->raw_collect (regno, buf);
++  }
++  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++  {
++    /* Big-endian values sit at the right end of the buffer.  */
++    size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
++    regcache->raw_collect (regno, buf + padding);
++  }
++
++ for (i = 0; i < bytes_to_transfer; i += sizeof (long))
++  { 
++    long l;
++
++    memcpy (&l, &buf[i], sizeof (l));
++    errno = 0;
++    ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
++    regaddr += sizeof (long);
++
++    if (errno != 0)
++    { 
++      char message[128];
++      sprintf (message, "writing register %s (#%d)",
++               gdbarch_register_name (gdbarch, regno), regno);
++      perror_with_name (message);
++    }
++  }
++}
++
++void _initialize_microblaze_linux_nat (void);
++
++void
++_initialize_microblaze_linux_nat (void)
++{
++  /* Register the target.  */
++  linux_target = &the_microblaze_linux_nat_target;
++  add_inf_child_target (linux_target);
++}
 diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
-index d6197c49dfd..fc52adffb72 100644
+index 17bcb50fd4f..5b57bb4d3ba 100644
 --- a/gdb/microblaze-linux-tdep.c
 +++ b/gdb/microblaze-linux-tdep.c
 @@ -37,6 +37,7 @@
@@ -563,7 +561,7 @@ index 00000000000..a2c744e2961
 + 
 +#endif /* MICROBLAZE_LINUX_TDEP_H */
 diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
-index ccd37d085d6..ccb6b730d64 100644
+index 6ab36bd746b..066602b385a 100644
 --- a/gdb/microblaze-tdep.c
 +++ b/gdb/microblaze-tdep.c
 @@ -285,6 +285,7 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
@@ -595,7 +593,7 @@ index ccd37d085d6..ccb6b730d64 100644
    if (ostart_pc > start_pc)
      return ostart_pc;
    return start_pc;
-@@ -453,6 +456,7 @@ microblaze_frame_cache (struct frame_info *next_frame, void **this_cache)
+@@ -453,6 +456,7 @@ microblaze_frame_cache (frame_info_ptr next_frame, void **this_cache)
    struct microblaze_frame_cache *cache;
    struct gdbarch *gdbarch = get_frame_arch (next_frame);
    int rn;
@@ -603,7 +601,7 @@ index ccd37d085d6..ccb6b730d64 100644
  
    if (*this_cache)
      return (struct microblaze_frame_cache *) *this_cache;
-@@ -466,10 +470,17 @@ microblaze_frame_cache (struct frame_info *next_frame, void **this_cache)
+@@ -466,10 +470,17 @@ microblaze_frame_cache (frame_info_ptr next_frame, void **this_cache)
      cache->register_offsets[rn] = -1;
  
    /* Call for side effects.  */
@@ -625,7 +623,7 @@ index ccd37d085d6..ccb6b730d64 100644
    return cache;
  }
  
-@@ -494,6 +505,25 @@ microblaze_frame_prev_register (struct frame_info *this_frame,
+@@ -494,6 +505,25 @@ microblaze_frame_prev_register (frame_info_ptr this_frame,
    struct microblaze_frame_cache *cache =
      microblaze_frame_cache (this_frame, this_cache);
  
@@ -651,7 +649,7 @@ index ccd37d085d6..ccb6b730d64 100644
    if (cache->frameless_p)
      {
        if (regnum == MICROBLAZE_PC_REGNUM)
-@@ -506,7 +536,9 @@ microblaze_frame_prev_register (struct frame_info *this_frame,
+@@ -506,7 +536,9 @@ microblaze_frame_prev_register (frame_info_ptr this_frame,
    else
      return trad_frame_get_prev_register (this_frame, cache->saved_regs,
                                          regnum);
@@ -662,8 +660,8 @@ index ccd37d085d6..ccb6b730d64 100644
  }
  
  static const struct frame_unwind microblaze_frame_unwind =
-@@ -622,7 +654,106 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
-   return (TYPE_LENGTH (type) == 16);
+@@ -621,7 +653,106 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
+   return (type->length () == 16);
  }
  
 -
@@ -770,7 +768,7 @@ index ccd37d085d6..ccb6b730d64 100644
  static int dwarf2_to_reg_map[78] =
  { 0  /* r0  */,   1  /* r1  */,   2  /* r2  */,   3  /* r3  */,  /*  0- 3 */
    4  /* r4  */,   5  /* r5  */,   6  /* r6  */,   7  /* r7  */,  /*  4- 7 */
-@@ -790,6 +921,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+@@ -788,6 +919,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
                                        microblaze_breakpoint::bp_from_kind);
    set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
  
@@ -780,7 +778,7 @@ index ccd37d085d6..ccb6b730d64 100644
  
    set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc);
 diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
-index 2e853d84d72..2415acfe7b6 100644
+index 738da4f0531..21f206777f0 100644
 --- a/gdb/microblaze-tdep.h
 +++ b/gdb/microblaze-tdep.h
 @@ -60,11 +60,11 @@ enum microblaze_regnum
@@ -832,5 +830,5 @@ index 2e853d84d72..2415acfe7b6 100644
    int frameless_p;
  
 -- 
-2.37.1 (Apple Git-137.1)
+2.34.1
 
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch
new file mode 100644
index 00000000..3a069fdf
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch
@@ -0,0 +1,1891 @@
+From 510b596b8cd25ccb3563555190d5396c7b378522 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 31 Jan 2019 14:36:00 +0530
+Subject: [PATCH 06/54] Adding 64 bit MB support Added new architecture to
+ Microblaze 64-bit support to GDB Signed-off-by :Nagaraju Mekala
+ <nmekala@xilix.com> Signed-off-by :Mahesh Bodapati <mbodapat@xilinx.com>
+
+Conflicts:
+        gdb/Makefile.in
+
+Conflicts:
+        bfd/cpu-microblaze.c
+        gdb/microblaze-tdep.c
+        ld/Makefile.am
+        ld/Makefile.in
+        opcodes/microblaze-dis.c
+
+Conflicts:
+        bfd/configure
+        gas/config/tc-microblaze.c
+        ld/Makefile.in
+        opcodes/microblaze-opcm.h
+
+Conflicts:
+        gdb/microblaze-tdep.c
+
+Conflicts:
+        bfd/elf32-microblaze.c
+        gas/config/tc-microblaze.c
+        gdb/features/Makefile
+        gdb/features/microblaze-with-stack-protect.c
+        gdb/microblaze-tdep.c
+        gdb/regformats/microblaze-with-stack-protect.dat
+        gdbserver/linux-microblaze-low.c
+        include/elf/common.h
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/Makefile.am                               |   2 +
+ bfd/Makefile.in                               |   3 +
+ bfd/archures.c                                |   2 +
+ bfd/bfd-in2.h                                 |  31 +++-
+ bfd/config.bfd                                |   4 +
+ bfd/configure                                 |   2 +
+ bfd/cpu-microblaze.c                          |  55 +++++-
+ bfd/elf32-microblaze.c                        | 155 ++++++++++++++--
+ bfd/libbfd.h                                  |   3 +
+ bfd/reloc.c                                   |  20 +++
+ bfd/targets.c                                 |   6 +
+ gdb/features/Makefile                         |   2 +
+ gdb/features/microblaze-core.xml              |   6 +-
+ gdb/features/microblaze-stack-protect.xml     |   4 +-
+ gdb/features/microblaze-with-stack-protect.c  |   8 +-
+ gdb/features/microblaze.c                     |   6 +-
+ gdb/features/microblaze64-core.xml            |  69 ++++++++
+ gdb/features/microblaze64-stack-protect.xml   |  12 ++
+ .../microblaze64-with-stack-protect.c         |  79 +++++++++
+ .../microblaze64-with-stack-protect.xml       |  12 ++
+ gdb/features/microblaze64.c                   |  77 ++++++++
+ gdb/features/microblaze64.xml                 |  11 ++
+ gdb/microblaze-linux-tdep.c                   |  36 +++-
+ gdb/microblaze-tdep.c                         | 125 +++++++++----
+ gdb/microblaze-tdep.h                         |   4 +-
+ include/elf/common.h                          |   1 +
+ include/elf/microblaze.h                      |   4 +
+ opcodes/microblaze-dis.c                      |  51 +++++-
+ opcodes/microblaze-opc.h                      | 165 +++++++++++++++++-
+ opcodes/microblaze-opcm.h                     |  28 ++-
+ 30 files changed, 896 insertions(+), 87 deletions(-)
+ create mode 100644 gdb/features/microblaze64-core.xml
+ create mode 100644 gdb/features/microblaze64-stack-protect.xml
+ create mode 100644 gdb/features/microblaze64-with-stack-protect.c
+ create mode 100644 gdb/features/microblaze64-with-stack-protect.xml
+ create mode 100644 gdb/features/microblaze64.c
+ create mode 100644 gdb/features/microblaze64.xml
+
+diff --git a/bfd/Makefile.am b/bfd/Makefile.am
+index 378c13198d6..089d86b6191 100644
+--- a/bfd/Makefile.am
++++ b/bfd/Makefile.am
+@@ -568,6 +568,7 @@ BFD64_BACKENDS = \
+        elf64-ppc.lo \
+        elf64-riscv.lo \
+        elf64-s390.lo \
++       elf64-microblaze.lo \
+        elf64-sparc.lo \
+        elf64-tilegx.lo \
+        elf64-x86-64.lo \
+@@ -615,6 +616,7 @@ BFD64_BACKENDS_CFILES = \
+        elf64-nfp.c \
+        elf64-ppc.c \
+        elf64-s390.c \
++       elf64-microblaze.c \
+        elf64-sparc.c \
+        elf64-tilegx.c \
+        elf64-x86-64.c \
+diff --git a/bfd/Makefile.in b/bfd/Makefile.in
+index 8d09f6fa4af..d9fe20f502b 100644
+--- a/bfd/Makefile.in
++++ b/bfd/Makefile.in
+@@ -1025,6 +1025,7 @@ BFD64_BACKENDS = \
+        elf64-ppc.lo \
+        elf64-riscv.lo \
+        elf64-s390.lo \
++       elf64-microblaze.lo \
+        elf64-sparc.lo \
+        elf64-tilegx.lo \
+        elf64-x86-64.lo \
+@@ -1072,6 +1073,7 @@ BFD64_BACKENDS_CFILES = \
+        elf64-nfp.c \
+        elf64-ppc.c \
+        elf64-s390.c \
++       elf64-microblaze.c \
+        elf64-sparc.c \
+        elf64-tilegx.c \
+        elf64-x86-64.c \
+@@ -1646,6 +1648,7 @@ distclean-compile:
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ppc.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-riscv.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-s390.Plo@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-microblaze.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sparc.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-tilegx.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-x86-64.Plo@am__quote@
+diff --git a/bfd/archures.c b/bfd/archures.c
+index b59979e60ac..2994a09bc37 100644
+--- a/bfd/archures.c
++++ b/bfd/archures.c
+@@ -515,6 +515,8 @@ DESCRIPTION
+ .  bfd_arch_lm32,      {* Lattice Mico32.  *}
+ .#define bfd_mach_lm32         1
+ .  bfd_arch_microblaze,{* Xilinx MicroBlaze.  *}
++.#define bfd_mach_microblaze   1
++.#define bfd_mach_microblaze64 2
+ .  bfd_arch_kvx,        {* Kalray VLIW core of the MPPA processor family *}
+ .#define bfd_mach_kv3_unknown       0
+ .#define bfd_mach_kv3_1             1
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index eddb9902f5e..9db63f254a3 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -1771,6 +1771,8 @@ enum bfd_architecture
+   bfd_arch_lm32,      /* Lattice Mico32.  */
+ #define bfd_mach_lm32          1
+   bfd_arch_microblaze,/* Xilinx MicroBlaze.  */
++#define bfd_mach_microblaze    1
++#define bfd_mach_microblaze64  2
+   bfd_arch_kvx,        /* Kalray VLIW core of the MPPA processor family */
+ #define bfd_mach_kv3_unknown       0
+ #define bfd_mach_kv3_1             1
+@@ -6461,16 +6463,41 @@ value relative to the read-write small data area anchor  */
+ expressions of the form "Symbol Op Symbol"  */
+   BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
+ 
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
++/* This is a 32 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  No relocation is
+ done here - only used for relaxing  */
+-  BFD_RELOC_MICROBLAZE_64_NONE,
++  BFD_RELOC_MICROBLAZE_32_NONE,
++
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++ *  +value in two words (with an imml instruction).  No relocation is
++ *   +done here - only used for relaxing  */
++    BFD_RELOC_MICROBLAZE_64_PCREL,
++
++/* This is a 64 bit reloc that stores the 32 bit relative
++ *  +value in two words (with an imml instruction).  No relocation is
++ *   +done here - only used for relaxing  */
++    BFD_RELOC_MICROBLAZE_64,
++
++/* This is a 64 bit reloc that stores the 32 bit relative
++ *  +value in two words (with an imml instruction).  No relocation is
++ *   +done here - only used for relaxing  */
++    BFD_RELOC_MICROBLAZE_EA64,
++
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++ *  +value in two words (with an imm instruction).  No relocation is
++ *   +done here - only used for relaxing  */
++    BFD_RELOC_MICROBLAZE_64_NONE,
+ 
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  The relocation is
+ PC-relative GOT offset  */
+   BFD_RELOC_MICROBLAZE_64_GOTPC,
+ 
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++value in two words (with an imml instruction).  The relocation is
++PC-relative GOT offset  */
++  BFD_RELOC_MICROBLAZE_64_GPC,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  The relocation is
+ GOT offset  */
+diff --git a/bfd/config.bfd b/bfd/config.bfd
+index 08129e6a8cb..3a7d427778c 100644
+--- a/bfd/config.bfd
++++ b/bfd/config.bfd
+@@ -884,11 +884,15 @@ case "${targ}" in
+   microblazeel*-*)
+     targ_defvec=microblaze_elf32_le_vec
+     targ_selvecs=microblaze_elf32_vec
++    targ64_selvecs=microblaze_elf64_vec
++    targ64_selvecs=microblaze_elf64_le_vec
+     ;;
+ 
+   microblaze*-*)
+     targ_defvec=microblaze_elf32_vec
+     targ_selvecs=microblaze_elf32_le_vec
++    targ64_selvecs=microblaze_elf64_vec
++    targ64_selvecs=microblaze_elf64_le_vec
+     ;;
+ 
+ #ifdef BFD64
+diff --git a/bfd/configure b/bfd/configure
+index f0a07ff675f..b2afdcf9bec 100755
+--- a/bfd/configure
++++ b/bfd/configure
+@@ -14062,6 +14062,8 @@ do
+     rx_elf32_linux_le_vec)      tb="$tb elf32-rx.lo elf32.lo $elf" ;;
+     s390_elf32_vec)             tb="$tb elf32-s390.lo elf32.lo $elf" ;;
+     s390_elf64_vec)             tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;;
++    microblaze_elf64_vec)       tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
++    microblaze_elf64_le_vec)    tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
+     score_elf32_be_vec)                 tb="$tb elf32-score.lo elf32-score7.lo elf32.lo elf64.lo $elf"; want64=true; target_size=64 ;;
+     score_elf32_le_vec)                 tb="$tb elf32-score.lo elf32-score7.lo elf32.lo elf64.lo $elf"; want64=true; target_size=64 ;;
+     sh_coff_vec)                tb="$tb coff-sh.lo $coff" ;;
+diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c
+index c14b170f94b..7557b3de7b3 100644
+--- a/bfd/cpu-microblaze.c
++++ b/bfd/cpu-microblaze.c
+@@ -23,13 +23,30 @@
+ #include "bfd.h"
+ #include "libbfd.h"
+ 
+-const bfd_arch_info_type bfd_microblaze_arch =
++const bfd_arch_info_type bfd_microblaze_arch[] =
++{
++#if BFD_DEFAULT_TARGET_SIZE == 64
++{
++  64,                          /* 32 bits in a word.  */
++  64,                          /* 32 bits in an address.  */
++  8,                           /* 8 bits in a byte.  */
++  bfd_arch_microblaze,         /* Architecture.  */
++  bfd_mach_microblaze64,       /* 64 bit Machine */
++  "microblaze",                        /* Architecture name.  */
++  "MicroBlaze",                        /* Printable name.  */
++  3,                           /* Section align power.  */
++  false,                               /* Is this the default architecture ?  */
++  bfd_default_compatible,      /* Architecture comparison function.  */
++  bfd_default_scan,            /* String to architecture conversion.  */
++  bfd_arch_default_fill,       /* Default fill.  */
++  &bfd_microblaze_arch[1]      /* Next in list.  */
++},
+ {
+   32,                          /* Bits in a word.  */
+   32,                          /* Bits in an address.  */
+   8,                           /* Bits in a byte.  */
+   bfd_arch_microblaze,         /* Architecture number.  */
+-  0,                           /* Machine number - 0 for now.  */
++  bfd_mach_microblaze,         /* Machine number - 0 for now.  */
+   "microblaze",                        /* Architecture name.  */
+   "MicroBlaze",                        /* Printable name.  */
+   3,                           /* Section align power.  */
+@@ -39,4 +56,38 @@ const bfd_arch_info_type bfd_microblaze_arch =
+   bfd_arch_default_fill,       /* Default fill.  */
+   NULL,                                /* Next in list.  */
+   0 /* Maximum offset of a reloc from the start of an insn.  */
++}
++#else
++{
++  32,                          /* 32 bits in a word.  */
++  32,                          /* 32 bits in an address.  */
++  8,                           /* 8 bits in a byte.  */
++  bfd_arch_microblaze,                 /* Architecture.  */
++  bfd_mach_microblaze,         /* 32 bit Machine */
++  "microblaze",                        /* Architecture name.  */
++  "MicroBlaze",                        /* Printable name.  */
++  3,                           /* Section align power.  */
++  true,                                /* Is this the default architecture ?  */
++  bfd_default_compatible,      /* Architecture comparison function.  */
++  bfd_default_scan,            /* String to architecture conversion.  */
++  bfd_arch_default_fill,       /* Default fill.  */
++  &bfd_microblaze_arch[1]      /* Next in list.  */
++},
++{
++  64,                          /* 32 bits in a word.  */
++  64,                          /* 32 bits in an address.  */
++  8,                           /* 8 bits in a byte.  */
++  bfd_arch_microblaze,         /* Architecture.  */
++  bfd_mach_microblaze64,       /* 64 bit Machine */
++  "microblaze",                        /* Architecture name.  */
++  "MicroBlaze",                        /* Printable name.  */
++  3,                           /* Section align power.  */
++  false,                               /* Is this the default architecture ?  */
++  bfd_default_compatible,      /* Architecture comparison function.  */
++  bfd_default_scan,            /* String to architecture conversion.  */
++  bfd_arch_default_fill,       /* Default fill.  */
++  NULL,                                /* Next in list.  */
++  0
++}
++#endif
+ };
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 487ddeafc5a..6ba28e757be 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -114,6 +114,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+          0x0000ffff,           /* Dest Mask.  */
+          true),                /* PC relative offset?  */
+ 
++   HOWTO (R_MICROBLAZE_IMML_64,        /* Type.  */
++          0,                   /* Rightshift.  */
++          2,                   /* Size (0 = byte, 1 = short, 2 = long).  */
++          16,                  /* Bitsize.  */
++          true,                /* PC_relative.  */
++          0,                   /* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_IMML_64",      /* Name.  */
++          false,               /* Partial Inplace.  */
++          0,                   /* Source Mask.  */
++          0x0000ffff,          /* Dest Mask.  */
++          false),              /* PC relative offset?  */
++
+    /* A 64 bit relocation.  Table entry not really used.  */
+    HOWTO (R_MICROBLAZE_64,     /* Type.  */
+          0,                    /* Rightshift.  */
+@@ -174,7 +188,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+          0x0000ffff,           /* Dest Mask.  */
+          false),               /* PC relative offset?  */
+ 
+-   /* This reloc does nothing. Used for relaxation.  */
++   HOWTO (R_MICROBLAZE_32_NONE,   /* Type.  */
++          0,         /* Rightshift.  */
++          2,            /* Size (0 = byte, 1 = short, 2 = long).  */
++          32,           /* Bitsize.  */
++          true,         /* PC_relative.  */
++          0,           /* Bitpos.  */
++          complain_overflow_bitfield,  /* Complain on overflow.  */
++          NULL,                  /* Special Function.  */
++          "R_MICROBLAZE_32_NONE",/* Name.  */
++          false,       /* Partial Inplace.  */
++          0,          /* Source Mask.  */
++          0,         /* Dest Mask.  */
++          false),       /* PC relative offset?  */
++
++   /* This reloc does nothing.  Used for relaxation.  */
+    HOWTO (R_MICROBLAZE_64_NONE,        /* Type.  */
+          0,                    /* Rightshift.  */
+          0,                    /* Size.  */
+@@ -264,6 +292,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+          0x0000ffff,           /* Dest Mask.  */
+          true),                /* PC relative offset?  */
+ 
++   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GPC_64,         /* Type.  */
++          0,                   /* Rightshift.  */
++          2,                   /* Size (0 = byte, 1 = short, 2 = long).  */
++          16,                  /* Bitsize.  */
++          true,                        /* PC_relative.  */
++          0,                   /* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,       /* Special Function.  */
++          "R_MICROBLAZE_GPC_64",       /* Name.  */
++          false,               /* Partial Inplace.  */
++          0,                   /* Source Mask.  */
++          0x0000ffff,          /* Dest Mask.  */
++          true),               /* PC relative offset?  */
++
+    /* A 64 bit GOT relocation.  Table-entry not really used.  */
+    HOWTO (R_MICROBLAZE_GOT_64,  /* Type.  */
+          0,                    /* Rightshift.  */
+@@ -560,6 +603,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+     case BFD_RELOC_NONE:
+       microblaze_reloc = R_MICROBLAZE_NONE;
+       break;
++    case BFD_RELOC_MICROBLAZE_32_NONE:
++      microblaze_reloc = R_MICROBLAZE_32_NONE;
++      break;
+     case BFD_RELOC_MICROBLAZE_64_NONE:
+       microblaze_reloc = R_MICROBLAZE_64_NONE;
+       break;
+@@ -600,9 +646,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+     case BFD_RELOC_VTABLE_ENTRY:
+       microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
+       break;
++    case BFD_RELOC_MICROBLAZE_64:
++      microblaze_reloc = R_MICROBLAZE_IMML_64;
++      break;
+     case BFD_RELOC_MICROBLAZE_64_GOTPC:
+       microblaze_reloc = R_MICROBLAZE_GOTPC_64;
+       break;
++    case BFD_RELOC_MICROBLAZE_64_GPC:
++      microblaze_reloc = R_MICROBLAZE_GPC_64;
++      break;
+     case BFD_RELOC_MICROBLAZE_64_GOT:
+       microblaze_reloc = R_MICROBLAZE_GOT_64;
+       break;
+@@ -1564,7 +1616,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+                if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0)
+                  {
+                    relocation += addend;
+-                   if (r_type == R_MICROBLAZE_32)
++                   if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64)
+                      bfd_put_32 (input_bfd, relocation, contents + offset);
+                    else
+                      {
+@@ -1969,8 +2021,7 @@ microblaze_elf_relax_section (bfd *abfd,
+       else
+        symval += irel->r_addend;
+ 
+-      if ((symval & 0xffff8000) == 0
+-         || (symval & 0xffff8000) == 0xffff8000)
++      if ((symval & 0xffff8000) == 0)
+        {
+          /* We can delete this instruction.  */
+          sdata->relax[sdata->relax_count].addr = irel->r_offset;
+@@ -2034,15 +2085,44 @@ microblaze_elf_relax_section (bfd *abfd,
+                    irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
+                }
+              break;
+-           case R_MICROBLAZE_NONE:
++           case R_MICROBLAZE_IMML_64:
++             {
++               /* This was a PC-relative instruction that was
++                  completely resolved.  */
++               int sfix, efix;
++            unsigned int val;
++               bfd_vma target_address;
++               target_address = irel->r_addend + irel->r_offset;
++               sfix = calc_fixup (irel->r_offset, 0, sec);
++               efix = calc_fixup (target_address, 0, sec);
++
++            /* Validate the in-band val.  */
++            val = bfd_get_32 (abfd, contents + irel->r_offset);
++            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++            }
++               irel->r_addend -= (efix - sfix);
++               /* Should use HOWTO.  */
++               microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
++                                                  irel->r_addend);
++             }
++             break;
++           case R_MICROBLAZE_32_NONE:
+              {
+                /* This was a PC-relative instruction that was
+                   completely resolved.  */
+                size_t sfix, efix;
++               unsigned int val;
+                bfd_vma target_address;
+                target_address = irel->r_addend + irel->r_offset;
+                sfix = calc_fixup (irel->r_offset, 0, sec);
+                efix = calc_fixup (target_address, 0, sec);
++
++               /* Validate the in-band val.  */
++               val = bfd_get_32 (abfd, contents + irel->r_offset);
++               if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++                      fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++               }
+                irel->r_addend -= (efix - sfix);
+                /* Should use HOWTO.  */
+                microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
+@@ -2059,8 +2139,8 @@ microblaze_elf_relax_section (bfd *abfd,
+                sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec);
+                efix = calc_fixup (target_address, 0, sec);
+                irel->r_addend -= (efix - sfix);
+-    microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset
+-                                      + INST_WORD_SIZE, irel->r_addend);
++    microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
++                                       irel->r_addend);
+              }
+              break;
+            }
+@@ -2090,9 +2170,50 @@ microblaze_elf_relax_section (bfd *abfd,
+          irelscanend = irelocs + o->reloc_count;
+          for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+            {
+-             if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+-               {
+-                 isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++             if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
++                {
++                  unsigned int val;
++
++                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++
++                  /* hax: We only do the following fixup for debug location lists.  */
++                  if (strcmp(".debug_loc", o->name))
++                    continue;
++
++                  /* This was a PC-relative instruction that was completely resolved.  */
++                  if (ocontents == NULL)
++                    {
++                      if (elf_section_data (o)->this_hdr.contents != NULL)
++                          ocontents = elf_section_data (o)->this_hdr.contents;
++                      else
++                        {
++                          /* We always cache the section contents.
++                             Perhaps, if info->keep_memory is FALSE, we
++                             should free them, if we are permitted to.  */
++
++                          if (o->rawsize == 0)
++                              o->rawsize = o->size;
++                          ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++                          if (ocontents == NULL)
++                              goto error_return;
++                          if (!bfd_get_section_contents (abfd, o, ocontents,
++                                                         (file_ptr) 0,
++                                                         o->rawsize))
++                              goto error_return;
++                         elf_section_data (o)->this_hdr.contents = ocontents;
++                       }
++                   }
++                  val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++                  if (val != irelscan->r_addend) {
++                    fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
++                  }
++                  irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
++                  microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++                                                     irelscan->r_addend);
++              }
++              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)// || ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64)
++                {
++                 isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+                  /* Look at the reloc only if the value has been resolved.  */
+                  if (isym->st_shndx == shndx
+@@ -2149,7 +2270,7 @@ microblaze_elf_relax_section (bfd *abfd,
+                              elf_section_data (o)->this_hdr.contents = ocontents;
+                            }
+                        }
+-                     irelscan->r_addend -= calc_fixup (irel->r_addend
++              irelscan->r_addend -= calc_fixup (irelscan->r_addend
+                                                        + isym->st_value,
+                                                        0,
+                                                        sec);
+@@ -3490,6 +3611,14 @@ microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
+   return true;
+ }
+ 
++
++static bool
++elf_microblaze_object_p (bfd *abfd)
++{
++  /* Set the right machine number for an s390 elf32 file.  */
++  return bfd_default_set_arch_mach (abfd, bfd_arch_microblaze, bfd_mach_microblaze);
++}
++
+ /* Hook called by the linker routine which adds symbols from an object
+    file.  We use it to put .comm items in .sbss, and not .bss.  */
+ 
+@@ -3560,8 +3689,6 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
+ #define elf_backend_finish_dynamic_symbol      microblaze_elf_finish_dynamic_symbol
+ #define elf_backend_size_dynamic_sections      microblaze_elf_size_dynamic_sections
+ #define elf_backend_add_symbol_hook            microblaze_elf_add_symbol_hook
+-
+-#define elf_backend_grok_prstatus               microblaze_elf_grok_prstatus
+-#define elf_backend_grok_psinfo                 microblaze_elf_grok_psinfo
++#define elf_backend_object_p                   elf_microblaze_object_p
+ 
+ #include "elf32-target.h"
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index d5f42f22c08..b0e898bf815 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -3010,6 +3010,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+   "BFD_RELOC_MICROBLAZE_32_ROSDA",
+   "BFD_RELOC_MICROBLAZE_32_RWSDA",
+   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
++  "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+@@ -3017,6 +3018,8 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
+   "BFD_RELOC_MICROBLAZE_32_GOTOFF",
+   "BFD_RELOC_MICROBLAZE_COPY",
++  "BFD_RELOC_MICROBLAZE_64",
++  "BFD_RELOC_MICROBLAZE_64_PCREL",
+   "BFD_RELOC_MICROBLAZE_64_TLS",
+   "BFD_RELOC_MICROBLAZE_64_TLSGD",
+   "BFD_RELOC_MICROBLAZE_64_TLSLD",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index 2ac883d0eac..278876e765e 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6694,6 +6694,12 @@ ENUM
+ ENUMDOC
+   This is a 32 bit reloc for the microblaze to handle
+   expressions of the form "Symbol Op Symbol"
++ENUM
++  BFD_RELOC_MICROBLAZE_32_NONE
++ENUMDOC
++  This is a 32 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imm instruction).  No relocation is
++  done here - only used for relaxing
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
+@@ -7933,6 +7939,20 @@ ENUMX
+ ENUMDOC
+   Tilera TILE-Gx Relocations.
+ 
++  This is a 64 bit reloc that stores 64-bit thread pointer relative offset
++  to two words (uses imml instruction).
++ENUM
++BFD_RELOC_MICROBLAZE_64,
++ENUMDOC
++ This is a 64 bit reloc that stores the 64 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
++ENUM
++BFD_RELOC_MICROBLAZE_64_PCREL,
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
+ ENUM
+   BFD_RELOC_BPF_64
+ ENUMX
+diff --git a/bfd/targets.c b/bfd/targets.c
+index 63b3abbd287..c48c0929157 100644
+--- a/bfd/targets.c
++++ b/bfd/targets.c
+@@ -799,6 +799,8 @@ extern const bfd_target mep_elf32_le_vec;
+ extern const bfd_target metag_elf32_vec;
+ extern const bfd_target microblaze_elf32_vec;
+ extern const bfd_target microblaze_elf32_le_vec;
++extern const bfd_target microblaze_elf64_vec;
++extern const bfd_target microblaze_elf64_le_vec;
+ extern const bfd_target mips_ecoff_be_vec;
+ extern const bfd_target mips_ecoff_le_vec;
+ extern const bfd_target mips_ecoff_bele_vec;
+@@ -1166,6 +1168,10 @@ static const bfd_target * const _bfd_target_vector[] =
+ 
+        &metag_elf32_vec,
+ 
++#ifdef BFD64
++       &microblaze_elf64_vec,
++       &microblaze_elf64_le_vec,
++#endif
+        &microblaze_elf32_vec,
+ 
+        &mips_ecoff_be_vec,
+diff --git a/gdb/features/Makefile b/gdb/features/Makefile
+index 0af9d67c2f7..ee053b7557c 100644
+--- a/gdb/features/Makefile
++++ b/gdb/features/Makefile
+@@ -102,7 +102,9 @@ OUTPUTS = $(patsubst %,$(outdir)/%.dat,$(WHICH))
+ # to make on the command line.
+ XMLTOC = \
+        microblaze-with-stack-protect.xml \
++       microblaze64-with-stack-protect.xml \
+        microblaze.xml \
++       microblaze64.xml \
+        mips-dsp-linux.xml \
+        mips-linux.xml \
+        mips64-dsp-linux.xml \
+diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml
+index d49aa075bae..ac052365773 100644
+--- a/gdb/features/microblaze-core.xml
++++ b/gdb/features/microblaze-core.xml
+@@ -8,7 +8,7 @@
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze.core">
+   <reg name="r0" bitsize="32" regnum="0"/>
+-  <reg name="r1" bitsize="32" type="data_ptr"/>
++  <reg name="r1" bitsize="32"/>
+   <reg name="r2" bitsize="32"/>
+   <reg name="r3" bitsize="32"/>
+   <reg name="r4" bitsize="32"/>
+@@ -39,7 +39,7 @@
+   <reg name="r29" bitsize="32"/>
+   <reg name="r30" bitsize="32"/>
+   <reg name="r31" bitsize="32"/>
+-  <reg name="rpc" bitsize="32" type="code_ptr"/>
++  <reg name="rpc" bitsize="32"/>
+   <reg name="rmsr" bitsize="32"/>
+   <reg name="rear" bitsize="32"/>
+   <reg name="resr" bitsize="32"/>
+@@ -64,4 +64,6 @@
+   <reg name="rtlbsx" bitsize="32"/>
+   <reg name="rtlblo" bitsize="32"/>
+   <reg name="rtlbhi" bitsize="32"/>
++  <reg name="slr" bitsize="32"/>
++  <reg name="shr" bitsize="32"/>
+ </feature>
+diff --git a/gdb/features/microblaze-stack-protect.xml b/gdb/features/microblaze-stack-protect.xml
+index a5ffe2e50b1..b15369e03a4 100644
+--- a/gdb/features/microblaze-stack-protect.xml
++++ b/gdb/features/microblaze-stack-protect.xml
+@@ -7,6 +7,6 @@
+ 
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze.stack-protect">
+-  <reg name="rslr" bitsize="32"/>
+-  <reg name="rshr" bitsize="32"/>
++  <reg name="slr" bitsize="32"/>
++  <reg name="shr" bitsize="32"/>
+ </feature>
+diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c
+index 574dc02db67..8ab9565a047 100644
+--- a/gdb/features/microblaze-with-stack-protect.c
++++ b/gdb/features/microblaze-with-stack-protect.c
+@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+ 
+   feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core");
+   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
+@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
+@@ -72,8 +72,8 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+ 
+   feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.stack-protect");
+-  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int");
+ 
+   tdesc_microblaze_with_stack_protect = result.release ();
+ }
+diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c
+index 8f1fb0a142f..ed12e5bcfd2 100644
+--- a/gdb/features/microblaze.c
++++ b/gdb/features/microblaze.c
+@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void)
+ 
+   feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core");
+   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
+@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void)
+   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
+@@ -70,6 +70,8 @@ initialize_tdesc_microblaze (void)
+   tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
+ 
+   tdesc_microblaze = result.release ();
+ }
+diff --git a/gdb/features/microblaze64-core.xml b/gdb/features/microblaze64-core.xml
+new file mode 100644
+index 00000000000..96e99e2fb24
+--- /dev/null
++++ b/gdb/features/microblaze64-core.xml
+@@ -0,0 +1,69 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.microblaze64.core">
++  <reg name="r0" bitsize="64" regnum="0"/>
++  <reg name="r1" bitsize="64"/>
++  <reg name="r2" bitsize="64"/>
++  <reg name="r3" bitsize="64"/>
++  <reg name="r4" bitsize="64"/>
++  <reg name="r5" bitsize="64"/>
++  <reg name="r6" bitsize="64"/>
++  <reg name="r7" bitsize="64"/>
++  <reg name="r8" bitsize="64"/>
++  <reg name="r9" bitsize="64"/>
++  <reg name="r10" bitsize="64"/>
++  <reg name="r11" bitsize="64"/>
++  <reg name="r12" bitsize="64"/>
++  <reg name="r13" bitsize="64"/>
++  <reg name="r14" bitsize="64"/>
++  <reg name="r15" bitsize="64"/>
++  <reg name="r16" bitsize="64"/>
++  <reg name="r17" bitsize="64"/>
++  <reg name="r18" bitsize="64"/>
++  <reg name="r19" bitsize="64"/>
++  <reg name="r20" bitsize="64"/>
++  <reg name="r21" bitsize="64"/>
++  <reg name="r22" bitsize="64"/>
++  <reg name="r23" bitsize="64"/>
++  <reg name="r24" bitsize="64"/>
++  <reg name="r25" bitsize="64"/>
++  <reg name="r26" bitsize="64"/>
++  <reg name="r27" bitsize="64"/>
++  <reg name="r28" bitsize="64"/>
++  <reg name="r29" bitsize="64"/>
++  <reg name="r30" bitsize="64"/>
++  <reg name="r31" bitsize="64"/>
++  <reg name="rpc" bitsize="64"/>
++  <reg name="rmsr" bitsize="32"/>
++  <reg name="rear" bitsize="64"/>
++  <reg name="resr" bitsize="32"/>
++  <reg name="rfsr" bitsize="32"/>
++  <reg name="rbtr" bitsize="64"/>
++  <reg name="rpvr0" bitsize="32"/>
++  <reg name="rpvr1" bitsize="32"/>
++  <reg name="rpvr2" bitsize="32"/>
++  <reg name="rpvr3" bitsize="32"/>
++  <reg name="rpvr4" bitsize="32"/>
++  <reg name="rpvr5" bitsize="32"/>
++  <reg name="rpvr6" bitsize="32"/>
++  <reg name="rpvr7" bitsize="32"/>
++  <reg name="rpvr8" bitsize="64"/>
++  <reg name="rpvr9" bitsize="64"/>
++  <reg name="rpvr10" bitsize="32"/>
++  <reg name="rpvr11" bitsize="32"/>
++  <reg name="redr" bitsize="32"/>
++  <reg name="rpid" bitsize="32"/>
++  <reg name="rzpr" bitsize="32"/>
++  <reg name="rtlbx" bitsize="32"/>
++  <reg name="rtlbsx" bitsize="32"/>
++  <reg name="rtlblo" bitsize="32"/>
++  <reg name="rtlbhi" bitsize="32"/>
++  <reg name="slr" bitsize="64"/>
++  <reg name="shr" bitsize="64"/>
++</feature>
+diff --git a/gdb/features/microblaze64-stack-protect.xml b/gdb/features/microblaze64-stack-protect.xml
+new file mode 100644
+index 00000000000..1bbf5fc3cea
+--- /dev/null
++++ b/gdb/features/microblaze64-stack-protect.xml
+@@ -0,0 +1,12 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.microblaze64.stack-protect">
++  <reg name="slr" bitsize="64"/>
++  <reg name="shr" bitsize="64"/>
++</feature>
+diff --git a/gdb/features/microblaze64-with-stack-protect.c b/gdb/features/microblaze64-with-stack-protect.c
+new file mode 100644
+index 00000000000..a4de4666c76
+--- /dev/null
++++ b/gdb/features/microblaze64-with-stack-protect.c
+@@ -0,0 +1,79 @@
++/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
++  Original: microblaze-with-stack-protect.xml */
++
++#include "defs.h"
++#include "osabi.h"
++#include "target-descriptions.h"
++
++struct target_desc *tdesc_microblaze64_with_stack_protect;
++static void
++initialize_tdesc_microblaze64_with_stack_protect (void)
++{
++  target_desc_up result = allocate_target_description ();
++  struct tdesc_feature *feature;
++
++  feature = tdesc_create_feature (result.get() , "org.gnu.gdb.microblaze64.core");
++  tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "int");
++  tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++
++  feature = tdesc_create_feature (result.get(), "org.gnu.gdb.microblaze64.stack-protect");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++
++  tdesc_microblaze64_with_stack_protect = result.release();
++}
+diff --git a/gdb/features/microblaze64-with-stack-protect.xml b/gdb/features/microblaze64-with-stack-protect.xml
+new file mode 100644
+index 00000000000..0e9f01611f3
+--- /dev/null
++++ b/gdb/features/microblaze64-with-stack-protect.xml
+@@ -0,0 +1,12 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++  <xi:include href="microblaze64-core.xml"/>
++  <xi:include href="microblaze64-stack-protect.xml"/>
++</target>
+diff --git a/gdb/features/microblaze64.c b/gdb/features/microblaze64.c
+new file mode 100644
+index 00000000000..8ab7a90dd95
+--- /dev/null
++++ b/gdb/features/microblaze64.c
+@@ -0,0 +1,77 @@
++/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
++  Original: microblaze.xml */
++
++#include "defs.h"
++#include "osabi.h"
++#include "target-descriptions.h"
++
++struct target_desc *tdesc_microblaze64;
++static void
++initialize_tdesc_microblaze64 (void)
++{
++  target_desc_up result = allocate_target_description ();
++  struct tdesc_feature *feature;
++
++  feature = tdesc_create_feature (result.get(), "org.gnu.gdb.microblaze64.core");
++  tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++
++  tdesc_microblaze64 = result.release();
++}
+diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml
+new file mode 100644
+index 00000000000..515d18e65cf
+--- /dev/null
++++ b/gdb/features/microblaze64.xml
+@@ -0,0 +1,11 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++  <xi:include href="microblaze64-core.xml"/>
++</target>
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 5b57bb4d3ba..39592a43f7c 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -40,6 +40,7 @@
+ #include "features/microblaze-linux.c"
+ 
+ static int microblaze_debug_flag = 0;
++int MICROBLAZE_REGISTER_SIZE=4;
+ 
+ static void
+ microblaze_debug (const char *fmt, ...)
+@@ -55,6 +56,7 @@ microblaze_debug (const char *fmt, ...)
+     }
+ }
+ 
++#if 0
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, 
+                                           struct bp_target_info *bp_tgt)
+@@ -86,6 +88,8 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+   return val;
+ }
+ 
++#endif
++
+ static void
+ microblaze_linux_sigtramp_cache (frame_info_ptr next_frame,
+                                 struct trad_frame_cache *this_cache,
+@@ -147,8 +151,8 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ 
+   linux_init_abi (info, gdbarch, 0);
+ 
+-  set_gdbarch_memory_remove_breakpoint (gdbarch,
+-                                       microblaze_linux_memory_remove_breakpoint);
++ // set_gdbarch_memory_remove_breakpoint (gdbarch,
++ //                                    microblaze_linux_memory_remove_breakpoint);
+ 
+   /* Shared library handling.  */
+   set_solib_svr4_fetch_link_map_offsets (gdbarch,
+@@ -160,10 +164,30 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ 
+   /* BFD target for core files.  */
+   if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+-    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++    {
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
++          set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblaze");
++          MICROBLAZE_REGISTER_SIZE=8;
++        }
++      else
++        set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++    }
+   else
+-    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++    {
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
++          set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblazeel");
++          MICROBLAZE_REGISTER_SIZE=8;
++        }
++      else
++        set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++    }
+ 
++    switch (info.bfd_arch_info->mach)
++    {
++    case bfd_mach_microblaze64:
++      set_gdbarch_ptr_bit (gdbarch, 64);
++    break;
++    }
+ 
+   /* Shared library handling.  */
+   set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
+@@ -178,7 +202,9 @@ void _initialize_microblaze_linux_tdep ();
+ void
+ _initialize_microblaze_linux_tdep ()
+ {
+-  gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX, 
++  gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze, GDB_OSABI_LINUX, 
++                         microblaze_linux_init_abi);
++  gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze64, GDB_OSABI_LINUX, 
+                          microblaze_linux_init_abi);
+   initialize_tdesc_microblaze_linux ();
+ }
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 066602b385a..9450882e850 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -40,7 +40,9 @@
+ #include "remote.h"
+ 
+ #include "features/microblaze-with-stack-protect.c"
++#include "features/microblaze64-with-stack-protect.c"
+ #include "features/microblaze.c"
++#include "features/microblaze64.c"
+ 
+ /* Instruction macros used for analyzing the prologue.  */
+ /* This set of instruction macros need to be changed whenever the
+@@ -75,12 +77,13 @@ static const char * const microblaze_register_names[] =
+   "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6",
+   "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11",
+   "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi",
+-  "rslr", "rshr"
++  "slr", "shr"
+ };
+ 
+ #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
+ 
+ static unsigned int microblaze_debug_flag = 0;
++int reg_size = 4;
+ 
+ #define microblaze_debug(fmt, ...) \
+   debug_prefixed_printf_cond_nofunc (microblaze_debug_flag, "MICROBLAZE", \
+@@ -128,6 +131,15 @@ microblaze_fetch_instruction (CORE_ADDR pc)
+ constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
+ 
+ typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
++static CORE_ADDR
++microblaze_store_arguments (struct regcache *regcache, int nargs,
++                           struct value **args, CORE_ADDR sp,
++                           int struct_return, CORE_ADDR struct_addr)
++{
++  error (_("store_arguments not implemented"));
++  return sp;
++}
++#if 0
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+                                    struct bp_target_info *bp_tgt)
+@@ -146,7 +158,6 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+   /* Make sure we see the memory breakpoints.  */
+   scoped_restore restore_memory
+     = make_scoped_restore_show_memory_breakpoints (1);
+-
+   val = target_read_memory (addr, old_contents, bplen);
+ 
+   /* If our breakpoint is no longer at the address, this means that the
+@@ -161,6 +172,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+   return val;
+ }
+ 
++#endif
+ /* Allocate and initialize a frame cache.  */
+ 
+ static struct microblaze_frame_cache *
+@@ -583,11 +595,11 @@ microblaze_extract_return_value (struct type *type, struct regcache *regcache,
+     {
+       case 1:  /* return last byte in the register.  */
+        regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf);
+-       memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 1, 1);
++       memcpy(valbuf, buf + reg_size - 1, 1);
+        return;
+       case 2:  /* return last 2 bytes in register.  */
+        regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf);
+-       memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 2, 2);
++       memcpy(valbuf, buf + reg_size - 2, 2);
+        return;
+       case 4:  /* for sizes 4 or 8, copy the required length.  */
+       case 8:
+@@ -753,6 +765,12 @@ microblaze_software_single_step (struct regcache *regcache)
+ }
+ #endif
+ 
++static void
++microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc)
++{
++  regcache_cooked_write_unsigned (regcache, MICROBLAZE_PC_REGNUM, pc);
++}
++
+ static int dwarf2_to_reg_map[78] =
+ { 0  /* r0  */,   1  /* r1  */,   2  /* r2  */,   3  /* r3  */,  /*  0- 3 */
+   4  /* r4  */,   5  /* r5  */,   6  /* r6  */,   7  /* r7  */,  /*  4- 7 */
+@@ -787,13 +805,14 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
+ static void
+ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
+ {
++
+   register_remote_g_packet_guess (gdbarch,
+                                  4 * MICROBLAZE_NUM_CORE_REGS,
+-                                 tdesc_microblaze);
++                                 tdesc_microblaze64);
+ 
+   register_remote_g_packet_guess (gdbarch,
+                                  4 * MICROBLAZE_NUM_REGS,
+-                                 tdesc_microblaze_with_stack_protect);
++                                 tdesc_microblaze64_with_stack_protect);
+ }
+ 
+ void
+@@ -801,7 +820,7 @@ microblaze_supply_gregset (const struct regset *regset,
+                         struct regcache *regcache,
+                         int regnum, const void *gregs)
+ {
+-  const unsigned int *regs = (const unsigned int *)gregs;
++  const gdb_byte *regs = (const gdb_byte *) gregs;
+   if (regnum >= 0)
+     regcache->raw_supply (regnum, regs + regnum);
+ 
+@@ -809,7 +828,7 @@ microblaze_supply_gregset (const struct regset *regset,
+     int i;
+ 
+     for (i = 0; i < 50; i++) {
+-      regcache->raw_supply (i, regs + i);
++      regcache->raw_supply (regnum, regs + i);
+     }
+   }
+ }
+@@ -832,6 +851,17 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
+ }
+ 
+ 
++static void
++make_regs (struct gdbarch *arch)
++{
++  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
++  int mach = gdbarch_bfd_arch_info (arch)->mach;
++  
++  if (mach == bfd_mach_microblaze64)
++    {
++      set_gdbarch_ptr_bit (arch, 64);
++    }
++}
+ 
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+@@ -844,8 +874,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   if (arches != NULL)
+     return arches->gdbarch;
+   if (tdesc == NULL)
+-    tdesc = tdesc_microblaze;
+-
++    {
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) 
++        {
++         tdesc = tdesc_microblaze64;
++          reg_size = 8;
++       }
++      else
++       tdesc = tdesc_microblaze;
++    }
+   /* Check any target description for validity.  */
+   if (tdesc_has_registers (tdesc))
+     {
+@@ -853,31 +890,42 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+       int valid_p;
+       int i;
+ 
+-      feature = tdesc_find_feature (tdesc,
+-                                   "org.gnu.gdb.microblaze.core");
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++        feature = tdesc_find_feature (tdesc,
++                                    "org.gnu.gdb.microblaze64.core");
++      else
++        feature = tdesc_find_feature (tdesc,
++                                    "org.gnu.gdb.microblaze.core");
+       if (feature == NULL)
+        return NULL;
+       tdesc_data = tdesc_data_alloc ();
+ 
+       valid_p = 1;
+-      for (i = 0; i < MICROBLAZE_NUM_CORE_REGS; i++)
+-       valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i,
+-                                           microblaze_register_names[i]);
+-      feature = tdesc_find_feature (tdesc,
+-                                   "org.gnu.gdb.microblaze.stack-protect");
++      for (i = 0; i < MICROBLAZE_NUM_REGS; i++)
++        valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), i,
++                                            microblaze_register_names[i]);
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++        feature = tdesc_find_feature (tdesc,
++                                    "org.gnu.gdb.microblaze64.stack-protect");
++      else
++        feature = tdesc_find_feature (tdesc,
++                                    "org.gnu.gdb.microblaze.stack-protect");
+       if (feature != NULL)
+-       {
+-         valid_p = 1;
+-         valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+-                                             MICROBLAZE_SLR_REGNUM,
+-                                             "rslr");
+-         valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+-                                             MICROBLAZE_SHR_REGNUM,
+-                                             "rshr");
+-       }
++        {
++          valid_p = 1;
++          valid_p &= tdesc_numbered_register (feature, tdesc_data.get(),
++                                              MICROBLAZE_SLR_REGNUM,
++                                              "slr");
++          valid_p &= tdesc_numbered_register (feature, tdesc_data.get(),
++                                              MICROBLAZE_SHR_REGNUM,
++                                              "shr");
++        }
+ 
+       if (!valid_p)
+-       return NULL;
++        {
++         // tdesc_data_cleanup (tdesc_data.get ());
++          return NULL;
++        }
+     }
+ 
+   /* Allocate space for the new architecture.  */
+@@ -897,7 +945,17 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   /* Register numbers of various important registers.  */
+   set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM); 
+   set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM); 
++  
++  /* Register set.  
++  make_regs (gdbarch); */
++  switch (info.bfd_arch_info->mach)
++    {
++    case bfd_mach_microblaze64:
++      set_gdbarch_ptr_bit (gdbarch, 64);
++    break;
++    }
+ 
++  
+   /* Map Dwarf2 registers to GDB registers.  */
+   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum);
+ 
+@@ -917,7 +975,9 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+                                       microblaze_breakpoint::kind_from_pc);
+   set_gdbarch_sw_breakpoint_from_kind (gdbarch,
+                                       microblaze_breakpoint::bp_from_kind);
+-  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
++//  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
++
++//  set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+ 
+   set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+ 
+@@ -925,7 +985,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ 
+   set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc);
+ 
+-  microblaze_register_g_packet_guesses (gdbarch);
++  //microblaze_register_g_packet_guesses (gdbarch);
+ 
+   frame_base_set_default (gdbarch, &microblaze_frame_base);
+ 
+@@ -940,12 +1000,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+     tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data));
+   //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer);
+ 
+-  /* If we have register sets, enable the generic core file support.  */
++  /* If we have register sets, enable the generic core file support.  
+   if (tdep->gregset) {
+     set_gdbarch_iterate_over_regset_sections (gdbarch,
+                                           microblaze_iterate_over_regset_sections);
+-  }
+-
++  }*/
+   return gdbarch;
+ }
+ 
+@@ -957,6 +1016,8 @@ _initialize_microblaze_tdep ()
+ 
+   initialize_tdesc_microblaze_with_stack_protect ();
+   initialize_tdesc_microblaze ();
++  initialize_tdesc_microblaze64_with_stack_protect ();
++  initialize_tdesc_microblaze64 ();
+   /* Debug this files internals.  */
+   add_setshow_zuinteger_cmd ("microblaze", class_maintenance,
+                             &microblaze_debug_flag, _("\
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 21f206777f0..542cdd82070 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -28,7 +28,7 @@ struct microblaze_gregset
+    microblaze_gregset() {}
+    unsigned int gregs[32];
+    unsigned int fpregs[32];
+-   unsigned int pregs[16];
++   unsigned int pregs[18];
+ };
+ 
+ struct microblaze_gdbarch_tdep : gdbarch_tdep_base
+@@ -134,7 +134,7 @@ struct microblaze_frame_cache
+   struct trad_frame_saved_reg *saved_regs;
+ };
+ /* All registers are 32 bits.  */
+-#define MICROBLAZE_REGISTER_SIZE 4
++//#define MICROBLAZE_REGISTER_SIZE 8
+ 
+ /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
+    Only used for native debugging.  */
+diff --git a/include/elf/common.h b/include/elf/common.h
+index 244b13361e5..6395f69426f 100644
+--- a/include/elf/common.h
++++ b/include/elf/common.h
+@@ -360,6 +360,7 @@
+ #define EM_U16_U8CORE  260     /* LAPIS nX-U16/U8 */
+ #define EM_TACHYUM     261     /* Tachyum */
+ #define EM_56800EF     262     /* NXP 56800EF Digital Signal Controller (DSC) */
++#define EM_MB_64       263     /* Xilinx MicroBlaze 32-bit RISC soft processor core */
+ 
+ /* If it is necessary to assign new unofficial EM_* values, please pick large
+    random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision
+diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
+index fecdd7e4831..3306e3c3ad6 100644
+--- a/include/elf/microblaze.h
++++ b/include/elf/microblaze.h
+@@ -61,6 +61,10 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
+   RELOC_NUMBER (R_MICROBLAZE_TEXTPCREL_64, 30)  /* PC-relative TEXT offset.  */
+   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31)    /* TEXT Entry offset 64-bit.  */
+   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit.  */
++  RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
++  RELOC_NUMBER (R_MICROBLAZE_IMML_64, 34)
++  RELOC_NUMBER (R_MICROBLAZE_GPC_64, 35)    /* GOT entry offset.  */
++   
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+ 
+ /* Global base address names.  */
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 12981abfea1..c910f2ff210 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -33,6 +33,7 @@
+ #define get_field_r1(buf, instr)   get_field (buf, instr, RA_MASK, RA_LOW)
+ #define get_field_r2(buf, instr)   get_field (buf, instr, RB_MASK, RB_LOW)
+ #define get_int_field_imm(instr)   ((instr & IMM_MASK) >> IMM_LOW)
++#define get_int_field_imml(instr)  ((instr & IMML_MASK) >> IMM_LOW)
+ #define get_int_field_r1(instr)    ((instr & RA_MASK) >> RA_LOW)
+ 
+ #define NUM_STRBUFS 3
+@@ -73,11 +74,20 @@ get_field_imm (struct string_buf *buf, long instr)
+ }
+ 
+ static char *
+-get_field_imm5 (struct string_buf *buf, long instr)
++get_field_imml (struct string_buf *buf, long instr)
+ {
+   char *p = strbuf (buf);
+ 
+-  sprintf (p, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
++  sprintf (p, "%d", (int)((instr & IMML_MASK) >> IMM_LOW));
++  return p;
++}
++
++static char *
++get_field_imms (struct string_buf *buf, long instr)
++{
++  char *p = strbuf (buf);
++
++  sprintf (p, "%d", (short)((instr & IMM6_MASK) >> IMM_LOW));
+   return p;
+ }
+ 
+@@ -90,6 +100,18 @@ get_field_imm5_mbar (struct string_buf *buf, long instr)
+   return p;
+ }
+ 
++static char *
++get_field_immw (struct string_buf *buf, long instr)
++{
++  char *p = strbuf (buf);
++
++  if (instr & 0x00004000)
++    sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
++ else
++    sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM6_MASK) >> IMM_LOW) + 1)); /* bsifi */
++  return p;
++}
++
+ static char *
+ get_field_rfsl (struct string_buf *buf, long instr)
+ {
+@@ -296,9 +318,14 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+                }
+            }
+          break;
+-       case INST_TYPE_RD_R1_IMM5:
++       case INST_TYPE_RD_R1_IMML:
++         print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
++                  get_field_r1(&buf, inst), get_field_imm (&buf, inst));
++          /* TODO: Also print symbol */
++          break;
++       case INST_TYPE_RD_R1_IMMS:
+          print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
+-                     get_field_r1 (&buf, inst), get_field_imm5 (&buf, inst));
++                  get_field_r1(&buf, inst), get_field_imms (&buf, inst));
+          break;
+        case INST_TYPE_RD_RFSL:
+          print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
+@@ -402,9 +429,12 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+                }
+            }
+          break;
+-       case INST_TYPE_RD_R2:
+-         print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
+-                     get_field_r2 (&buf, inst));
++        case INST_TYPE_IMML:
++         print_func (stream, "\t%s", get_field_imml (&buf, inst));
++          /* TODO: Also print symbol */
++         break;
++        case INST_TYPE_RD_R2:
++         print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_r2 (&buf, inst));
+          break;
+        case INST_TYPE_R2:
+          print_func (stream, "\t%s", get_field_r2 (&buf, inst));
+@@ -427,7 +457,12 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+          /* For mbar 16 or sleep insn.  */
+        case INST_TYPE_NONE:
+          break;
+-         /* For tuqula instruction */
++        /* For bit field insns.  */
++       case INST_TYPE_RD_R1_IMMW_IMMS:
++         print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst),
++                  get_field_immw (&buf, inst), get_field_imms (&buf, inst));
++         break;
++       /* For tuqula instruction */
+        case INST_TYPE_RD:
+          print_func (stream, "\t%s", get_field_rd (&buf, inst));
+          break;
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 7398e9e246a..dc78712d67b 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -40,7 +40,7 @@
+ #define INST_TYPE_RD_SPECIAL 11
+ #define INST_TYPE_R1 12
+ /* New instn type for barrel shift imms.  */
+-#define INST_TYPE_RD_R1_IMM5  13
++#define INST_TYPE_RD_R1_IMMS  13
+ #define INST_TYPE_RD_RFSL    14
+ #define INST_TYPE_R1_RFSL    15
+ 
+@@ -59,6 +59,15 @@
+ /* For mbar.  */
+ #define INST_TYPE_IMM5 20
+ 
++/* For bsefi and bsifi */
++#define INST_TYPE_RD_R1_IMMW_IMMS  21
++
++/* For 64-bit instructions */
++#define INST_TYPE_IMML 22
++#define INST_TYPE_RD_R1_IMML 23
++#define INST_TYPE_R1_IMML 24
++#define INST_TYPE_RD_R1_IMMW_IMMS  21
++
+ #define INST_TYPE_NONE 25
+ 
+ 
+@@ -88,11 +97,14 @@
+ #define OPCODE_MASK_H24   0xFC1F07FF /* High 6, bits 20-16 and low 11 bits.  */
+ #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits.  */
+ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
+-#define OPCODE_MASK_H3    0xFC000600 /* High 6 bits and bits 21, 22.  */
++#define OPCODE_MASK_H3    0xFC000700 /* High 6 bits and bits 21, 22, 23.  */
++#define OPCODE_MASK_H3B   0xFC00E600 /* High 6 bits and bits 16, 17, 18, 21, 22.  */
+ #define OPCODE_MASK_H32   0xFC00FC00 /* High 6 bits and bit 16-21.  */
++#define OPCODE_MASK_H32B  0xFC00E000 /* High 6 bits and bit 16, 17, 18.  */
+ #define OPCODE_MASK_H34B  0xFC0000FF /* High 6 bits and low 8 bits.  */
+ #define OPCODE_MASK_H35B  0xFC0004FF /* High 6 bits and low 9 bits.  */
+ #define OPCODE_MASK_H34C  0xFC0007E0 /* High 6 bits and bits 21-26.  */
++#define OPCODE_MASK_H8    0xFF000000 /* High 8 bits only.  */
+ 
+ /* New Mask for msrset, msrclr insns.  */
+ #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16.  */
+@@ -102,7 +114,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 300
++#define MAX_OPCODES 412
+ 
+ const struct op_code_struct
+ {
+@@ -120,6 +132,7 @@ const struct op_code_struct
+   /* More info about output format here.  */
+ } microblaze_opcodes[MAX_OPCODES] =
+ {
++  /* 32-bit instructions */
+   {"add",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
+   {"rsub",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
+   {"addc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
+@@ -156,9 +169,11 @@ const struct op_code_struct
+   {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
+   {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
+   {"muli",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
+-  {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
+-  {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
+-  {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
++  {"bslli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst },
++  {"bsrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst },
++  {"bsrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst },
++  {"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
++  {"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+   {"or",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
+   {"and",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
+   {"xor",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
+@@ -260,9 +275,7 @@ const struct op_code_struct
+   {"la",    INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik.  */
+   {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42.  */
+   {"not",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1.  */
+-  {"neg",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0.  */
+   {"rtb",   INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4.  */
+-  {"sub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra.  */
+   {"lmi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },
+   {"smi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
+   {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
+@@ -418,6 +431,130 @@ const struct op_code_struct
+   {"suspend",   INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 24.  */
+   {"swapb",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4,   swapb,     arithmetic_inst },
+   {"swaph",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4,   swaph,     arithmetic_inst },
++  /* 64-bit instructions */
++  {"addl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000100, OPCODE_MASK_H4, addl, arithmetic_inst },
++  {"rsubl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000100, OPCODE_MASK_H4, rsubl, arithmetic_inst },
++  {"addlc",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000100, OPCODE_MASK_H4, addlc, arithmetic_inst },
++  {"rsublc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000100, OPCODE_MASK_H4, rsublc, arithmetic_inst },
++  {"addlk",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000100, OPCODE_MASK_H4, addlk, arithmetic_inst },
++  {"rsublk",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000100, OPCODE_MASK_H4, rsublk, arithmetic_inst },
++  {"addlkc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000100, OPCODE_MASK_H4, addlkc, arithmetic_inst },
++  {"rsublkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000100, OPCODE_MASK_H4, rsublkc, arithmetic_inst },
++  {"cmpl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
++  {"cmplu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
++  {"addli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsubli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlic",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlik",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },  /* Identical to 32-bit */
++  {"mull",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
++  {"bslll",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
++  {"bslra",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
++  {"bslrl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000100, OPCODE_MASK_H3, bslrl, barrel_shift_inst },
++  {"bsllli",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002400, OPCODE_MASK_H3B, bsllli, barrel_shift_inst },
++  {"bslrai",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002200, OPCODE_MASK_H3B, bslrai, barrel_shift_inst },
++  {"bslrli",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002000, OPCODE_MASK_H3B, bslrli, barrel_shift_inst },
++  {"bslefi",  INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64006000, OPCODE_MASK_H32B, bslefi, barrel_shift_inst },
++  {"bslifi",  INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6400a000, OPCODE_MASK_H32B, bslifi, barrel_shift_inst },
++  {"orl",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000100, OPCODE_MASK_H4, orl, logical_inst },
++  {"andl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000100, OPCODE_MASK_H4, andl, logical_inst },
++  {"xorl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000100, OPCODE_MASK_H4, xorl, logical_inst },
++  {"andnl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000100, OPCODE_MASK_H4, andnl, logical_inst },
++  {"pcmplbf", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000500, OPCODE_MASK_H4, pcmplbf, logical_inst },
++  {"pcmpleq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000500, OPCODE_MASK_H4, pcmpleq, logical_inst },
++  {"pcmplne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000500, OPCODE_MASK_H4, pcmplne, logical_inst },
++  {"srla",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000101, OPCODE_MASK_H34, srla, logical_inst },
++  {"srlc",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000121, OPCODE_MASK_H34, srlc, logical_inst },
++  {"srll",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000141, OPCODE_MASK_H34, srll, logical_inst },
++  {"sextl8",  INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000160, OPCODE_MASK_H34, sextl8, logical_inst },
++  {"sextl16", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000161, OPCODE_MASK_H34, sextl16, logical_inst },
++  {"sextl32", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000162, OPCODE_MASK_H34, sextl32, logical_inst },
++  {"brea",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98010000, OPCODE_MASK_H124, brea, branch_inst },
++  {"bread",   INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98110000, OPCODE_MASK_H124, bread, branch_inst },
++  {"breald",  INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98150000, OPCODE_MASK_H24, breald, branch_inst },
++  {"beaeq",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000000, OPCODE_MASK_H14, beaeq, branch_inst },
++  {"bealeq",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000100, OPCODE_MASK_H14, bealeq, branch_inst },
++  {"beaeqd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000000, OPCODE_MASK_H14, beaeqd, branch_inst },
++  {"bealeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000100, OPCODE_MASK_H14, bealeqd, branch_inst },
++  {"beane",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200000, OPCODE_MASK_H14, beane, branch_inst },
++  {"bealne",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200100, OPCODE_MASK_H14, bealne, branch_inst },
++  {"beaned",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200000, OPCODE_MASK_H14, beaned, branch_inst },
++  {"bealned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200100, OPCODE_MASK_H14, bealned, branch_inst },
++  {"bealt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400000, OPCODE_MASK_H14, bealt, branch_inst },
++  {"beallt",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400100, OPCODE_MASK_H14, beallt, branch_inst },
++  {"bealtd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400000, OPCODE_MASK_H14, bealtd, branch_inst },
++  {"bealltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400100, OPCODE_MASK_H14, bealltd, branch_inst },
++  {"beale",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600000, OPCODE_MASK_H14, beale, branch_inst },
++  {"bealle",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600100, OPCODE_MASK_H14, bealle, branch_inst },
++  {"bealed",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600000, OPCODE_MASK_H14, bealed, branch_inst },
++  {"bealled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600100, OPCODE_MASK_H14, bealled, branch_inst },
++  {"beagt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800000, OPCODE_MASK_H14, beagt, branch_inst },
++  {"bealgt",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800100, OPCODE_MASK_H14, bealgt, branch_inst },
++  {"beagtd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800000, OPCODE_MASK_H14, beagtd, branch_inst },
++  {"bealgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800100, OPCODE_MASK_H14, bealgtd, branch_inst },
++  {"beage",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00000, OPCODE_MASK_H14, beage, branch_inst },
++  {"bealge",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00100, OPCODE_MASK_H14, bealge, branch_inst },
++  {"beaged",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
++  {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
++  {"orli",    INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"andli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"xorli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"andnli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"imml",    INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
++  {"breai",   INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
++  {"breaid",  INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
++  {"brealid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8150000, OPCODE_MASK_H2, brealid, branch_inst },
++  {"beaeqi",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, beaeqi, branch_inst },
++  {"bealeqi", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqi */
++  {"beaeqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, beaeqid, branch_inst },
++  {"bealeqid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beaeqid */
++  {"beanei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, beanei, branch_inst },
++  {"bealnei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beanei */
++  {"beaneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, beaneid, branch_inst },
++  {"bealneid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beaneid */
++  {"bealti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, bealti, branch_inst },
++  {"beallti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealti */
++  {"bealtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, bealtid, branch_inst },
++  {"bealltid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to bealtid */
++  {"bealei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, bealei, branch_inst },
++  {"beallei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealei */
++  {"bealeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, bealeid, branch_inst },
++  {"bealleid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to bealeid */
++  {"beagti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, beagti, branch_inst },
++  {"bealgti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagti */
++  {"beagtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, beagtid, branch_inst },
++  {"bealgtid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beagtid */
++  {"beagei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, beagei, branch_inst },
++  {"bealgei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagei */
++  {"beageid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, beageid, branch_inst },
++  {"bealgeid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beageid */
++  {"ll",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000100, OPCODE_MASK_H4, ll, memory_load_inst },
++  {"llr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst },
++  {"sl",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst },
++  {"slr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst },
++  {"lli",     INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xEC000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },  /* Identical to 32-bit */
++  {"sli",     INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xFC000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
++  {"lla",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* lla translates to addlik */
++  {"dadd",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst },
++  {"drsub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst },
++  {"dmul",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000500, OPCODE_MASK_H4, dmul, arithmetic_inst },
++  {"ddiv",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000580, OPCODE_MASK_H4, ddiv, arithmetic_inst },
++  {"dcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000610, OPCODE_MASK_H4, dcmp_lt, arithmetic_inst },
++  {"dcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000620, OPCODE_MASK_H4, dcmp_eq, arithmetic_inst },
++  {"dcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000630, OPCODE_MASK_H4, dcmp_le, arithmetic_inst },
++  {"dcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000640, OPCODE_MASK_H4, dcmp_gt, arithmetic_inst },
++  {"dcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000650, OPCODE_MASK_H4, dcmp_ne, arithmetic_inst },
++  {"dcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000660, OPCODE_MASK_H4, dcmp_ge, arithmetic_inst },
++  {"dcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000600, OPCODE_MASK_H4, dcmp_un, arithmetic_inst },
++  {"dbl",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl,   arithmetic_inst },
++  {"dlong",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst },
++  {"dsqrt",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst },
++  {"neg",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0.  */
++  {"sub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra.  */
++
+   {"", 0, 0, 0, 0, 0, 0, 0, 0},
+ };
+ 
+@@ -438,5 +575,17 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM5  ((int) 0x00000000)
+ #define MAX_IMM5  ((int) 0x0000001f)
+ 
++#define MIN_IMM6  ((int) 0x00000000)
++#define MAX_IMM6  ((int) 0x0000003f)
++
++#define MIN_IMM_WIDTH  ((int) 0x00000001)
++#define MAX_IMM_WIDTH  ((int) 0x00000020)
++
++#define MIN_IMM6_WIDTH  ((int) 0x00000001)
++#define MAX_IMM6_WIDTH  ((int) 0x00000040)
++
++#define MIN_IMML  ((long) 0xffffff8000000000L)
++#define MAX_IMML  ((long) 0x0000007fffffffffL)
++
+ #endif /* MICROBLAZE_OPC */
+ 
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index c91b002d951..3923f6258d8 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -25,11 +25,12 @@
+ 
+ enum microblaze_instr
+ {
++  /* 32-bit instructions */
+   add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
+   addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
+   mulh, mulhu, mulhsu, swapb, swaph,
+   idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
+-  ncget, ncput, muli, bslli, bsrai, bsrli, mului,
++  ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
+   /* 'or/and/xor' are C++ keywords.  */
+   microblaze_or, microblaze_and, microblaze_xor,
+   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+@@ -39,8 +40,8 @@ enum microblaze_instr
+   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+   bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
+-  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
+-  sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
++  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, lli,
++  sbi, shi, sli, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
+   fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
+   /* 'fsqrt' is a glibc:math.h symbol.  */
+   fint, microblaze_fsqrt,
+@@ -59,6 +60,18 @@ enum microblaze_instr
+   aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
+   eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
+   eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
++
++  /* 64-bit instructions */
++  addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++  bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
++  andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
++  brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
++  bealned, bealt, beallt, bealtd, bealltd, beale, bealle, bealed, bealled, beagt,
++  bealgt, beagtd, bealgtd, beage, bealge, beaged, bealged, breai, breaid, brealid,
++  beaeqi, beaeqid, beanei, beaneid, bealti, bealtid, bealei, bealeid, beagti,
++  beagtid, beagei, beageid, imml, ll, llr, sl, slr,
++  dadd, drsub, dmul, ddiv, dcmp_lt, dcmp_eq, dcmp_le, dcmp_gt, dcmp_ne, dcmp_ge,
++  dcmp_un, dbl, dlong, dsqrt,
+   invalid_inst
+ };
+ 
+@@ -130,18 +143,25 @@ enum microblaze_instr_type
+ #define RB_LOW  11 /* Low bit for RB.  */
+ #define IMM_LOW  0 /* Low bit for immediate.  */
+ #define IMM_MBAR 21 /* low bit for mbar instruction.  */
++#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
+ 
+ #define RD_MASK 0x03E00000
+ #define RA_MASK 0x001F0000
+ #define RB_MASK 0x0000F800
+ #define IMM_MASK 0x0000FFFF
++#define IMML_MASK 0x00FFFFFF
+ 
+-/* Imm mask for barrel shifts.  */
++/* Imm masks for barrel shifts.  */
+ #define IMM5_MASK 0x0000001F
++#define IMM6_MASK 0x0000003F
+ 
+ /* Imm mask for mbar.  */
+ #define IMM5_MBAR_MASK 0x03E00000
+ 
++/* Imm masks for extract/insert width. */
++#define IMM5_WIDTH_MASK 0x000007C0
++#define IMM6_WIDTH_MASK 0x00000FC0
++
+ /* FSL imm mask for get, put instructions.  */
+ #define  RFSL_MASK 0x000000F
+ 
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0007-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0007-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch
deleted file mode 100644
index ec11e7be..00000000
--- a/meta-microblaze/recipes-devtools/gdb/gdb/0007-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch
+++ /dev/null
@@ -1,300 +0,0 @@
-From d2f145ec8e4e149e055adc74e92016447af91806 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 9 Nov 2021 16:19:17 +0530
-Subject: [PATCH 7/8] [Patch,MicroBlaze] : Added m64 abi for 64 bit target
- descriptions. set m64 abi for 64 bit elf.
-
-Conflicts:
-        gdb/microblaze-tdep.c
-        gdb/microblaze-tdep.h
-Upstream-Status: Pending
-
-Signed-off-by: Mark Hatle <mark.hatle@amd.com>
-
----
- gdb/features/microblaze64.xml |   1 +
- gdb/microblaze-tdep.c         | 159 ++++++++++++++++++++++++++++++++--
- gdb/microblaze-tdep.h         |  13 ++-
- 3 files changed, 165 insertions(+), 8 deletions(-)
-
-diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml
-index 515d18e65cf..9c1b7d22003 100644
---- a/gdb/features/microblaze64.xml
-+++ b/gdb/features/microblaze64.xml
-@@ -7,5 +7,6 @@
- 
- <!DOCTYPE target SYSTEM "gdb-target.dtd">
- <target>
-+  <architecture>microblaze64</architecture>
-   <xi:include href="microblaze64-core.xml"/>
- </target>
-diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
-index c347bb9516b..d83072cdaef 100644
---- a/gdb/microblaze-tdep.c
-+++ b/gdb/microblaze-tdep.c
-@@ -65,8 +65,95 @@
- #define IS_SAVE_HIDDEN_PTR(op, rd, ra, rb) \
-   ((op == add || op == addik) && ra == MICROBLAZE_FIRST_ARGREG && rb == 0)
- 
-+static const char *microblaze_abi_string;
-+
-+static const char *const microblaze_abi_strings[] = {
-+  "auto",
-+  "m64",
-+};
-+
-+enum microblaze_abi
-+microblaze_abi (struct gdbarch *gdbarch)
-+{
-+  microblaze_gdbarch_tdep *tdep = (microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch);
-+  return tdep->microblaze_abi;
-+}
- /* The registers of the Xilinx microblaze processor.  */
- 
-+ static struct cmd_list_element *setmicroblazecmdlist = NULL;
-+ static struct cmd_list_element *showmicroblazecmdlist = NULL;
-+
-+static void
-+microblaze_abi_update (const char *ignore_args,
-+                 int from_tty, struct cmd_list_element *c)
-+{
-+  struct gdbarch_info info;
-+
-+  /* Force the architecture to update, and (if it's a microblaze architecture)
-+ *      microblaze_gdbarch_init will take care of the rest.  */
-+//  gdbarch_info_init (&info);
-+  gdbarch_update_p (info);
-+}
-+
-+
-+static enum microblaze_abi
-+global_microblaze_abi (void)
-+{
-+  int i;
-+
-+  for (i = 0; microblaze_abi_strings[i] != NULL; i++)
-+    if (microblaze_abi_strings[i] == microblaze_abi_string)
-+      return (enum microblaze_abi) i;
-+
-+//  internal_error (__FILE__, __LINE__, _("unknown ABI string"));
-+}
-+
-+static void
-+show_microblaze_abi (struct ui_file *file,
-+               int from_tty,
-+               struct cmd_list_element *ignored_cmd,
-+               const char *ignored_value)
-+{
-+      enum microblaze_abi global_abi = global_microblaze_abi ();
-+      enum microblaze_abi actual_abi = microblaze_abi (target_gdbarch ());
-+      const char *actual_abi_str = microblaze_abi_strings[actual_abi];
-+
-+#if 1 
-+      if (global_abi == MICROBLAZE_ABI_AUTO)
-+        fprintf_filtered
-+          (file,
-+           "The microblaze ABI is set automatically (currently \"%s\").\n",
-+           actual_abi_str);    
-+      else if (global_abi == actual_abi)
-+        fprintf_filtered
-+          (file,
-+           "The microblaze ABI is assumed to be \"%s\" (due to user setting).\n",
-+           actual_abi_str);
-+      else
-+        {
-+#endif
-+          /* Probably shouldn't happen...  */
-+          fprintf_filtered (file,
-+                            "The (auto detected) microblaze ABI \"%s\" is in use "
-+                            "even though the user setting was \"%s\".\n",
-+             actual_abi_str, microblaze_abi_strings[global_abi]);
-+        }
-+}                 
-+
-+static void
-+show_microblaze_command (const char *args, int from_tty)
-+{
-+  help_list (showmicroblazecmdlist, "show microblaze ", all_commands, gdb_stdout);
-+}
-+
-+static void
-+set_microblaze_command (const char *args, int from_tty)
-+{
-+  printf_unfiltered
-+    ("\"set microblaze\" must be followed by an appropriate subcommand.\n");
-+  help_list (setmicroblazecmdlist, "set microblaze ", all_commands, gdb_stdout);
-+}
-+
- static const char * const microblaze_register_names[] =
- {
-   "r0",   "r1",  "r2",    "r3",   "r4",   "r5",   "r6",   "r7",
-@@ -85,9 +172,21 @@ static const char * const microblaze_register_names[] =
- static unsigned int microblaze_debug_flag = 0;
- int reg_size = 4;
- 
-+unsigned int
-+microblaze_abi_regsize (struct gdbarch *gdbarch)
-+{
-+  switch (microblaze_abi (gdbarch))
-+    {
-+    case MICROBLAZE_ABI_M64:
-+      return 8;
-+    default:
-+      return 4;
-+    }
-+}
-+
- #define microblaze_debug(fmt, ...) \
-   debug_prefixed_printf_cond_nofunc (microblaze_debug_flag, "MICROBLAZE", \
--                                    fmt, ## __VA_ARGS__)
-+                                     fmt, ## __VA_ARGS__)
- 
- 
- /* Return the name of register REGNUM.  */
-@@ -868,15 +967,30 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
- {
-   struct gdbarch *gdbarch;
-   tdesc_arch_data_up tdesc_data;
-+  enum microblaze_abi microblaze_abi, found_abi, wanted_abi;
-   const struct target_desc *tdesc = info.target_desc;
- 
-+ /* What has the user specified from the command line?  */
-+  wanted_abi = global_microblaze_abi ();
-+  if (gdbarch_debug)
-+    fprintf_unfiltered (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n",
-+                        wanted_abi);
-+  if (wanted_abi != MICROBLAZE_ABI_AUTO)
-+    microblaze_abi = wanted_abi;
-+
-   /* If there is already a candidate, use it.  */
-   arches = gdbarch_list_lookup_by_info (arches, &info);
--  if (arches != NULL)
-+  if ((arches != NULL) && (microblaze_abi != MICROBLAZE_ABI_M64))
-     return arches->gdbarch;
-+
-+  if (microblaze_abi == MICROBLAZE_ABI_M64)
-+    {
-+          tdesc = tdesc_microblaze64;
-+          reg_size = 8;
-+    }
-   if (tdesc == NULL)
-     {
--      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) 
-+      if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) 
-         {
-          tdesc = tdesc_microblaze64;
-           reg_size = 8;
-@@ -891,7 +1005,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-       int valid_p;
-       int i;
- 
--      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
-+      if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64))
-         feature = tdesc_find_feature (tdesc,
-                                     "org.gnu.gdb.microblaze64.core");
-       else
-@@ -905,7 +1019,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-       for (i = 0; i < MICROBLAZE_NUM_REGS; i++)
-         valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), i,
-                                             microblaze_register_names[i]);
--      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
-+      if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64))
-         feature = tdesc_find_feature (tdesc,
-                                     "org.gnu.gdb.microblaze64.stack-protect");
-       else
-@@ -955,7 +1069,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-       set_gdbarch_ptr_bit (gdbarch, 64);
-     break;
-     }
--
-+  if(microblaze_abi == MICROBLAZE_ABI_M64)
-+    set_gdbarch_ptr_bit (gdbarch, 64);
-   
-   /* Map Dwarf2 registers to GDB registers.  */
-   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum);
-@@ -1014,7 +1129,38 @@ void
- _initialize_microblaze_tdep ()
- {
-   register_gdbarch_init (bfd_arch_microblaze, microblaze_gdbarch_init);
-+// static struct cmd_list_element *setmicroblazecmdlist = NULL;
-+// static struct cmd_list_element *showmicroblazecmdlist = NULL;
-+
-+  /* Add root prefix command for all "set microblaze"/"show microblaze" commands.  */
- 
-+  add_setshow_prefix_cmd ("microblaze", no_class,
-+                        _("Various microblaze specific commands."),
-+                        _("Various microblaze specific commands."),
-+                        &setmicroblazecmdlist,&showmicroblazecmdlist,
-+                        &setlist,&showlist);
-+#if 0
-+  add_prefix_cmd ("microblaze", no_class, set_microblaze_command,
-+                  _("Various microblaze specific commands."),
-+                  &setmicroblazecmdlist, "set microblaze ", 0, &setlist);
-+
-+  add_prefix_cmd ("microblaze", no_class, show_microblaze_command,
-+                  _("Various microblaze specific commands."),
-+                  &showmicroblazecmdlist, "show microblaze ", 0, &showlist);
-+#endif
-+
-+  /* Allow the user to override the ABI.  */
-+  add_setshow_enum_cmd ("abi", class_obscure, microblaze_abi_strings,
-+                        &microblaze_abi_string, _("\
-+Set the microblaze ABI used by this program."), _("\
-+Show the microblaze ABI used by this program."), _("\
-+This option can be set to one of:\n\
-+  auto  - the default ABI associated with the current binary\n\
-+  m64"),
-+                       microblaze_abi_update,
-+                      show_microblaze_abi,
-+                       &setmicroblazecmdlist, &showmicroblazecmdlist);
-+  
-   initialize_tdesc_microblaze_with_stack_protect ();
-   initialize_tdesc_microblaze ();
-   initialize_tdesc_microblaze64_with_stack_protect ();
-@@ -1029,5 +1175,4 @@ When non-zero, microblaze specific debugging is enabled."),
-                             NULL,
-                             &setdebuglist, &showdebuglist);
- 
--
- }
-diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
-index f4d810303ca..babd6c36926 100644
---- a/gdb/microblaze-tdep.h
-+++ b/gdb/microblaze-tdep.h
-@@ -19,9 +19,17 @@
- 
- #ifndef MICROBLAZE_TDEP_H
- #define MICROBLAZE_TDEP_H 1
--
-+#include "objfiles.h"
- #include "gdbarch.h"
- 
-+struct gdbarch;
-+enum microblaze_abi
-+  {
-+    MICROBLAZE_ABI_AUTO = 0,
-+    MICROBLAZE_ABI_M64,
-+ };
-+
-+enum microblaze_abi microblaze_abi (struct gdbarch *gdbarch);
- /* Microblaze architecture-specific information.  */
- struct microblaze_gregset
- {
-@@ -35,11 +43,14 @@ struct microblaze_gdbarch_tdep : gdbarch_tdep
- {
-   int dummy;           // declare something.
- 
-+  enum microblaze_abi microblaze_abi {};
-+  enum microblaze_abi found_abi {};
-   /* Register sets.  */
-   struct regset *gregset;
-   size_t sizeof_gregset;
-   struct regset *fpregset;
-   size_t sizeof_fpregset;
-+  int register_size;
- };
- 
- /* Register numbers.  */
--- 
-2.37.1 (Apple Git-137.1)
-
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0006-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch
index 9d12cc53..27c04153 100644
--- a/meta-microblaze/recipes-devtools/gdb/gdb/0006-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch
@@ -1,23 +1,20 @@
-From ef411b49f3b2c9e4048eb273f43ab4ee96f96b7e Mon Sep 17 00:00:00 2001
+From b6735e00ff7c60f8e66527402dd541b4217ce38f Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 19 Apr 2021 14:33:27 +0530
-Subject: [PATCH 6/8] [Patch,MicroBlaze] : these changes will make 64 bit
- vectors as default target types when we built gdb with microblaze 64 bit type
- targets,for instance microblaze-xilinx-elf64/microblazeel-xilinx-elf64
-
-Upstream-Status: Pending
-
-Signed-off-by: Mark Hatle <mark.hatle@amd.com>
+Subject: [PATCH 07/54] these changes will make 64 bit vectors as default
+ target types when we built gdb with microblaze 64 bit type targets,for
+ instance microblaze-xilinx-elf64/microblazeel-xilinx-elf64
 
+Signed-off-by: Aayush Misra <aayushm@amd.com>
 ---
  bfd/config.bfd | 8 ++++++++
  1 file changed, 8 insertions(+)
 
 diff --git a/bfd/config.bfd b/bfd/config.bfd
-index 5e9ba3d9805..deb3d078439 100644
+index 3a7d427778c..9a4b26be8f8 100644
 --- a/bfd/config.bfd
 +++ b/bfd/config.bfd
-@@ -856,7 +856,15 @@ case "${targ}" in
+@@ -880,7 +880,15 @@ case "${targ}" in
      targ_defvec=metag_elf32_vec
      targ_underscore=yes
      ;;
@@ -34,5 +31,5 @@ index 5e9ba3d9805..deb3d078439 100644
      targ_defvec=microblaze_elf32_le_vec
      targ_selvecs=microblaze_elf32_vec
 -- 
-2.37.1 (Apple Git-137.1)
+2.34.1
 
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0005-Patch-microblaze-Adding-64-bit-MB-support.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch
index 6eea28fe..54e53f6f 100644
--- a/meta-microblaze/recipes-devtools/gdb/gdb/0005-Patch-microblaze-Adding-64-bit-MB-support.patch
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch
@@ -1,591 +1,21 @@
-From 6aadc445a00275c37112e431c6a29f5a331e6e16 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Thu, 31 Jan 2019 14:36:00 +0530
-Subject: [PATCH 5/8] [Patch, microblaze]: Adding 64 bit MB support Added new
- architecture to Microblaze 64-bit support to GDB Signed-off-by :Nagaraju
- Mekala <nmekala@xilix.com> Signed-off-by :Mahesh Bodapati
- <mbodapat@xilinx.com>
+From 89f7a0c3e8b3bc37a37280bacec724f764503f38 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 9 Nov 2021 16:19:17 +0530
+Subject: [PATCH 08/54] Added m64 abi for 64 bit target descriptions. set m64
+ abi for 64 bit elf.
 
 Conflicts:
-        gdb/Makefile.in
-
-Conflicts:
-        bfd/cpu-microblaze.c
         gdb/microblaze-tdep.c
-        ld/Makefile.am
-        ld/Makefile.in
-        opcodes/microblaze-dis.c
-
-Conflicts:
-        bfd/configure
-        gas/config/tc-microblaze.c
-        ld/Makefile.in
-        opcodes/microblaze-opcm.h
-
-Conflicts:
-        gdb/microblaze-tdep.c
-
-Conflicts:
-        bfd/elf32-microblaze.c
-        gas/config/tc-microblaze.c
-        gdb/features/Makefile
-        gdb/features/microblaze-with-stack-protect.c
-        gdb/microblaze-tdep.c
-        gdb/regformats/microblaze-with-stack-protect.dat
-        gdbserver/linux-microblaze-low.c
-        include/elf/common.h
-Upstream-Status: Pending
-
-Signed-off-by: Mark Hatle <mark.hatle@amd.com>
+        gdb/microblaze-tdep.h
 
+Signed-off-by: Aayush Misra <aayushm@amd.com>
 ---
- bfd/Makefile.am                               |    2 +
- bfd/Makefile.in                               |    3 +
- bfd/archures.c                                |    2 +
- bfd/bfd-in2.h                                 |   31 +-
- bfd/config.bfd                                |    4 +
- bfd/configure                                 |    2 +
- bfd/cpu-microblaze.c                          |   55 +-
- bfd/elf32-microblaze.c                        |  162 +-
- bfd/elf64-microblaze.c                        | 3810 +++++++++++++++++
- bfd/libbfd.h                                  |    3 +
- bfd/reloc.c                                   |   20 +
- bfd/targets.c                                 |    6 +
- gdb/features/Makefile                         |    2 +
- gdb/features/microblaze-core.xml              |    6 +-
- gdb/features/microblaze-stack-protect.xml     |    4 +-
- gdb/features/microblaze-with-stack-protect.c  |    8 +-
- gdb/features/microblaze.c                     |    6 +-
- gdb/features/microblaze64-core.xml            |   69 +
- gdb/features/microblaze64-stack-protect.xml   |   12 +
- .../microblaze64-with-stack-protect.c         |   79 +
- .../microblaze64-with-stack-protect.xml       |   12 +
- gdb/features/microblaze64.c                   |   77 +
- gdb/features/microblaze64.xml                 |   11 +
- gdb/microblaze-linux-tdep.c                   |   36 +-
- gdb/microblaze-tdep.c                         |  126 +-
- gdb/microblaze-tdep.h                         |    4 +-
- include/elf/common.h                          |    1 +
- include/elf/microblaze.h                      |    4 +
- opcodes/microblaze-dis.c                      |   51 +-
- opcodes/microblaze-opc.h                      |  180 +-
- opcodes/microblaze-opcm.h                     |   36 +-
- 31 files changed, 4729 insertions(+), 95 deletions(-)
+ bfd/elf64-microblaze.c | 3810 ++++++++++++++++++++++++++++++++++++++++
+ gdb/microblaze-tdep.c  |  160 +-
+ gdb/microblaze-tdep.h  |   13 +-
+ 3 files changed, 3975 insertions(+), 8 deletions(-)
  create mode 100755 bfd/elf64-microblaze.c
- create mode 100644 gdb/features/microblaze64-core.xml
- create mode 100644 gdb/features/microblaze64-stack-protect.xml
- create mode 100644 gdb/features/microblaze64-with-stack-protect.c
- create mode 100644 gdb/features/microblaze64-with-stack-protect.xml
- create mode 100644 gdb/features/microblaze64.c
- create mode 100644 gdb/features/microblaze64.xml
 
-diff --git a/bfd/Makefile.am b/bfd/Makefile.am
-index b9a3f8207ac..2ddd7891661 100644
---- a/bfd/Makefile.am
-+++ b/bfd/Makefile.am
-@@ -571,6 +571,7 @@ BFD64_BACKENDS = \
-        elf64-riscv.lo \
-        elfxx-riscv.lo \
-        elf64-s390.lo \
-+       elf64-microblaze.lo \
-        elf64-sparc.lo \
-        elf64-tilegx.lo \
-        elf64-x86-64.lo \
-@@ -608,6 +609,7 @@ BFD64_BACKENDS_CFILES = \
-        elf64-nfp.c \
-        elf64-ppc.c \
-        elf64-s390.c \
-+       elf64-microblaze.c \
-        elf64-sparc.c \
-        elf64-tilegx.c \
-        elf64-x86-64.c \
-diff --git a/bfd/Makefile.in b/bfd/Makefile.in
-index 934dd4bc066..7efb10f111d 100644
---- a/bfd/Makefile.in
-+++ b/bfd/Makefile.in
-@@ -1040,6 +1040,7 @@ BFD64_BACKENDS = \
-        elf64-riscv.lo \
-        elfxx-riscv.lo \
-        elf64-s390.lo \
-+       elf64-microblaze.lo \
-        elf64-sparc.lo \
-        elf64-tilegx.lo \
-        elf64-x86-64.lo \
-@@ -1077,6 +1078,7 @@ BFD64_BACKENDS_CFILES = \
-        elf64-nfp.c \
-        elf64-ppc.c \
-        elf64-s390.c \
-+       elf64-microblaze.c \
-        elf64-sparc.c \
-        elf64-tilegx.c \
-        elf64-x86-64.c \
-@@ -1664,6 +1666,7 @@ distclean-compile:
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ppc.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-riscv.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-s390.Plo@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-microblaze.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sparc.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-tilegx.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-x86-64.Plo@am__quote@
-diff --git a/bfd/archures.c b/bfd/archures.c
-index fac9fe82a08..1790c741c58 100644
---- a/bfd/archures.c
-+++ b/bfd/archures.c
-@@ -524,6 +524,8 @@ DESCRIPTION
- .  bfd_arch_lm32,      {* Lattice Mico32.  *}
- .#define bfd_mach_lm32         1
- .  bfd_arch_microblaze,{* Xilinx MicroBlaze.  *}
-+.#define bfd_mach_microblaze   1
-+.#define bfd_mach_microblaze64 2
- .  bfd_arch_tilepro,   {* Tilera TILEPro.  *}
- .  bfd_arch_tilegx,    {* Tilera TILE-Gx.  *}
- .#define bfd_mach_tilepro      1
-diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index c0b563aec02..ccaeecb9476 100644
---- a/bfd/bfd-in2.h
-+++ b/bfd/bfd-in2.h
-@@ -1903,6 +1903,8 @@ enum bfd_architecture
-   bfd_arch_lm32,      /* Lattice Mico32.  */
- #define bfd_mach_lm32          1
-   bfd_arch_microblaze,/* Xilinx MicroBlaze.  */
-+#define bfd_mach_microblaze    1
-+#define bfd_mach_microblaze64  2
-   bfd_arch_tilepro,   /* Tilera TILEPro.  */
-   bfd_arch_tilegx,    /* Tilera TILE-Gx.  */
- #define bfd_mach_tilepro       1
-@@ -5443,16 +5445,41 @@ value relative to the read-write small data area anchor  */
- expressions of the form "Symbol Op Symbol"  */
-   BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
- 
--/* This is a 64 bit reloc that stores the 32 bit pc relative
-+/* This is a 32 bit reloc that stores the 32 bit pc relative
- value in two words (with an imm instruction).  No relocation is
- done here - only used for relaxing  */
--  BFD_RELOC_MICROBLAZE_64_NONE,
-+  BFD_RELOC_MICROBLAZE_32_NONE,
-+
-+/* This is a 64 bit reloc that stores the 32 bit pc relative
-+ *  +value in two words (with an imml instruction).  No relocation is
-+ *   +done here - only used for relaxing  */
-+    BFD_RELOC_MICROBLAZE_64_PCREL,
-+
-+/* This is a 64 bit reloc that stores the 32 bit relative
-+ *  +value in two words (with an imml instruction).  No relocation is
-+ *   +done here - only used for relaxing  */
-+    BFD_RELOC_MICROBLAZE_64,
-+
-+/* This is a 64 bit reloc that stores the 32 bit relative
-+ *  +value in two words (with an imml instruction).  No relocation is
-+ *   +done here - only used for relaxing  */
-+    BFD_RELOC_MICROBLAZE_EA64,
-+
-+/* This is a 64 bit reloc that stores the 32 bit pc relative
-+ *  +value in two words (with an imm instruction).  No relocation is
-+ *   +done here - only used for relaxing  */
-+    BFD_RELOC_MICROBLAZE_64_NONE,
- 
- /* This is a 64 bit reloc that stores the 32 bit pc relative
- value in two words (with an imm instruction).  The relocation is
- PC-relative GOT offset  */
-   BFD_RELOC_MICROBLAZE_64_GOTPC,
- 
-+/* This is a 64 bit reloc that stores the 32 bit pc relative
-+value in two words (with an imml instruction).  The relocation is
-+PC-relative GOT offset  */
-+  BFD_RELOC_MICROBLAZE_64_GPC,
-+
- /* This is a 64 bit reloc that stores the 32 bit pc relative
- value in two words (with an imm instruction).  The relocation is
- GOT offset  */
-diff --git a/bfd/config.bfd b/bfd/config.bfd
-index 872685cfb72..5e9ba3d9805 100644
---- a/bfd/config.bfd
-+++ b/bfd/config.bfd
-@@ -860,11 +860,15 @@ case "${targ}" in
-   microblazeel*-*)
-     targ_defvec=microblaze_elf32_le_vec
-     targ_selvecs=microblaze_elf32_vec
-+    targ64_selvecs=microblaze_elf64_vec
-+    targ64_selvecs=microblaze_elf64_le_vec
-     ;;
- 
-   microblaze*-*)
-     targ_defvec=microblaze_elf32_vec
-     targ_selvecs=microblaze_elf32_le_vec
-+    targ64_selvecs=microblaze_elf64_vec
-+    targ64_selvecs=microblaze_elf64_le_vec
-     ;;
- 
- #ifdef BFD64
-diff --git a/bfd/configure b/bfd/configure
-index 0ef4c206fb0..b7547c6777c 100755
---- a/bfd/configure
-+++ b/bfd/configure
-@@ -13547,6 +13547,8 @@ do
-     rx_elf32_linux_le_vec)      tb="$tb elf32-rx.lo elf32.lo $elf" ;;
-     s390_elf32_vec)             tb="$tb elf32-s390.lo elf32.lo $elf" ;;
-     s390_elf64_vec)             tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;;
-+    microblaze_elf64_vec)       tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
-+    microblaze_elf64_le_vec)    tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
-     score_elf32_be_vec)                 tb="$tb elf32-score.lo elf32-score7.lo elf32.lo elf64.lo $elf"; want64=true; target_size=64 ;;
-     score_elf32_le_vec)                 tb="$tb elf32-score.lo elf32-score7.lo elf32.lo elf64.lo $elf"; want64=true; target_size=64 ;;
-     sh_coff_vec)                tb="$tb coff-sh.lo $coff" ;;
-diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c
-index 0c1d2b1aa69..106f78229b5 100644
---- a/bfd/cpu-microblaze.c
-+++ b/bfd/cpu-microblaze.c
-@@ -23,13 +23,30 @@
- #include "bfd.h"
- #include "libbfd.h"
- 
--const bfd_arch_info_type bfd_microblaze_arch =
-+const bfd_arch_info_type bfd_microblaze_arch[] =
-+{
-+#if BFD_DEFAULT_TARGET_SIZE == 64
-+{
-+  64,                          /* 32 bits in a word.  */
-+  64,                          /* 32 bits in an address.  */
-+  8,                           /* 8 bits in a byte.  */
-+  bfd_arch_microblaze,         /* Architecture.  */
-+  bfd_mach_microblaze64,       /* 64 bit Machine */
-+  "microblaze",                        /* Architecture name.  */
-+  "MicroBlaze",                        /* Printable name.  */
-+  3,                           /* Section align power.  */
-+  false,                               /* Is this the default architecture ?  */
-+  bfd_default_compatible,      /* Architecture comparison function.  */
-+  bfd_default_scan,            /* String to architecture conversion.  */
-+  bfd_arch_default_fill,       /* Default fill.  */
-+  &bfd_microblaze_arch[1]      /* Next in list.  */
-+},
- {
-   32,                          /* Bits in a word.  */
-   32,                          /* Bits in an address.  */
-   8,                           /* Bits in a byte.  */
-   bfd_arch_microblaze,         /* Architecture number.  */
--  0,                           /* Machine number - 0 for now.  */
-+  bfd_mach_microblaze,         /* Machine number - 0 for now.  */
-   "microblaze",                        /* Architecture name.  */
-   "MicroBlaze",                        /* Printable name.  */
-   3,                           /* Section align power.  */
-@@ -39,4 +56,38 @@ const bfd_arch_info_type bfd_microblaze_arch =
-   bfd_arch_default_fill,       /* Default fill.  */
-   NULL,                                /* Next in list.  */
-   0 /* Maximum offset of a reloc from the start of an insn.  */
-+}
-+#else
-+{
-+  32,                          /* 32 bits in a word.  */
-+  32,                          /* 32 bits in an address.  */
-+  8,                           /* 8 bits in a byte.  */
-+  bfd_arch_microblaze,                 /* Architecture.  */
-+  bfd_mach_microblaze,         /* 32 bit Machine */
-+  "microblaze",                        /* Architecture name.  */
-+  "MicroBlaze",                        /* Printable name.  */
-+  3,                           /* Section align power.  */
-+  true,                                /* Is this the default architecture ?  */
-+  bfd_default_compatible,      /* Architecture comparison function.  */
-+  bfd_default_scan,            /* String to architecture conversion.  */
-+  bfd_arch_default_fill,       /* Default fill.  */
-+  &bfd_microblaze_arch[1]      /* Next in list.  */
-+},
-+{
-+  64,                          /* 32 bits in a word.  */
-+  64,                          /* 32 bits in an address.  */
-+  8,                           /* 8 bits in a byte.  */
-+  bfd_arch_microblaze,         /* Architecture.  */
-+  bfd_mach_microblaze64,       /* 64 bit Machine */
-+  "microblaze",                        /* Architecture name.  */
-+  "MicroBlaze",                        /* Printable name.  */
-+  3,                           /* Section align power.  */
-+  false,                               /* Is this the default architecture ?  */
-+  bfd_default_compatible,      /* Architecture comparison function.  */
-+  bfd_default_scan,            /* String to architecture conversion.  */
-+  bfd_arch_default_fill,       /* Default fill.  */
-+  NULL,                                /* Next in list.  */
-+  0
-+}
-+#endif
- };
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index d3b3c66cf00..053c1b432f9 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -114,6 +114,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
-          0x0000ffff,           /* Dest Mask.  */
-          true),                /* PC relative offset?  */
- 
-+   HOWTO (R_MICROBLAZE_IMML_64,        /* Type.  */
-+          0,                   /* Rightshift.  */
-+          2,                   /* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,                  /* Bitsize.  */
-+          true,                /* PC_relative.  */
-+          0,                   /* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_IMML_64",      /* Name.  */
-+          false,               /* Partial Inplace.  */
-+          0,                   /* Source Mask.  */
-+          0x0000ffff,          /* Dest Mask.  */
-+          false),              /* PC relative offset?  */
-+
-    /* A 64 bit relocation.  Table entry not really used.  */
-    HOWTO (R_MICROBLAZE_64,     /* Type.  */
-          0,                    /* Rightshift.  */
-@@ -174,7 +188,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
-          0x0000ffff,           /* Dest Mask.  */
-          false),               /* PC relative offset?  */
- 
--   /* This reloc does nothing. Used for relaxation.  */
-+   HOWTO (R_MICROBLAZE_32_NONE,   /* Type.  */
-+          0,         /* Rightshift.  */
-+          2,            /* Size (0 = byte, 1 = short, 2 = long).  */
-+          32,           /* Bitsize.  */
-+          true,         /* PC_relative.  */
-+          0,           /* Bitpos.  */
-+          complain_overflow_bitfield,  /* Complain on overflow.  */
-+          NULL,                  /* Special Function.  */
-+          "R_MICROBLAZE_32_NONE",/* Name.  */
-+          false,       /* Partial Inplace.  */
-+          0,          /* Source Mask.  */
-+          0,         /* Dest Mask.  */
-+          false),       /* PC relative offset?  */
-+
-+   /* This reloc does nothing.  Used for relaxation.  */
-    HOWTO (R_MICROBLAZE_64_NONE,        /* Type.  */
-          0,                    /* Rightshift.  */
-          3,                    /* Size (0 = byte, 1 = short, 2 = long).  */
-@@ -264,6 +292,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
-          0x0000ffff,           /* Dest Mask.  */
-          true),                /* PC relative offset?  */
- 
-+   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_GPC_64,         /* Type.  */
-+          0,                   /* Rightshift.  */
-+          2,                   /* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,                  /* Bitsize.  */
-+          true,                        /* PC_relative.  */
-+          0,                   /* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,       /* Special Function.  */
-+          "R_MICROBLAZE_GPC_64",       /* Name.  */
-+          false,               /* Partial Inplace.  */
-+          0,                   /* Source Mask.  */
-+          0x0000ffff,          /* Dest Mask.  */
-+          true),               /* PC relative offset?  */
-+
-    /* A 64 bit GOT relocation.  Table-entry not really used.  */
-    HOWTO (R_MICROBLAZE_GOT_64,  /* Type.  */
-          0,                    /* Rightshift.  */
-@@ -560,6 +603,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
-     case BFD_RELOC_NONE:
-       microblaze_reloc = R_MICROBLAZE_NONE;
-       break;
-+    case BFD_RELOC_MICROBLAZE_32_NONE:
-+      microblaze_reloc = R_MICROBLAZE_32_NONE;
-+      break;
-     case BFD_RELOC_MICROBLAZE_64_NONE:
-       microblaze_reloc = R_MICROBLAZE_64_NONE;
-       break;
-@@ -600,9 +646,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
-     case BFD_RELOC_VTABLE_ENTRY:
-       microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
-       break;
-+    case BFD_RELOC_MICROBLAZE_64:
-+      microblaze_reloc = R_MICROBLAZE_IMML_64;
-+      break;
-     case BFD_RELOC_MICROBLAZE_64_GOTPC:
-       microblaze_reloc = R_MICROBLAZE_GOTPC_64;
-       break;
-+    case BFD_RELOC_MICROBLAZE_64_GPC:
-+      microblaze_reloc = R_MICROBLAZE_GPC_64;
-+      break;
-     case BFD_RELOC_MICROBLAZE_64_GOT:
-       microblaze_reloc = R_MICROBLAZE_GOT_64;
-       break;
-@@ -1507,9 +1559,9 @@ microblaze_elf_relocate_section (bfd *output_bfd,
-              relocation += addend;
-              relocation -= dtprel_base(info);
-              bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
--                         contents + offset + 2);
-+                         contents + offset + endian);
-              bfd_put_16 (input_bfd, relocation & 0xffff,
--                         contents + offset + 2 + INST_WORD_SIZE);
-+                         contents + offset + endian + INST_WORD_SIZE);
-              break;
-            case (int) R_MICROBLAZE_TEXTREL_64:
-            case (int) R_MICROBLAZE_TEXTREL_32_LO:
-@@ -1523,7 +1575,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
-                if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0)
-                  {
-                    relocation += addend;
--                   if (r_type == R_MICROBLAZE_32)
-+                   if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64)
-                      bfd_put_32 (input_bfd, relocation, contents + offset);
-                    else
-                      {
-@@ -1925,8 +1977,7 @@ microblaze_elf_relax_section (bfd *abfd,
-       else
-        symval += irel->r_addend;
- 
--      if ((symval & 0xffff8000) == 0
--         || (symval & 0xffff8000) == 0xffff8000)
-+      if ((symval & 0xffff8000) == 0)
-        {
-          /* We can delete this instruction.  */
-          sec->relax[sec->relax_count].addr = irel->r_offset;
-@@ -1990,21 +2041,51 @@ microblaze_elf_relax_section (bfd *abfd,
-                    irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
-                }
-              break;
-+           case R_MICROBLAZE_IMML_64:
-+             {
-+               /* This was a PC-relative instruction that was
-+                  completely resolved.  */
-+               int sfix, efix;
-+            unsigned int val;
-+               bfd_vma target_address;
-+               target_address = irel->r_addend + irel->r_offset;
-+               sfix = calc_fixup (irel->r_offset, 0, sec);
-+               efix = calc_fixup (target_address, 0, sec);
-+
-+            /* Validate the in-band val.  */
-+            val = bfd_get_32 (abfd, contents + irel->r_offset);
-+            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
-+               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
-+            }
-+               irel->r_addend -= (efix - sfix);
-+               /* Should use HOWTO.  */
-+               microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
-+                                                  irel->r_addend);
-+             }
-+             break;
-            case R_MICROBLAZE_NONE:
-+           case R_MICROBLAZE_32_NONE:
-              {
-                /* This was a PC-relative instruction that was
-                   completely resolved.  */
-                int sfix, efix;
-+               unsigned int val;
-                bfd_vma target_address;
-                target_address = irel->r_addend + irel->r_offset;
-                sfix = calc_fixup (irel->r_offset, 0, sec);
-                efix = calc_fixup (target_address, 0, sec);
-+
-+               /* Validate the in-band val.  */
-+               val = bfd_get_32 (abfd, contents + irel->r_offset);
-+               if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
-+                      fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
-+               }
-                irel->r_addend -= (efix - sfix);
-                /* Should use HOWTO.  */
-                microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
-                                                   irel->r_addend);
--             }
--             break;
-+               }
-+               break;
-            case R_MICROBLAZE_64_NONE:
-              {
-                /* This was a PC-relative 64-bit instruction that was
-@@ -2015,8 +2096,8 @@ microblaze_elf_relax_section (bfd *abfd,
-                sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec);
-                efix = calc_fixup (target_address, 0, sec);
-                irel->r_addend -= (efix - sfix);
--    microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset
--                                      + INST_WORD_SIZE, irel->r_addend);
-+    microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
-+                                       irel->r_addend);
-              }
-              break;
-            }
-@@ -2046,9 +2127,50 @@ microblaze_elf_relax_section (bfd *abfd,
-          irelscanend = irelocs + o->reloc_count;
-          for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
-            {
--             if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
--               {
--                 isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
-+             if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
-+                {
-+                  unsigned int val;
-+
-+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
-+
-+                  /* hax: We only do the following fixup for debug location lists.  */
-+                  if (strcmp(".debug_loc", o->name))
-+                    continue;
-+
-+                  /* This was a PC-relative instruction that was completely resolved.  */
-+                  if (ocontents == NULL)
-+                    {
-+                      if (elf_section_data (o)->this_hdr.contents != NULL)
-+                          ocontents = elf_section_data (o)->this_hdr.contents;
-+                      else
-+                        {
-+                          /* We always cache the section contents.
-+                             Perhaps, if info->keep_memory is FALSE, we
-+                             should free them, if we are permitted to.  */
-+
-+                          if (o->rawsize == 0)
-+                              o->rawsize = o->size;
-+                          ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
-+                          if (ocontents == NULL)
-+                              goto error_return;
-+                          if (!bfd_get_section_contents (abfd, o, ocontents,
-+                                                         (file_ptr) 0,
-+                                                         o->rawsize))
-+                              goto error_return;
-+                         elf_section_data (o)->this_hdr.contents = ocontents;
-+                       }
-+                   }
-+                  val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
-+                  if (val != irelscan->r_addend) {
-+                    fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
-+                  }
-+                  irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
-+                  microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
-+                                                     irelscan->r_addend);
-+              }
-+              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)// || ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64)
-+                {
-+                 isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
- 
-                  /* Look at the reloc only if the value has been resolved.  */
-                  if (isym->st_shndx == shndx
-@@ -2105,7 +2227,7 @@ microblaze_elf_relax_section (bfd *abfd,
-                              elf_section_data (o)->this_hdr.contents = ocontents;
-                            }
-                        }
--                     irelscan->r_addend -= calc_fixup (irel->r_addend
-+              irelscan->r_addend -= calc_fixup (irelscan->r_addend
-                                                        + isym->st_value,
-                                                        0,
-                                                        sec);
-@@ -3445,6 +3567,14 @@ microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
-   return true;
- }
- 
-+
-+static bool
-+elf_microblaze_object_p (bfd *abfd)
-+{
-+  /* Set the right machine number for an s390 elf32 file.  */
-+  return bfd_default_set_arch_mach (abfd, bfd_arch_microblaze, bfd_mach_microblaze);
-+}
-+
- /* Hook called by the linker routine which adds symbols from an object
-    file.  We use it to put .comm items in .sbss, and not .bss.  */
- 
-@@ -3514,8 +3644,6 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
- #define elf_backend_finish_dynamic_symbol      microblaze_elf_finish_dynamic_symbol
- #define elf_backend_size_dynamic_sections      microblaze_elf_size_dynamic_sections
- #define elf_backend_add_symbol_hook            microblaze_elf_add_symbol_hook
--
--#define elf_backend_grok_prstatus               microblaze_elf_grok_prstatus
--#define elf_backend_grok_psinfo                 microblaze_elf_grok_psinfo
-+#define elf_backend_object_p                   elf_microblaze_object_p
- 
- #include "elf32-target.h"
 diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
 new file mode 100755
 index 00000000000..6cd9753a592
@@ -4402,1388 +3832,273 @@ index 00000000000..6cd9753a592
 +#define elf_backend_add_symbol_hook            microblaze_elf_add_symbol_hook
 +
 +#include "elf64-target.h"
-diff --git a/bfd/libbfd.h b/bfd/libbfd.h
-index 6e62e556962..ef5568a78b0 100644
---- a/bfd/libbfd.h
-+++ b/bfd/libbfd.h
-@@ -2992,6 +2992,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
-   "BFD_RELOC_MICROBLAZE_32_ROSDA",
-   "BFD_RELOC_MICROBLAZE_32_RWSDA",
-   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
-+  "BFD_RELOC_MICROBLAZE_32_NONE",
-   "BFD_RELOC_MICROBLAZE_64_NONE",
-   "BFD_RELOC_MICROBLAZE_64_GOTPC",
-   "BFD_RELOC_MICROBLAZE_64_GOT",
-@@ -2999,6 +3000,8 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
-   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
-   "BFD_RELOC_MICROBLAZE_32_GOTOFF",
-   "BFD_RELOC_MICROBLAZE_COPY",
-+  "BFD_RELOC_MICROBLAZE_64",
-+  "BFD_RELOC_MICROBLAZE_64_PCREL",
-   "BFD_RELOC_MICROBLAZE_64_TLS",
-   "BFD_RELOC_MICROBLAZE_64_TLSGD",
-   "BFD_RELOC_MICROBLAZE_64_TLSLD",
-diff --git a/bfd/reloc.c b/bfd/reloc.c
-index 164060361a9..e733e2397f4 100644
---- a/bfd/reloc.c
-+++ b/bfd/reloc.c
-@@ -6898,6 +6898,12 @@ ENUM
- ENUMDOC
-   This is a 32 bit reloc for the microblaze to handle
-   expressions of the form "Symbol Op Symbol"
-+ENUM
-+  BFD_RELOC_MICROBLAZE_32_NONE
-+ENUMDOC
-+  This is a 32 bit reloc that stores the 32 bit pc relative
-+  value in two words (with an imm instruction).  No relocation is
-+  done here - only used for relaxing
- ENUM
-   BFD_RELOC_MICROBLAZE_64_NONE
- ENUMDOC
-@@ -6991,6 +6997,20 @@ ENUMDOC
-   value in two words (with an imm instruction).  The relocation is
-   relative offset from start of TEXT.
- 
-+  This is a 64 bit reloc that stores 64-bit thread pointer relative offset
-+  to two words (uses imml instruction).
-+ENUM
-+BFD_RELOC_MICROBLAZE_64,
-+ENUMDOC
-+ This is a 64 bit reloc that stores the 64 bit pc relative
-+ value in two words (with an imml instruction).  No relocation is
-+ done here - only used for relaxing
-+ENUM
-+BFD_RELOC_MICROBLAZE_64_PCREL,
-+ENUMDOC
-+ This is a 32 bit reloc that stores the 32 bit pc relative
-+ value in two words (with an imml instruction).  No relocation is
-+ done here - only used for relaxing
- ENUM
-   BFD_RELOC_AARCH64_RELOC_START
- ENUMDOC
-diff --git a/bfd/targets.c b/bfd/targets.c
-index 417743efc0e..333f05c55f4 100644
---- a/bfd/targets.c
-+++ b/bfd/targets.c
-@@ -795,6 +795,8 @@ extern const bfd_target mep_elf32_le_vec;
- extern const bfd_target metag_elf32_vec;
- extern const bfd_target microblaze_elf32_vec;
- extern const bfd_target microblaze_elf32_le_vec;
-+extern const bfd_target microblaze_elf64_vec;
-+extern const bfd_target microblaze_elf64_le_vec;
- extern const bfd_target mips_ecoff_be_vec;
- extern const bfd_target mips_ecoff_le_vec;
- extern const bfd_target mips_ecoff_bele_vec;
-@@ -1165,6 +1167,10 @@ static const bfd_target * const _bfd_target_vector[] =
- 
-        &metag_elf32_vec,
- 
-+#ifdef BFD64
-+       &microblaze_elf64_vec,
-+       &microblaze_elf64_le_vec,
-+#endif
-        &microblaze_elf32_vec,
- 
-        &mips_ecoff_be_vec,
-diff --git a/gdb/features/Makefile b/gdb/features/Makefile
-index fc3196864c9..1bb198abfd3 100644
---- a/gdb/features/Makefile
-+++ b/gdb/features/Makefile
-@@ -101,7 +101,9 @@ OUTPUTS = $(patsubst %,$(outdir)/%.dat,$(WHICH))
- # to make on the command line.
- XMLTOC = \
-        microblaze-with-stack-protect.xml \
-+       microblaze64-with-stack-protect.xml \
-        microblaze.xml \
-+       microblaze64.xml \
-        mips-dsp-linux.xml \
-        mips-linux.xml \
-        mips64-dsp-linux.xml \
-diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml
-index 29fdd6c0a2f..a5c3cce069d 100644
---- a/gdb/features/microblaze-core.xml
-+++ b/gdb/features/microblaze-core.xml
-@@ -8,7 +8,7 @@
- <!DOCTYPE feature SYSTEM "gdb-target.dtd">
- <feature name="org.gnu.gdb.microblaze.core">
-   <reg name="r0" bitsize="32" regnum="0"/>
--  <reg name="r1" bitsize="32" type="data_ptr"/>
-+  <reg name="r1" bitsize="32"/>
-   <reg name="r2" bitsize="32"/>
-   <reg name="r3" bitsize="32"/>
-   <reg name="r4" bitsize="32"/>
-@@ -39,7 +39,7 @@
-   <reg name="r29" bitsize="32"/>
-   <reg name="r30" bitsize="32"/>
-   <reg name="r31" bitsize="32"/>
--  <reg name="rpc" bitsize="32" type="code_ptr"/>
-+  <reg name="rpc" bitsize="32"/>
-   <reg name="rmsr" bitsize="32"/>
-   <reg name="rear" bitsize="32"/>
-   <reg name="resr" bitsize="32"/>
-@@ -64,4 +64,6 @@
-   <reg name="rtlbsx" bitsize="32"/>
-   <reg name="rtlblo" bitsize="32"/>
-   <reg name="rtlbhi" bitsize="32"/>
-+  <reg name="slr" bitsize="32"/>
-+  <reg name="shr" bitsize="32"/>
- </feature>
-diff --git a/gdb/features/microblaze-stack-protect.xml b/gdb/features/microblaze-stack-protect.xml
-index aac51ea471c..722a51f0df5 100644
---- a/gdb/features/microblaze-stack-protect.xml
-+++ b/gdb/features/microblaze-stack-protect.xml
-@@ -7,6 +7,6 @@
- 
- <!DOCTYPE feature SYSTEM "gdb-target.dtd">
- <feature name="org.gnu.gdb.microblaze.stack-protect">
--  <reg name="rslr" bitsize="32"/>
--  <reg name="rshr" bitsize="32"/>
-+  <reg name="slr" bitsize="32"/>
-+  <reg name="shr" bitsize="32"/>
- </feature>
-diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c
-index aa180bf35d5..6a9e74c7a6f 100644
---- a/gdb/features/microblaze-with-stack-protect.c
-+++ b/gdb/features/microblaze-with-stack-protect.c
-@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
- 
-   feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core");
-   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
--  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
-+  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
-@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
-   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
--  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
-+  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
-@@ -72,8 +72,8 @@ initialize_tdesc_microblaze_with_stack_protect (void)
-   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
- 
-   feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.stack-protect");
--  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 32, "int");
--  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int");
- 
-   tdesc_microblaze_with_stack_protect = result.release ();
- }
-diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c
-index ef2c64c720e..201232dff83 100644
---- a/gdb/features/microblaze.c
-+++ b/gdb/features/microblaze.c
-@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void)
- 
-   feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core");
-   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
--  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
-+  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
-@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void)
-   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
--  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
-+  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
-@@ -70,6 +70,8 @@ initialize_tdesc_microblaze (void)
-   tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 9450882e850..f265e8fc608 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -65,8 +65,95 @@
+ #define IS_SAVE_HIDDEN_PTR(op, rd, ra, rb) \
+   ((op == add || op == addik) && ra == MICROBLAZE_FIRST_ARGREG && rb == 0)
  
-   tdesc_microblaze = result.release ();
- }
-diff --git a/gdb/features/microblaze64-core.xml b/gdb/features/microblaze64-core.xml
-new file mode 100644
-index 00000000000..96e99e2fb24
---- /dev/null
-+++ b/gdb/features/microblaze64-core.xml
-@@ -0,0 +1,69 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
-+
-+     Copying and distribution of this file, with or without modification,
-+     are permitted in any medium without royalty provided the copyright
-+     notice and this notice are preserved.  -->
-+
-+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
-+<feature name="org.gnu.gdb.microblaze64.core">
-+  <reg name="r0" bitsize="64" regnum="0"/>
-+  <reg name="r1" bitsize="64"/>
-+  <reg name="r2" bitsize="64"/>
-+  <reg name="r3" bitsize="64"/>
-+  <reg name="r4" bitsize="64"/>
-+  <reg name="r5" bitsize="64"/>
-+  <reg name="r6" bitsize="64"/>
-+  <reg name="r7" bitsize="64"/>
-+  <reg name="r8" bitsize="64"/>
-+  <reg name="r9" bitsize="64"/>
-+  <reg name="r10" bitsize="64"/>
-+  <reg name="r11" bitsize="64"/>
-+  <reg name="r12" bitsize="64"/>
-+  <reg name="r13" bitsize="64"/>
-+  <reg name="r14" bitsize="64"/>
-+  <reg name="r15" bitsize="64"/>
-+  <reg name="r16" bitsize="64"/>
-+  <reg name="r17" bitsize="64"/>
-+  <reg name="r18" bitsize="64"/>
-+  <reg name="r19" bitsize="64"/>
-+  <reg name="r20" bitsize="64"/>
-+  <reg name="r21" bitsize="64"/>
-+  <reg name="r22" bitsize="64"/>
-+  <reg name="r23" bitsize="64"/>
-+  <reg name="r24" bitsize="64"/>
-+  <reg name="r25" bitsize="64"/>
-+  <reg name="r26" bitsize="64"/>
-+  <reg name="r27" bitsize="64"/>
-+  <reg name="r28" bitsize="64"/>
-+  <reg name="r29" bitsize="64"/>
-+  <reg name="r30" bitsize="64"/>
-+  <reg name="r31" bitsize="64"/>
-+  <reg name="rpc" bitsize="64"/>
-+  <reg name="rmsr" bitsize="32"/>
-+  <reg name="rear" bitsize="64"/>
-+  <reg name="resr" bitsize="32"/>
-+  <reg name="rfsr" bitsize="32"/>
-+  <reg name="rbtr" bitsize="64"/>
-+  <reg name="rpvr0" bitsize="32"/>
-+  <reg name="rpvr1" bitsize="32"/>
-+  <reg name="rpvr2" bitsize="32"/>
-+  <reg name="rpvr3" bitsize="32"/>
-+  <reg name="rpvr4" bitsize="32"/>
-+  <reg name="rpvr5" bitsize="32"/>
-+  <reg name="rpvr6" bitsize="32"/>
-+  <reg name="rpvr7" bitsize="32"/>
-+  <reg name="rpvr8" bitsize="64"/>
-+  <reg name="rpvr9" bitsize="64"/>
-+  <reg name="rpvr10" bitsize="32"/>
-+  <reg name="rpvr11" bitsize="32"/>
-+  <reg name="redr" bitsize="32"/>
-+  <reg name="rpid" bitsize="32"/>
-+  <reg name="rzpr" bitsize="32"/>
-+  <reg name="rtlbx" bitsize="32"/>
-+  <reg name="rtlbsx" bitsize="32"/>
-+  <reg name="rtlblo" bitsize="32"/>
-+  <reg name="rtlbhi" bitsize="32"/>
-+  <reg name="slr" bitsize="64"/>
-+  <reg name="shr" bitsize="64"/>
-+</feature>
-diff --git a/gdb/features/microblaze64-stack-protect.xml b/gdb/features/microblaze64-stack-protect.xml
-new file mode 100644
-index 00000000000..1bbf5fc3cea
---- /dev/null
-+++ b/gdb/features/microblaze64-stack-protect.xml
-@@ -0,0 +1,12 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
-+
-+     Copying and distribution of this file, with or without modification,
-+     are permitted in any medium without royalty provided the copyright
-+     notice and this notice are preserved.  -->
-+
-+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
-+<feature name="org.gnu.gdb.microblaze64.stack-protect">
-+  <reg name="slr" bitsize="64"/>
-+  <reg name="shr" bitsize="64"/>
-+</feature>
-diff --git a/gdb/features/microblaze64-with-stack-protect.c b/gdb/features/microblaze64-with-stack-protect.c
-new file mode 100644
-index 00000000000..a4de4666c76
---- /dev/null
-+++ b/gdb/features/microblaze64-with-stack-protect.c
-@@ -0,0 +1,79 @@
-+/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
-+  Original: microblaze-with-stack-protect.xml */
++static const char *microblaze_abi_string;
 +
-+#include "defs.h"
-+#include "osabi.h"
-+#include "target-descriptions.h"
++static const char *const microblaze_abi_strings[] = {
++  "auto",
++  "m64",
++};
++
++enum microblaze_abi
++microblaze_abi (struct gdbarch *gdbarch)
++{
++  microblaze_gdbarch_tdep *tdep = (microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch);
++  return tdep->microblaze_abi;
++}
+ /* The registers of the Xilinx microblaze processor.  */
+ 
++ static struct cmd_list_element *setmicroblazecmdlist = NULL;
++ static struct cmd_list_element *showmicroblazecmdlist = NULL;
 +
-+struct target_desc *tdesc_microblaze64_with_stack_protect;
 +static void
-+initialize_tdesc_microblaze64_with_stack_protect (void)
++microblaze_abi_update (const char *ignore_args,
++                 int from_tty, struct cmd_list_element *c)
 +{
-+  target_desc_up result = allocate_target_description ();
-+  struct tdesc_feature *feature;
-+
-+  feature = tdesc_create_feature (result.get() , "org.gnu.gdb.microblaze64.core");
-+  tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "int");
-+  tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
-+
-+  feature = tdesc_create_feature (result.get(), "org.gnu.gdb.microblaze64.stack-protect");
-+  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
-+
-+  tdesc_microblaze64_with_stack_protect = result.release();
++  struct gdbarch_info info;
++
++  /* Force the architecture to update, and (if it's a microblaze architecture)
++ *      microblaze_gdbarch_init will take care of the rest.  */
++//  gdbarch_info_init (&info);
++  gdbarch_update_p (info);
 +}
-diff --git a/gdb/features/microblaze64-with-stack-protect.xml b/gdb/features/microblaze64-with-stack-protect.xml
-new file mode 100644
-index 00000000000..0e9f01611f3
---- /dev/null
-+++ b/gdb/features/microblaze64-with-stack-protect.xml
-@@ -0,0 +1,12 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
-+
-+     Copying and distribution of this file, with or without modification,
-+     are permitted in any medium without royalty provided the copyright
-+     notice and this notice are preserved.  -->
-+
-+<!DOCTYPE target SYSTEM "gdb-target.dtd">
-+<target>
-+  <xi:include href="microblaze64-core.xml"/>
-+  <xi:include href="microblaze64-stack-protect.xml"/>
-+</target>
-diff --git a/gdb/features/microblaze64.c b/gdb/features/microblaze64.c
-new file mode 100644
-index 00000000000..8ab7a90dd95
---- /dev/null
-+++ b/gdb/features/microblaze64.c
-@@ -0,0 +1,77 @@
-+/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
-+  Original: microblaze.xml */
 +
-+#include "defs.h"
-+#include "osabi.h"
-+#include "target-descriptions.h"
 +
-+struct target_desc *tdesc_microblaze64;
-+static void
-+initialize_tdesc_microblaze64 (void)
++static enum microblaze_abi
++global_microblaze_abi (void)
 +{
-+  target_desc_up result = allocate_target_description ();
-+  struct tdesc_feature *feature;
-+
-+  feature = tdesc_create_feature (result.get(), "org.gnu.gdb.microblaze64.core");
-+  tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
-+
-+  tdesc_microblaze64 = result.release();
++  int i;
++
++  for (i = 0; microblaze_abi_strings[i] != NULL; i++)
++    if (microblaze_abi_strings[i] == microblaze_abi_string)
++      return (enum microblaze_abi) i;
++
++//  internal_error (__FILE__, __LINE__, _("unknown ABI string"));
 +}
-diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml
-new file mode 100644
-index 00000000000..515d18e65cf
---- /dev/null
-+++ b/gdb/features/microblaze64.xml
-@@ -0,0 +1,11 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
-+
-+     Copying and distribution of this file, with or without modification,
-+     are permitted in any medium without royalty provided the copyright
-+     notice and this notice are preserved.  -->
-+
-+<!DOCTYPE target SYSTEM "gdb-target.dtd">
-+<target>
-+  <xi:include href="microblaze64-core.xml"/>
-+</target>
-diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
-index fc52adffb72..f2db32f0087 100644
---- a/gdb/microblaze-linux-tdep.c
-+++ b/gdb/microblaze-linux-tdep.c
-@@ -40,6 +40,7 @@
- #include "features/microblaze-linux.c"
- 
- static int microblaze_debug_flag = 0;
-+int MICROBLAZE_REGISTER_SIZE=4;
- 
- static void
- microblaze_debug (const char *fmt, ...)
-@@ -55,6 +56,7 @@ microblaze_debug (const char *fmt, ...)
-     }
- }
- 
-+#if 0
- static int
- microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, 
-                                           struct bp_target_info *bp_tgt)
-@@ -86,6 +88,8 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
-   return val;
- }
- 
-+#endif
 +
- static void
- microblaze_linux_sigtramp_cache (struct frame_info *next_frame,
-                                 struct trad_frame_cache *this_cache,
-@@ -147,8 +151,8 @@ microblaze_linux_init_abi (struct gdbarch_info info,
- 
-   linux_init_abi (info, gdbarch, 0);
- 
--  set_gdbarch_memory_remove_breakpoint (gdbarch,
--                                       microblaze_linux_memory_remove_breakpoint);
-+ // set_gdbarch_memory_remove_breakpoint (gdbarch,
-+ //                                    microblaze_linux_memory_remove_breakpoint);
- 
-   /* Shared library handling.  */
-   set_solib_svr4_fetch_link_map_offsets (gdbarch,
-@@ -160,10 +164,30 @@ microblaze_linux_init_abi (struct gdbarch_info info,
- 
-   /* BFD target for core files.  */
-   if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
--    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
-+    {
-+      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
-+          set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblaze");
-+          MICROBLAZE_REGISTER_SIZE=8;
-+        }
++static void
++show_microblaze_abi (struct ui_file *file,
++               int from_tty,
++               struct cmd_list_element *ignored_cmd,
++               const char *ignored_value)
++{
++      enum microblaze_abi global_abi = global_microblaze_abi ();
++      enum microblaze_abi actual_abi = microblaze_abi (target_gdbarch ());
++      const char *actual_abi_str = microblaze_abi_strings[actual_abi];
++
++#if 1 
++      if (global_abi == MICROBLAZE_ABI_AUTO)
++        fprintf_filtered
++          (file,
++           "The microblaze ABI is set automatically (currently \"%s\").\n",
++           actual_abi_str);    
++      else if (global_abi == actual_abi)
++        fprintf_filtered
++          (file,
++           "The microblaze ABI is assumed to be \"%s\" (due to user setting).\n",
++           actual_abi_str);
 +      else
-+        set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
-+    }
-   else
--    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
-+    {
-+      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
-+          set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblazeel");
-+          MICROBLAZE_REGISTER_SIZE=8;
++        {
++#endif
++          /* Probably shouldn't happen...  */
++          fprintf_filtered (file,
++                            "The (auto detected) microblaze ABI \"%s\" is in use "
++                            "even though the user setting was \"%s\".\n",
++             actual_abi_str, microblaze_abi_strings[global_abi]);
 +        }
-+      else
-+        set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
-+    }
- 
-+    switch (info.bfd_arch_info->mach)
-+    {
-+    case bfd_mach_microblaze64:
-+      set_gdbarch_ptr_bit (gdbarch, 64);
-+    break;
-+    }
- 
-   /* Shared library handling.  */
-   set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
-@@ -178,7 +202,9 @@ void _initialize_microblaze_linux_tdep ();
- void
- _initialize_microblaze_linux_tdep ()
- {
--  gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX, 
-+  gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze, GDB_OSABI_LINUX, 
-+                         microblaze_linux_init_abi);
-+  gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze64, GDB_OSABI_LINUX, 
-                          microblaze_linux_init_abi);
-   initialize_tdesc_microblaze_linux ();
- }
-diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
-index ccb6b730d64..c347bb9516b 100644
---- a/gdb/microblaze-tdep.c
-+++ b/gdb/microblaze-tdep.c
-@@ -40,7 +40,9 @@
- #include "remote.h"
- 
- #include "features/microblaze-with-stack-protect.c"
-+#include "features/microblaze64-with-stack-protect.c"
- #include "features/microblaze.c"
-+#include "features/microblaze64.c"
- 
- /* Instruction macros used for analyzing the prologue.  */
- /* This set of instruction macros need to be changed whenever the
-@@ -75,12 +77,13 @@ static const char * const microblaze_register_names[] =
-   "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6",
-   "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11",
-   "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi",
--  "rslr", "rshr"
-+  "slr", "shr"
- };
- 
- #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
- 
- static unsigned int microblaze_debug_flag = 0;
-+int reg_size = 4;
- 
- #define microblaze_debug(fmt, ...) \
-   debug_prefixed_printf_cond_nofunc (microblaze_debug_flag, "MICROBLAZE", \
-@@ -128,6 +131,15 @@ microblaze_fetch_instruction (CORE_ADDR pc)
- constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
- 
- typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
-+static CORE_ADDR
-+microblaze_store_arguments (struct regcache *regcache, int nargs,
-+                           struct value **args, CORE_ADDR sp,
-+                           int struct_return, CORE_ADDR struct_addr)
++}                 
++
++static void
++show_microblaze_command (const char *args, int from_tty)
 +{
-+  error (_("store_arguments not implemented"));
-+  return sp;
++  help_list (showmicroblazecmdlist, "show microblaze ", all_commands, gdb_stdout);
 +}
-+#if 0
- static int
- microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
-                                    struct bp_target_info *bp_tgt)
-@@ -146,7 +158,6 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
-   /* Make sure we see the memory breakpoints.  */
-   scoped_restore restore_memory
-     = make_scoped_restore_show_memory_breakpoints (1);
--
-   val = target_read_memory (addr, old_contents, bplen);
- 
-   /* If our breakpoint is no longer at the address, this means that the
-@@ -161,6 +172,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
-   return val;
- }
- 
-+#endif
- /* Allocate and initialize a frame cache.  */
- 
- static struct microblaze_frame_cache *
-@@ -577,17 +589,16 @@ microblaze_extract_return_value (struct type *type, struct regcache *regcache,
-                                 gdb_byte *valbuf)
- {
-   gdb_byte buf[8];
--
-   /* Copy the return value (starting) in RETVAL_REGNUM to VALBUF.  */
-   switch (TYPE_LENGTH (type))
-     {
-       case 1:  /* return last byte in the register.  */
-        regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf);
--       memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 1, 1);
-+       memcpy(valbuf, buf + reg_size - 1, 1);
-        return;
-       case 2:  /* return last 2 bytes in register.  */
-        regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf);
--       memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 2, 2);
-+       memcpy(valbuf, buf + reg_size - 2, 2);
-        return;
-       case 4:  /* for sizes 4 or 8, copy the required length.  */
-       case 8:
-@@ -754,6 +765,12 @@ microblaze_software_single_step (struct regcache *regcache)
- }
- #endif
- 
++
 +static void
-+microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc)
++set_microblaze_command (const char *args, int from_tty)
 +{
-+  regcache_cooked_write_unsigned (regcache, MICROBLAZE_PC_REGNUM, pc);
++  printf_unfiltered
++    ("\"set microblaze\" must be followed by an appropriate subcommand.\n");
++  help_list (setmicroblazecmdlist, "set microblaze ", all_commands, gdb_stdout);
 +}
 +
- static int dwarf2_to_reg_map[78] =
- { 0  /* r0  */,   1  /* r1  */,   2  /* r2  */,   3  /* r3  */,  /*  0- 3 */
-   4  /* r4  */,   5  /* r5  */,   6  /* r6  */,   7  /* r7  */,  /*  4- 7 */
-@@ -788,13 +805,14 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
- static void
- microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
+ static const char * const microblaze_register_names[] =
  {
-+
-   register_remote_g_packet_guess (gdbarch,
-                                  4 * MICROBLAZE_NUM_CORE_REGS,
--                                 tdesc_microblaze);
-+                                 tdesc_microblaze64);
- 
-   register_remote_g_packet_guess (gdbarch,
-                                  4 * MICROBLAZE_NUM_REGS,
--                                 tdesc_microblaze_with_stack_protect);
-+                                 tdesc_microblaze64_with_stack_protect);
- }
- 
- void
-@@ -802,7 +820,7 @@ microblaze_supply_gregset (const struct regset *regset,
-                         struct regcache *regcache,
-                         int regnum, const void *gregs)
- {
--  const unsigned int *regs = (const unsigned int *)gregs;
-+  const gdb_byte *regs = (const gdb_byte *) gregs;
-   if (regnum >= 0)
-     regcache->raw_supply (regnum, regs + regnum);
- 
-@@ -810,7 +828,7 @@ microblaze_supply_gregset (const struct regset *regset,
-     int i;
- 
-     for (i = 0; i < 50; i++) {
--      regcache->raw_supply (i, regs + i);
-+      regcache->raw_supply (regnum, regs + i);
-     }
-   }
- }
-@@ -833,6 +851,17 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
- }
- 
+   "r0",   "r1",  "r2",    "r3",   "r4",   "r5",   "r6",   "r7",
+@@ -85,9 +172,21 @@ static const char * const microblaze_register_names[] =
+ static unsigned int microblaze_debug_flag = 0;
+ int reg_size = 4;
  
-+static void
-+make_regs (struct gdbarch *arch)
++unsigned int
++microblaze_abi_regsize (struct gdbarch *gdbarch)
 +{
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
-+  int mach = gdbarch_bfd_arch_info (arch)->mach;
-+  
-+  if (mach == bfd_mach_microblaze64)
++  switch (microblaze_abi (gdbarch))
 +    {
-+      set_gdbarch_ptr_bit (arch, 64);
++    case MICROBLAZE_ABI_M64:
++      return 8;
++    default:
++      return 4;
 +    }
 +}
++
+ #define microblaze_debug(fmt, ...) \
+   debug_prefixed_printf_cond_nofunc (microblaze_debug_flag, "MICROBLAZE", \
+-                                    fmt, ## __VA_ARGS__)
++                                     fmt, ## __VA_ARGS__)
  
- static struct gdbarch *
+ 
+ /* Return the name of register REGNUM.  */
+@@ -867,15 +966,30 @@ static struct gdbarch *
  microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-@@ -846,8 +875,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-   if (arches != NULL)
+ {
+   tdesc_arch_data_up tdesc_data;
++  enum microblaze_abi microblaze_abi, found_abi, wanted_abi;
+   const struct target_desc *tdesc = info.target_desc;
+ 
++ /* What has the user specified from the command line?  */
++  wanted_abi = global_microblaze_abi ();
++  if (gdbarch_debug)
++    fprintf_unfiltered (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n",
++                        wanted_abi);
++  if (wanted_abi != MICROBLAZE_ABI_AUTO)
++    microblaze_abi = wanted_abi;
++
+   /* If there is already a candidate, use it.  */
+   arches = gdbarch_list_lookup_by_info (arches, &info);
+-  if (arches != NULL)
++  if ((arches != NULL) && (microblaze_abi != MICROBLAZE_ABI_M64))
      return arches->gdbarch;
-   if (tdesc == NULL)
--    tdesc = tdesc_microblaze;
--
++
++  if (microblaze_abi == MICROBLAZE_ABI_M64)
 +    {
-+      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) 
-+        {
-+         tdesc = tdesc_microblaze64;
++          tdesc = tdesc_microblaze64;
 +          reg_size = 8;
-+       }
-+      else
-+       tdesc = tdesc_microblaze;
 +    }
-   /* Check any target description for validity.  */
-   if (tdesc_has_registers (tdesc))
+   if (tdesc == NULL)
      {
-@@ -855,31 +891,42 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+-      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) 
++      if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) 
+         {
+          tdesc = tdesc_microblaze64;
+           reg_size = 8;
+@@ -890,7 +1004,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
        int valid_p;
        int i;
  
--      feature = tdesc_find_feature (tdesc,
--                                   "org.gnu.gdb.microblaze.core");
-+      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
-+        feature = tdesc_find_feature (tdesc,
-+                                    "org.gnu.gdb.microblaze64.core");
-+      else
-+        feature = tdesc_find_feature (tdesc,
-+                                    "org.gnu.gdb.microblaze.core");
-       if (feature == NULL)
-        return NULL;
-       tdesc_data = tdesc_data_alloc ();
- 
-       valid_p = 1;
--      for (i = 0; i < MICROBLAZE_NUM_CORE_REGS; i++)
--       valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i,
--                                           microblaze_register_names[i]);
--      feature = tdesc_find_feature (tdesc,
--                                   "org.gnu.gdb.microblaze.stack-protect");
-+      for (i = 0; i < MICROBLAZE_NUM_REGS; i++)
-+        valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), i,
-+                                            microblaze_register_names[i]);
-+      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
-+        feature = tdesc_find_feature (tdesc,
-+                                    "org.gnu.gdb.microblaze64.stack-protect");
-+      else
-+        feature = tdesc_find_feature (tdesc,
-+                                    "org.gnu.gdb.microblaze.stack-protect");
-       if (feature != NULL)
--       {
--         valid_p = 1;
--         valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
--                                             MICROBLAZE_SLR_REGNUM,
--                                             "rslr");
--         valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
--                                             MICROBLAZE_SHR_REGNUM,
--                                             "rshr");
--       }
-+        {
-+          valid_p = 1;
-+          valid_p &= tdesc_numbered_register (feature, tdesc_data.get(),
-+                                              MICROBLAZE_SLR_REGNUM,
-+                                              "slr");
-+          valid_p &= tdesc_numbered_register (feature, tdesc_data.get(),
-+                                              MICROBLAZE_SHR_REGNUM,
-+                                              "shr");
-+        }
- 
-       if (!valid_p)
--       return NULL;
-+        {
-+         // tdesc_data_cleanup (tdesc_data.get ());
-+          return NULL;
-+        }
+-      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++      if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64))
+         feature = tdesc_find_feature (tdesc,
+                                     "org.gnu.gdb.microblaze64.core");
+       else
+@@ -904,7 +1018,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+       for (i = 0; i < MICROBLAZE_NUM_REGS; i++)
+         valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), i,
+                                             microblaze_register_names[i]);
+-      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++      if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64))
+         feature = tdesc_find_feature (tdesc,
+                                     "org.gnu.gdb.microblaze64.stack-protect");
+       else
+@@ -954,7 +1068,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+       set_gdbarch_ptr_bit (gdbarch, 64);
+     break;
      }
- 
-   /* Allocate space for the new architecture.  */
-@@ -899,7 +946,17 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-   /* Register numbers of various important registers.  */
-   set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM); 
-   set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM); 
-+  
-+  /* Register set.  
-+  make_regs (gdbarch); */
-+  switch (info.bfd_arch_info->mach)
-+    {
-+    case bfd_mach_microblaze64:
-+      set_gdbarch_ptr_bit (gdbarch, 64);
-+    break;
-+    }
- 
-+  
+-
++  if(microblaze_abi == MICROBLAZE_ABI_M64)
++    set_gdbarch_ptr_bit (gdbarch, 64);
+   
    /* Map Dwarf2 registers to GDB registers.  */
    set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum);
+@@ -1014,6 +1129,38 @@ _initialize_microblaze_tdep ()
+ {
+   gdbarch_register (bfd_arch_microblaze, microblaze_gdbarch_init);
  
-@@ -919,7 +976,9 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-                                       microblaze_breakpoint::kind_from_pc);
-   set_gdbarch_sw_breakpoint_from_kind (gdbarch,
-                                       microblaze_breakpoint::bp_from_kind);
--  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
-+//  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
-+
-+//  set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
- 
-   set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
- 
-@@ -927,7 +986,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
- 
-   set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc);
- 
--  microblaze_register_g_packet_guesses (gdbarch);
-+  //microblaze_register_g_packet_guesses (gdbarch);
- 
-   frame_base_set_default (gdbarch, &microblaze_frame_base);
- 
-@@ -942,12 +1001,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-     tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data));
-   //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer);
++// static struct cmd_list_element *setmicroblazecmdlist = NULL;
++// static struct cmd_list_element *showmicroblazecmdlist = NULL;
++
++  /* Add root prefix command for all "set microblaze"/"show microblaze" commands.  */
++ 
++  add_setshow_prefix_cmd ("microblaze", no_class,
++                        _("Various microblaze specific commands."),
++                        _("Various microblaze specific commands."),
++                        &setmicroblazecmdlist,&showmicroblazecmdlist,
++                        &setlist,&showlist);
++#if 0
++  add_prefix_cmd ("microblaze", no_class, set_microblaze_command,
++                  _("Various microblaze specific commands."),
++                  &setmicroblazecmdlist, "set microblaze ", 0, &setlist);
++
++  add_prefix_cmd ("microblaze", no_class, show_microblaze_command,
++                  _("Various microblaze specific commands."),
++                  &showmicroblazecmdlist, "show microblaze ", 0, &showlist);
++#endif
++
++  /* Allow the user to override the ABI.  */
++  add_setshow_enum_cmd ("abi", class_obscure, microblaze_abi_strings,
++                        &microblaze_abi_string, _("\
++Set the microblaze ABI used by this program."), _("\
++Show the microblaze ABI used by this program."), _("\
++This option can be set to one of:\n\
++  auto  - the default ABI associated with the current binary\n\
++  m64"),
++                       microblaze_abi_update,
++                      show_microblaze_abi,
++                       &setmicroblazecmdlist, &showmicroblazecmdlist);
++  
+   initialize_tdesc_microblaze_with_stack_protect ();
+   initialize_tdesc_microblaze ();
+   initialize_tdesc_microblaze64_with_stack_protect ();
+@@ -1028,5 +1175,4 @@ When non-zero, microblaze specific debugging is enabled."),
+                             NULL,
+                             &setdebuglist, &showdebuglist);
  
--  /* If we have register sets, enable the generic core file support.  */
-+  /* If we have register sets, enable the generic core file support.  
-   if (tdep->gregset) {
-     set_gdbarch_iterate_over_regset_sections (gdbarch,
-                                           microblaze_iterate_over_regset_sections);
--  }
 -
-+  }*/
-   return gdbarch;
  }
- 
-@@ -959,6 +1017,8 @@ _initialize_microblaze_tdep ()
- 
-   initialize_tdesc_microblaze_with_stack_protect ();
-   initialize_tdesc_microblaze ();
-+  initialize_tdesc_microblaze64_with_stack_protect ();
-+  initialize_tdesc_microblaze64 ();
-   /* Debug this files internals.  */
-   add_setshow_zuinteger_cmd ("microblaze", class_maintenance,
-                             &microblaze_debug_flag, _("\
 diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
-index 2415acfe7b6..f4d810303ca 100644
+index 542cdd82070..17a4bb5190c 100644
 --- a/gdb/microblaze-tdep.h
 +++ b/gdb/microblaze-tdep.h
-@@ -28,7 +28,7 @@ struct microblaze_gregset
-    microblaze_gregset() {}
-    unsigned int gregs[32];
-    unsigned int fpregs[32];
--   unsigned int pregs[16];
-+   unsigned int pregs[18];
- };
- 
- struct microblaze_gdbarch_tdep : gdbarch_tdep
-@@ -134,7 +134,7 @@ struct microblaze_frame_cache
-   struct trad_frame_saved_reg *saved_regs;
- };
- /* All registers are 32 bits.  */
--#define MICROBLAZE_REGISTER_SIZE 4
-+//#define MICROBLAZE_REGISTER_SIZE 8
- 
- /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
-    Only used for native debugging.  */
-diff --git a/include/elf/common.h b/include/elf/common.h
-index 70d63e3299c..8aa330d6631 100644
---- a/include/elf/common.h
-+++ b/include/elf/common.h
-@@ -360,6 +360,7 @@
- #define EM_U16_U8CORE  260     /* LAPIS nX-U16/U8 */
- #define EM_TACHYUM     261     /* Tachyum */
- #define EM_56800EF     262     /* NXP 56800EF Digital Signal Controller (DSC) */
-+#define EM_MB_64       263     /* Xilinx MicroBlaze 32-bit RISC soft processor core */
- 
- /* If it is necessary to assign new unofficial EM_* values, please pick large
-    random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision
-diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
-index 43ad3ad3904..79799b86a49 100644
---- a/include/elf/microblaze.h
-+++ b/include/elf/microblaze.h
-@@ -61,6 +61,10 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
-   RELOC_NUMBER (R_MICROBLAZE_TEXTPCREL_64, 30)  /* PC-relative TEXT offset.  */
-   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31)    /* TEXT Entry offset 64-bit.  */
-   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit.  */
-+  RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
-+  RELOC_NUMBER (R_MICROBLAZE_IMML_64, 34)
-+  RELOC_NUMBER (R_MICROBLAZE_GPC_64, 35)    /* GOT entry offset.  */
-+   
- END_RELOC_NUMBERS (R_MICROBLAZE_max)
- 
- /* Global base address names.  */
-diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
-index b057492ba93..283d87c04a2 100644
---- a/opcodes/microblaze-dis.c
-+++ b/opcodes/microblaze-dis.c
-@@ -33,6 +33,7 @@
- #define get_field_r1(buf, instr)   get_field (buf, instr, RA_MASK, RA_LOW)
- #define get_field_r2(buf, instr)   get_field (buf, instr, RB_MASK, RB_LOW)
- #define get_int_field_imm(instr)   ((instr & IMM_MASK) >> IMM_LOW)
-+#define get_int_field_imml(instr)  ((instr & IMML_MASK) >> IMM_LOW)
- #define get_int_field_r1(instr)    ((instr & RA_MASK) >> RA_LOW)
- 
- #define NUM_STRBUFS 3
-@@ -73,11 +74,20 @@ get_field_imm (struct string_buf *buf, long instr)
- }
+@@ -19,9 +19,17 @@
  
- static char *
--get_field_imm5 (struct string_buf *buf, long instr)
-+get_field_imml (struct string_buf *buf, long instr)
- {
-   char *p = strbuf (buf);
- 
--  sprintf (p, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
-+  sprintf (p, "%d", (int)((instr & IMML_MASK) >> IMM_LOW));
-+  return p;
-+}
-+
-+static char *
-+get_field_imms (struct string_buf *buf, long instr)
-+{
-+  char *p = strbuf (buf);
-+
-+  sprintf (p, "%d", (short)((instr & IMM6_MASK) >> IMM_LOW));
-   return p;
- }
- 
-@@ -90,6 +100,18 @@ get_field_imm5_mbar (struct string_buf *buf, long instr)
-   return p;
- }
- 
-+static char *
-+get_field_immw (struct string_buf *buf, long instr)
-+{
-+  char *p = strbuf (buf);
-+
-+  if (instr & 0x00004000)
-+    sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
-+ else
-+    sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM6_MASK) >> IMM_LOW) + 1)); /* bsifi */
-+  return p;
-+}
-+
- static char *
- get_field_rfsl (struct string_buf *buf, long instr)
- {
-@@ -296,9 +318,14 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
-                }
-            }
-          break;
--       case INST_TYPE_RD_R1_IMM5:
-+       case INST_TYPE_RD_R1_IMML:
-+         print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
-+                  get_field_r1(&buf, inst), get_field_imm (&buf, inst));
-+          /* TODO: Also print symbol */
-+          break;
-+       case INST_TYPE_RD_R1_IMMS:
-          print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
--                     get_field_r1 (&buf, inst), get_field_imm5 (&buf, inst));
-+                  get_field_r1(&buf, inst), get_field_imms (&buf, inst));
-          break;
-        case INST_TYPE_RD_RFSL:
-          print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
-@@ -402,9 +429,12 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
-                }
-            }
-          break;
--       case INST_TYPE_RD_R2:
--         print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
--                     get_field_r2 (&buf, inst));
-+        case INST_TYPE_IMML:
-+         print_func (stream, "\t%s", get_field_imml (&buf, inst));
-+          /* TODO: Also print symbol */
-+         break;
-+        case INST_TYPE_RD_R2:
-+         print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_r2 (&buf, inst));
-          break;
-        case INST_TYPE_R2:
-          print_func (stream, "\t%s", get_field_r2 (&buf, inst));
-@@ -427,7 +457,12 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
-          /* For mbar 16 or sleep insn.  */
-        case INST_TYPE_NONE:
-          break;
--         /* For tuqula instruction */
-+        /* For bit field insns.  */
-+       case INST_TYPE_RD_R1_IMMW_IMMS:
-+         print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst),
-+                  get_field_immw (&buf, inst), get_field_imms (&buf, inst));
-+         break;
-+       /* For tuqula instruction */
-        case INST_TYPE_RD:
-          print_func (stream, "\t%s", get_field_rd (&buf, inst));
-          break;
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index ffb0f08c692..5e45df995de 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -40,7 +40,7 @@
- #define INST_TYPE_RD_SPECIAL 11
- #define INST_TYPE_R1 12
- /* New instn type for barrel shift imms.  */
--#define INST_TYPE_RD_R1_IMM5  13
-+#define INST_TYPE_RD_R1_IMMS  13
- #define INST_TYPE_RD_RFSL    14
- #define INST_TYPE_R1_RFSL    15
- 
-@@ -59,6 +59,15 @@
- /* For mbar.  */
- #define INST_TYPE_IMM5 20
- 
-+/* For bsefi and bsifi */
-+#define INST_TYPE_RD_R1_IMMW_IMMS  21
-+
-+/* For 64-bit instructions */
-+#define INST_TYPE_IMML 22
-+#define INST_TYPE_RD_R1_IMML 23
-+#define INST_TYPE_R1_IMML 24
-+#define INST_TYPE_RD_R1_IMMW_IMMS  21
-+
- #define INST_TYPE_NONE 25
- 
- 
-@@ -88,10 +97,14 @@
- #define OPCODE_MASK_H24 0xFC1F07FF  /* High 6, bits 20-16 and low 11 bits.  */
- #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits.  */
- #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
--#define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */
-+#define OPCODE_MASK_H3  0xFC000700  /* High 6 bits and bits 21, 22, 23.  */
-+#define OPCODE_MASK_H3B 0xFC00E600  /* High 6 bits and bits 16, 17, 18, 21, 22.  */
- #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
-+#define OPCODE_MASK_H32B 0xFC00E000  /* High 6 bits and bit 16, 17, 18.  */
- #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
-+#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits.  */
- #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
-+#define OPCODE_MASK_H8  0xFF000000  /* High 8 bits only.  */
- 
- /* New Mask for msrset, msrclr insns.  */
- #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16.  */
-@@ -101,7 +114,7 @@
- #define DELAY_SLOT 1
- #define NO_DELAY_SLOT 0
- 
--#define MAX_OPCODES 289
-+#define MAX_OPCODES 412
+ #ifndef MICROBLAZE_TDEP_H
+ #define MICROBLAZE_TDEP_H 1
+-
++#include "objfiles.h"
+ #include "gdbarch.h"
  
- const struct op_code_struct
++struct gdbarch;
++enum microblaze_abi
++  {
++    MICROBLAZE_ABI_AUTO = 0,
++    MICROBLAZE_ABI_M64,
++ };
++
++enum microblaze_abi microblaze_abi (struct gdbarch *gdbarch);
+ /* Microblaze architecture-specific information.  */
+ struct microblaze_gregset
  {
-@@ -119,6 +132,7 @@ const struct op_code_struct
-   /* More info about output format here.  */
- } microblaze_opcodes[MAX_OPCODES] =
+@@ -35,11 +43,14 @@ struct microblaze_gdbarch_tdep : gdbarch_tdep_base
  {
-+  /* 32-bit instructions */
-   {"add",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
-   {"rsub",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
-   {"addc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
-@@ -155,9 +169,11 @@ const struct op_code_struct
-   {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
-   {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
-   {"muli",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
--  {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
--  {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
--  {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
-+  {"bslli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst },
-+  {"bsrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst },
-+  {"bsrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst },
-+  {"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
-+  {"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
-   {"or",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
-   {"and",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
-   {"xor",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
-@@ -174,9 +190,14 @@ const struct op_code_struct
-   {"wic",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
-   {"wdc",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
-   {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
-+  {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
-   {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
-+  {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
-+  {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst },
-   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
-+  {"mtse",  INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst },
-   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
-+  {"mfse",  INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst },
-   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
-   {"brd",   INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
-   {"brld",  INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
-@@ -226,18 +247,24 @@ const struct op_code_struct
-   {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
-   {"lbu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
-   {"lbur",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
-+  {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst },
-   {"lhu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
-   {"lhur",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
-+  {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst },
-   {"lw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
-   {"lwr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
-   {"lwx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
-+  {"lwea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst },
-   {"sb",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
-   {"sbr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
-+  {"sbea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst },
-   {"sh",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
-   {"shr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
-+  {"shea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst },
-   {"sw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
-   {"swr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
-   {"swx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
-+  {"swea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst },
-   {"lbui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
-   {"lhui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
-   {"lwi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
-@@ -248,9 +275,7 @@ const struct op_code_struct
-   {"la",    INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik.  */
-   {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42.  */
-   {"not",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1.  */
--  {"neg",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0.  */
-   {"rtb",   INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4.  */
--  {"sub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra.  */
-   {"lmi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },
-   {"smi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
-   {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
-@@ -402,8 +427,135 @@ const struct op_code_struct
-   {"clz",       INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34,  clz,       special_inst },
-   {"mbar",      INST_TYPE_IMM5,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN,   mbar,      special_inst },
-   {"sleep",     INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 16.  */
-+  {"hibernate", INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 8.   */
-+  {"suspend",   INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 24.  */
-   {"swapb",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4,   swapb,     arithmetic_inst },
-   {"swaph",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4,   swaph,     arithmetic_inst },
-+
-+  /* 64-bit instructions */
-+  {"addl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000100, OPCODE_MASK_H4, addl, arithmetic_inst },
-+  {"rsubl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000100, OPCODE_MASK_H4, rsubl, arithmetic_inst },
-+  {"addlc",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000100, OPCODE_MASK_H4, addlc, arithmetic_inst },
-+  {"rsublc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000100, OPCODE_MASK_H4, rsublc, arithmetic_inst },
-+  {"addlk",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000100, OPCODE_MASK_H4, addlk, arithmetic_inst },
-+  {"rsublk",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000100, OPCODE_MASK_H4, rsublk, arithmetic_inst },
-+  {"addlkc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000100, OPCODE_MASK_H4, addlkc, arithmetic_inst },
-+  {"rsublkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000100, OPCODE_MASK_H4, rsublkc, arithmetic_inst },
-+  {"cmpl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
-+  {"cmplu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
-+  {"addli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"rsubli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addlic",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addlik",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },  /* Identical to 32-bit */
-+  {"mull",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
-+  {"bslll",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
-+  {"bslra",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
-+  {"bslrl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000100, OPCODE_MASK_H3, bslrl, barrel_shift_inst },
-+  {"bsllli",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002400, OPCODE_MASK_H3B, bsllli, barrel_shift_inst },
-+  {"bslrai",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002200, OPCODE_MASK_H3B, bslrai, barrel_shift_inst },
-+  {"bslrli",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002000, OPCODE_MASK_H3B, bslrli, barrel_shift_inst },
-+  {"bslefi",  INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64006000, OPCODE_MASK_H32B, bslefi, barrel_shift_inst },
-+  {"bslifi",  INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6400a000, OPCODE_MASK_H32B, bslifi, barrel_shift_inst },
-+  {"orl",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000100, OPCODE_MASK_H4, orl, logical_inst },
-+  {"andl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000100, OPCODE_MASK_H4, andl, logical_inst },
-+  {"xorl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000100, OPCODE_MASK_H4, xorl, logical_inst },
-+  {"andnl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000100, OPCODE_MASK_H4, andnl, logical_inst },
-+  {"pcmplbf", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000500, OPCODE_MASK_H4, pcmplbf, logical_inst },
-+  {"pcmpleq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000500, OPCODE_MASK_H4, pcmpleq, logical_inst },
-+  {"pcmplne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000500, OPCODE_MASK_H4, pcmplne, logical_inst },
-+  {"srla",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000101, OPCODE_MASK_H34, srla, logical_inst },
-+  {"srlc",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000121, OPCODE_MASK_H34, srlc, logical_inst },
-+  {"srll",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000141, OPCODE_MASK_H34, srll, logical_inst },
-+  {"sextl8",  INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000160, OPCODE_MASK_H34, sextl8, logical_inst },
-+  {"sextl16", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000161, OPCODE_MASK_H34, sextl16, logical_inst },
-+  {"sextl32", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000162, OPCODE_MASK_H34, sextl32, logical_inst },
-+  {"brea",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98010000, OPCODE_MASK_H124, brea, branch_inst },
-+  {"bread",   INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98110000, OPCODE_MASK_H124, bread, branch_inst },
-+  {"breald",  INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98150000, OPCODE_MASK_H24, breald, branch_inst },
-+  {"beaeq",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000000, OPCODE_MASK_H14, beaeq, branch_inst },
-+  {"bealeq",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000100, OPCODE_MASK_H14, bealeq, branch_inst },
-+  {"beaeqd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000000, OPCODE_MASK_H14, beaeqd, branch_inst },
-+  {"bealeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000100, OPCODE_MASK_H14, bealeqd, branch_inst },
-+  {"beane",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200000, OPCODE_MASK_H14, beane, branch_inst },
-+  {"bealne",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200100, OPCODE_MASK_H14, bealne, branch_inst },
-+  {"beaned",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200000, OPCODE_MASK_H14, beaned, branch_inst },
-+  {"bealned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200100, OPCODE_MASK_H14, bealned, branch_inst },
-+  {"bealt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400000, OPCODE_MASK_H14, bealt, branch_inst },
-+  {"beallt",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400100, OPCODE_MASK_H14, beallt, branch_inst },
-+  {"bealtd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400000, OPCODE_MASK_H14, bealtd, branch_inst },
-+  {"bealltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400100, OPCODE_MASK_H14, bealltd, branch_inst },
-+  {"beale",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600000, OPCODE_MASK_H14, beale, branch_inst },
-+  {"bealle",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600100, OPCODE_MASK_H14, bealle, branch_inst },
-+  {"bealed",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600000, OPCODE_MASK_H14, bealed, branch_inst },
-+  {"bealled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600100, OPCODE_MASK_H14, bealled, branch_inst },
-+  {"beagt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800000, OPCODE_MASK_H14, beagt, branch_inst },
-+  {"bealgt",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800100, OPCODE_MASK_H14, bealgt, branch_inst },
-+  {"beagtd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800000, OPCODE_MASK_H14, beagtd, branch_inst },
-+  {"bealgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800100, OPCODE_MASK_H14, bealgtd, branch_inst },
-+  {"beage",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00000, OPCODE_MASK_H14, beage, branch_inst },
-+  {"bealge",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00100, OPCODE_MASK_H14, bealge, branch_inst },
-+  {"beaged",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
-+  {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
-+  {"orli",    INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"andli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"xorli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"andnli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"imml",    INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
-+  {"breai",   INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
-+  {"breaid",  INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
-+  {"brealid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8150000, OPCODE_MASK_H2, brealid, branch_inst },
-+  {"beaeqi",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, beaeqi, branch_inst },
-+  {"bealeqi", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqi */
-+  {"beaeqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, beaeqid, branch_inst },
-+  {"bealeqid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beaeqid */
-+  {"beanei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, beanei, branch_inst },
-+  {"bealnei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beanei */
-+  {"beaneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, beaneid, branch_inst },
-+  {"bealneid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beaneid */
-+  {"bealti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, bealti, branch_inst },
-+  {"beallti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealti */
-+  {"bealtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, bealtid, branch_inst },
-+  {"bealltid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to bealtid */
-+  {"bealei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, bealei, branch_inst },
-+  {"beallei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealei */
-+  {"bealeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, bealeid, branch_inst },
-+  {"bealleid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to bealeid */
-+  {"beagti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, beagti, branch_inst },
-+  {"bealgti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagti */
-+  {"beagtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, beagtid, branch_inst },
-+  {"bealgtid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beagtid */
-+  {"beagei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, beagei, branch_inst },
-+  {"bealgei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagei */
-+  {"beageid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, beageid, branch_inst },
-+  {"bealgeid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beageid */
-+  {"ll",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000100, OPCODE_MASK_H4, ll, memory_load_inst },
-+  {"llr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst },
-+  {"sl",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst },
-+  {"slr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst },
-+  {"lli",     INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xEC000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },  /* Identical to 32-bit */
-+  {"sli",     INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xFC000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
-+  {"lla",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* lla translates to addlik */
-+  {"dadd",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst },
-+  {"drsub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst },
-+  {"dmul",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000500, OPCODE_MASK_H4, dmul, arithmetic_inst },
-+  {"ddiv",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000580, OPCODE_MASK_H4, ddiv, arithmetic_inst },
-+  {"dcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000610, OPCODE_MASK_H4, dcmp_lt, arithmetic_inst },
-+  {"dcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000620, OPCODE_MASK_H4, dcmp_eq, arithmetic_inst },
-+  {"dcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000630, OPCODE_MASK_H4, dcmp_le, arithmetic_inst },
-+  {"dcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000640, OPCODE_MASK_H4, dcmp_gt, arithmetic_inst },
-+  {"dcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000650, OPCODE_MASK_H4, dcmp_ne, arithmetic_inst },
-+  {"dcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000660, OPCODE_MASK_H4, dcmp_ge, arithmetic_inst },
-+  {"dcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000600, OPCODE_MASK_H4, dcmp_un, arithmetic_inst },
-+  {"dbl",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl,   arithmetic_inst },
-+  {"dlong",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst },
-+  {"dsqrt",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst },
-+  {"neg",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0.  */
-+  {"sub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra.  */
-+
-   {"", 0, 0, 0, 0, 0, 0, 0, 0},
- };
- 
-@@ -424,5 +576,17 @@ char pvr_register_prefix[] = "rpvr";
- #define MIN_IMM5  ((int) 0x00000000)
- #define MAX_IMM5  ((int) 0x0000001f)
+   int dummy;           // declare something.
  
-+#define MIN_IMM6  ((int) 0x00000000)
-+#define MAX_IMM6  ((int) 0x0000003f)
-+
-+#define MIN_IMM_WIDTH  ((int) 0x00000001)
-+#define MAX_IMM_WIDTH  ((int) 0x00000020)
-+
-+#define MIN_IMM6_WIDTH  ((int) 0x00000001)
-+#define MAX_IMM6_WIDTH  ((int) 0x00000040)
-+
-+#define MIN_IMML  ((long) 0xffffff8000000000L)
-+#define MAX_IMML  ((long) 0x0000007fffffffffL)
-+
- #endif /* MICROBLAZE_OPC */
- 
-diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index 8e293465fec..254d9fe911e 100644
---- a/opcodes/microblaze-opcm.h
-+++ b/opcodes/microblaze-opcm.h
-@@ -25,22 +25,23 @@
- 
- enum microblaze_instr
- {
-+  /* 32-bit instructions */
-   add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
-   addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
-   mulh, mulhu, mulhsu,swapb,swaph,
-   idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
--  ncget, ncput, muli, bslli, bsrai, bsrli, mului,
-+  ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
-   /* 'or/and/xor' are C++ keywords.  */
-   microblaze_or, microblaze_and, microblaze_xor,
-   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
--  wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
--  brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
--  bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
-+  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse,
-+  mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd,
-+  bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
-   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
-   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
--  bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
--  shr, sw, swr, swx, lbui, lhui, lwi,
--  sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
-+  bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
-+  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, lli,
-+  sbi, shi, sli, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
-   fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
-   /* 'fsqrt' is a glibc:math.h symbol.  */
-   fint, microblaze_fsqrt,
-@@ -59,6 +60,18 @@ enum microblaze_instr
-   aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
-   eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
-   eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
-+
-+  /* 64-bit instructions */
-+  addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
-+  bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
-+  andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
-+  brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
-+  bealned, bealt, beallt, bealtd, bealltd, beale, bealle, bealed, bealled, beagt,
-+  bealgt, beagtd, bealgtd, beage, bealge, beaged, bealged, breai, breaid, brealid,
-+  beaeqi, beaeqid, beanei, beaneid, bealti, bealtid, bealei, bealeid, beagti,
-+  beagtid, beagei, beageid, imml, ll, llr, sl, slr,
-+  dadd, drsub, dmul, ddiv, dcmp_lt, dcmp_eq, dcmp_le, dcmp_gt, dcmp_ne, dcmp_ge,
-+  dcmp_un, dbl, dlong, dsqrt,
-   invalid_inst
++  enum microblaze_abi microblaze_abi {};
++  enum microblaze_abi found_abi {};
+   /* Register sets.  */
+   struct regset *gregset;
+   size_t sizeof_gregset;
+   struct regset *fpregset;
+   size_t sizeof_fpregset;
++  int register_size;
  };
  
-@@ -130,18 +143,25 @@ enum microblaze_instr_type
- #define RB_LOW  11 /* Low bit for RB.  */
- #define IMM_LOW  0 /* Low bit for immediate.  */
- #define IMM_MBAR 21 /* low bit for mbar instruction.  */
-+#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
- 
- #define RD_MASK 0x03E00000
- #define RA_MASK 0x001F0000
- #define RB_MASK 0x0000F800
- #define IMM_MASK 0x0000FFFF
-+#define IMML_MASK 0x00FFFFFF
- 
--/* Imm mask for barrel shifts.  */
-+/* Imm masks for barrel shifts.  */
- #define IMM5_MASK 0x0000001F
-+#define IMM6_MASK 0x0000003F
- 
- /* Imm mask for mbar.  */
- #define IMM5_MBAR_MASK 0x03E00000
- 
-+/* Imm masks for extract/insert width. */
-+#define IMM5_WIDTH_MASK 0x000007C0
-+#define IMM6_WIDTH_MASK 0x00000FC0
-+
- /* FSL imm mask for get, put instructions.  */
- #define  RFSL_MASK 0x000000F
- 
+ /* Register numbers.  */
 -- 
-2.37.1 (Apple Git-137.1)
+2.34.1
 
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0008-Patch-MicroBlaze.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0009-Depth-Total-number-of-inline-functions-refer-inline-.patch
index 941a3b9c..6769e1ee 100644
--- a/meta-microblaze/recipes-devtools/gdb/gdb/0008-Patch-MicroBlaze.patch
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0009-Depth-Total-number-of-inline-functions-refer-inline-.patch
@@ -1,32 +1,41 @@
-From 0532b1db08b9d8efc670f7288fe2d8168b8ed0d1 Mon Sep 17 00:00:00 2001
+From c37f307714121981fa91766c539913f7912643b7 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 21 Jul 2022 11:45:01 +0530
-Subject: [PATCH 8/8] =?UTF-8?q?[Patch,MicroBlaze]:=20Depth:=20=20Total=20n?=
- =?UTF-8?q?umber=20of=20inline=20functions=20[refer=20inline-frame.c]=20st?=
- =?UTF-8?q?ate->skipped=5Fframes=20:=20Number=20of=20inline=20functions=20?=
- =?UTF-8?q?skipped.=20the=20current=20unwind=5Fpc=20is=20causing=20an=20is?=
- =?UTF-8?q?sue=20when=20we=20try=20to=20step=20into=20inline=20functions[D?=
- =?UTF-8?q?epth=20is=20becoming=200].=20It=E2=80=99s=20incrementing=20pc?=
- =?UTF-8?q?=20by=208=20even=20with=20si=20instruction.?=
+Subject: [PATCH 09/54] =?UTF-8?q?Depth:=20Total=20number=20of=20inline=20f?=
+ =?UTF-8?q?unctions=20[refer=20inline-frame.c]=20state->skipped=5Fframes?=
+ =?UTF-8?q?=20:=20Number=20of=20inline=20functions=20skipped.=20the=20curr?=
+ =?UTF-8?q?ent=20unwind=5Fpc=20is=20causing=20an=20issue=20when=20we=20try?=
+ =?UTF-8?q?=20to=20step=20into=20inline=20functions[Depth=20is=20becoming?=
+ =?UTF-8?q?=200].=20It=E2=80=99s=20incrementing=20pc=20by=208=20even=20wit?=
+ =?UTF-8?q?h=20si=20instruction.?=
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
 
-Upstream-Status: Pending
-
-Signed-off-by: Mark Hatle <mark.hatle@amd.com>
-
+Signed-off-by: Aayush Misra <aayushm@amd.com>
 ---
- gdb/microblaze-tdep.c | 14 +++-----------
- 1 file changed, 3 insertions(+), 11 deletions(-)
+ gdb/features/microblaze64.xml |  1 +
+ gdb/microblaze-tdep.c         | 14 +++-----------
+ 2 files changed, 4 insertions(+), 11 deletions(-)
 
+diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml
+index 515d18e65cf..9c1b7d22003 100644
+--- a/gdb/features/microblaze64.xml
++++ b/gdb/features/microblaze64.xml
+@@ -7,5 +7,6 @@
+ 
+ <!DOCTYPE target SYSTEM "gdb-target.dtd">
+ <target>
++  <architecture>microblaze64</architecture>
+   <xi:include href="microblaze64-core.xml"/>
+ </target>
 diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
-index d83072cdaef..38ba38e8c7d 100644
+index f265e8fc608..3e541789fac 100644
 --- a/gdb/microblaze-tdep.c
 +++ b/gdb/microblaze-tdep.c
 @@ -513,16 +513,8 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
  static CORE_ADDR
- microblaze_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
+ microblaze_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame)
  {
 -  gdb_byte buf[4];
    CORE_ADDR pc;
@@ -61,5 +70,5 @@ index d83072cdaef..38ba38e8c7d 100644
  
  static CORE_ADDR
 -- 
-2.37.1 (Apple Git-137.1)
+2.34.1
 
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0009-gdb-gdserver-Fix-ABI-settings-for-gdbserver.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0009-gdb-gdserver-Fix-ABI-settings-for-gdbserver.patch
deleted file mode 100644
index 6a930420..00000000
--- a/meta-microblaze/recipes-devtools/gdb/gdb/0009-gdb-gdserver-Fix-ABI-settings-for-gdbserver.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 53b76bb548720367032a51a6d604c975b10bb30e Mon Sep 17 00:00:00 2001
-From: Aayush Misra <aayushm@amd.com>
-Date: Fri, 29 Mar 2024 14:59:16 +0530
-Subject: [PATCH] gdb/gdserver: Fix ABI settings for gdbserver
-
-Upstream-Status: Pending
-
----
- gdb/microblaze-tdep.c | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
-diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
-index 38ba38e8c7d..35cec286d8f 100644
---- a/gdb/microblaze-tdep.c
-+++ b/gdb/microblaze-tdep.c
-@@ -1120,12 +1120,13 @@ void _initialize_microblaze_tdep ();
- void
- _initialize_microblaze_tdep ()
- {
-+  //Setting abi to auto manually, should be able to modify in 'arch'_gdbarch_init function
-+  microblaze_abi_string = microblaze_abi_strings[0]; 
-+
-   register_gdbarch_init (bfd_arch_microblaze, microblaze_gdbarch_init);
--// static struct cmd_list_element *setmicroblazecmdlist = NULL;
--// static struct cmd_list_element *showmicroblazecmdlist = NULL;
- 
--  /* Add root prefix command for all "set microblaze"/"show microblaze" commands.  */
- 
-+  /* Add root prefix command for all "set microblaze"/"show microblaze" commands.  */
-   add_setshow_prefix_cmd ("microblaze", no_class,
-                         _("Various microblaze specific commands."),
-                         _("Various microblaze specific commands."),
--- 
-2.34.1
-
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch
new file mode 100644
index 00000000..e5c88f01
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch
@@ -0,0 +1,133 @@
+From 6b6632b730808a012738f9eddf621abd6463e317 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 29 Feb 2024 10:53:04 +0530
+Subject: [PATCH 10/54] Fix gdb-14 build errors for microblaze-xilinx-elf
+ 2023.2 merge
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elf64-microblaze.c | 12 ++++++++++++
+ gdb/frame.c            |  2 +-
+ gdb/microblaze-tdep.c  | 17 +++++++++++------
+ 3 files changed, 24 insertions(+), 7 deletions(-)
+
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index 6cd9753a592..119d266f95a 100755
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -750,6 +750,18 @@ microblaze_elf_info_to_howto (bfd * abfd,
+   return true;
+ }
+ 
++/* Relax table contains information about instructions which can
++   be removed by relaxation -- replacing a long address with a
++   short address.  */
++struct relax_table
++{
++  /* Address where bytes may be deleted.  */
++  bfd_vma addr;
++
++  /* Number of bytes to be deleted.  */
++  size_t size;
++};
++
+ struct _microblaze_elf_section_data
+ {
+   struct bfd_elf_section_data elf;
+diff --git a/gdb/frame.c b/gdb/frame.c
+index c4d967e01d5..8be230e0617 100644
+--- a/gdb/frame.c
++++ b/gdb/frame.c
+@@ -1315,7 +1315,7 @@ frame_unwind_register_value (frame_info_ptr next_frame, int regnum)
+              int i;
+ 
+              const gdb_byte *buf = NULL;
+-             if (value_entirely_available(value)) {
++             if (value->entirely_available()) {
+                gdb::array_view<const gdb_byte> buf = value->contents ();
+              }
+ 
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 3e541789fac..f7d9d6419ce 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -75,7 +75,7 @@ static const char *const microblaze_abi_strings[] = {
+ enum microblaze_abi
+ microblaze_abi (struct gdbarch *gdbarch)
+ {
+-  microblaze_gdbarch_tdep *tdep = (microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch);
++  microblaze_gdbarch_tdep *tdep = gdbarch_tdep<microblaze_gdbarch_tdep> (gdbarch);
+   return tdep->microblaze_abi;
+ }
+ /* The registers of the Xilinx microblaze processor.  */
+@@ -120,12 +120,12 @@ show_microblaze_abi (struct ui_file *file,
+ 
+ #if 1 
+       if (global_abi == MICROBLAZE_ABI_AUTO)
+-        fprintf_filtered
++        gdb_printf
+           (file,
+            "The microblaze ABI is set automatically (currently \"%s\").\n",
+            actual_abi_str);    
+       else if (global_abi == actual_abi)
+-        fprintf_filtered
++        gdb_printf
+           (file,
+            "The microblaze ABI is assumed to be \"%s\" (due to user setting).\n",
+            actual_abi_str);
+@@ -133,7 +133,7 @@ show_microblaze_abi (struct ui_file *file,
+         {
+ #endif
+           /* Probably shouldn't happen...  */
+-          fprintf_filtered (file,
++          gdb_printf (file,
+                             "The (auto detected) microblaze ABI \"%s\" is in use "
+                             "even though the user setting was \"%s\".\n",
+              actual_abi_str, microblaze_abi_strings[global_abi]);
+@@ -934,7 +934,7 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
+                                      void *cb_data,
+                                      const struct regcache *regcache)
+ {
+-  struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch);
++  microblaze_gdbarch_tdep *tdep = gdbarch_tdep<microblaze_gdbarch_tdep> (gdbarch);
+ 
+   cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data);
+ 
+@@ -942,6 +942,8 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
+ }
+ 
+ 
++#if 0
++// compilation errors - function is not actually used ?
+ static void
+ make_regs (struct gdbarch *arch)
+ {
+@@ -953,6 +955,7 @@ make_regs (struct gdbarch *arch)
+       set_gdbarch_ptr_bit (arch, 64);
+     }
+ }
++#endif
+ 
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+@@ -964,7 +967,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+  /* What has the user specified from the command line?  */
+   wanted_abi = global_microblaze_abi ();
+   if (gdbarch_debug)
+-    fprintf_unfiltered (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n",
++    gdb_printf (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n",
+                         wanted_abi);
+   if (wanted_abi != MICROBLAZE_ABI_AUTO)
+     microblaze_abi = wanted_abi;
+@@ -1038,6 +1041,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   gdbarch *gdbarch
+     = gdbarch_alloc (&info, gdbarch_tdep_up (new microblaze_gdbarch_tdep));
+ 
++  microblaze_gdbarch_tdep *tdep = gdbarch_tdep<microblaze_gdbarch_tdep> (gdbarch);
++
+   tdep->gregset = NULL;
+   tdep->sizeof_gregset = 0;
+   tdep->fpregset = NULL;
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch
new file mode 100644
index 00000000..d7e51502
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch
@@ -0,0 +1,28 @@
+From 389711a13933a60323d368d5e5f1f54bd171b16b Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 29 Feb 2024 10:55:16 +0530
+Subject: [PATCH 11/54] fix gdb microblaze-xilinx-elf crash issue on invocation
+ Regression from merging microblaze 64-bit support
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/microblaze-tdep.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index f7d9d6419ce..d4b9ef837e5 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -1124,6 +1124,9 @@ void _initialize_microblaze_tdep ();
+ void
+ _initialize_microblaze_tdep ()
+ {
++  //Setting abi to auto manually, should be able to modify in 'arch'_gdbarch_init function
++  microblaze_abi_string = microblaze_abi_strings[0]; 
++
+   gdbarch_register (bfd_arch_microblaze, microblaze_gdbarch_init);
+ 
+ // static struct cmd_list_element *setmicroblazecmdlist = NULL;
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0013-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0013-Disable-the-warning-message-for-eh_frame_hdr.patch
new file mode 100644
index 00000000..8e966788
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0013-Disable-the-warning-message-for-eh_frame_hdr.patch
@@ -0,0 +1,35 @@
+From ee4f6d0c1ea82b531d7481692e499fc0b35c88a8 Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Fri, 22 Jun 2012 01:20:20 +0200
+Subject: [PATCH 13/54] Disable the warning message for eh_frame_hdr
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+
+Conflicts:
+        bfd/elf-eh-frame.c
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elf-eh-frame.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c
+index bf7a9902355..21029b59632 100644
+--- a/bfd/elf-eh-frame.c
++++ b/bfd/elf-eh-frame.c
+@@ -1045,10 +1045,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
+   goto success;
+ 
+  free_no_table:
++/* FIXME: Remove the microblaze specifics when relaxing gets fixed.  */
++if (bfd_get_arch(abfd) != bfd_arch_microblaze) {
+   _bfd_error_handler
+     /* xgettext:c-format */
+     (_("error in %pB(%pA); no .eh_frame_hdr table will be created"),
+      abfd, sec);
++}
+   hdr_info->u.dwarf.table = false;
+   free (sec_info);
+  success:
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0015-upstream-change-to-garbage-collection-sweep-causes-m.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0015-upstream-change-to-garbage-collection-sweep-causes-m.patch
new file mode 100644
index 00000000..41118c1a
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0015-upstream-change-to-garbage-collection-sweep-causes-m.patch
@@ -0,0 +1,43 @@
+From 6531ec7f986fff48b9efc883526018f494cf88fb Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Wed, 27 Feb 2013 13:56:11 +1000
+Subject: [PATCH 15/54] upstream change to garbage collection sweep causes mb
+ regression
+
+Upstream change for PR13177 now clears the def_regular during gc_sweep of a
+section. (All other archs in binutils/bfd/elf32-*.c received an update
+to a warning about unresolvable relocations - this warning is not present
+in binutils/bfd/elf32-microblaze.c, but this warning check would not
+prevent the error being seen)
+
+The visible issue with this change is when running a c++ application
+in Petalinux which links libstdc++.so for exception handling it segfaults
+on execution.
+
+This does not occur if static linking libstdc++.a, so its during the
+relocations for a shared lib with garbage collection this occurs
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+
+Conflicts:
+        bfd/elflink.c
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elflink.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/bfd/elflink.c b/bfd/elflink.c
+index ca162145f7e..0524019641e 100644
+--- a/bfd/elflink.c
++++ b/bfd/elflink.c
+@@ -6608,7 +6608,6 @@ elf_gc_sweep_symbol (struct elf_link_hash_entry *h, void *data)
+ 
+       inf = (struct elf_gc_sweep_symbol_info *) data;
+       (*inf->hide_symbol) (inf->info, h, true);
+-      h->def_regular = 0;
+       h->ref_regular = 0;
+       h->ref_regular_nonweak = 0;
+     }
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0016-Add-new-bit-field-instructions.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0016-Add-new-bit-field-instructions.patch
new file mode 100644
index 00000000..30a7322d
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0016-Add-new-bit-field-instructions.patch
@@ -0,0 +1,88 @@
+From 50a52ab3ad64b8525a970744dbb1c5f67dc24886 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 18 Jul 2016 12:24:28 +0530
+Subject: [PATCH 16/54] Add new bit-field instructions
+
+This patches adds new bsefi and bsifi instructions.
+BSEFI- The instruction shall extract a bit field from a
+register and place it right-adjusted in the destination register.
+The other bits in the destination register shall be set to zero
+BSIFI- The instruction shall insert a right-adjusted bit field
+from a register at another position in the destination register.
+The rest of the bits in the destination register shall be unchanged
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+
+Conflicts:
+        opcodes/microblaze-dis.c
+
+Conflicts:
+        gas/config/tc-microblaze.c
+        opcodes/microblaze-opc.h
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++-
+ opcodes/microblaze-dis.c   | 18 +++++++++-
+ opcodes/microblaze-opc.h   |  6 ++++
+ 3 files changed, 93 insertions(+), 2 deletions(-)
+
+Index: gdb-14.2/opcodes/microblaze-dis.c
+===================================================================
+--- gdb-14.2.orig/opcodes/microblaze-dis.c
++++ gdb-14.2/opcodes/microblaze-dis.c
+@@ -113,7 +113,19 @@ get_field_immw (struct string_buf *buf,
+ }
+ 
+ static char *
+-get_field_rfsl (struct string_buf *buf, long instr)
++get_field_imm5width (struct string_buf *buf, long instr)
++{
++  char *p = strbuf (buf);
++
++  if (instr & 0x00004000)
++    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
++ else
++    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
++  return p;
++}
++
++static char *
++get_field_rfsl (struct string_buf *buf,long instr)
+ {
+   char *p = strbuf (buf);
+ 
+@@ -462,6 +474,10 @@ print_insn_microblaze (bfd_vma memaddr,
+          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst),
+                   get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+          break;
++        /* For bit field insns.  */
++       case INST_TYPE_RD_R1_IMM5_IMM5:
++          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
++            break;
+        /* For tuqula instruction */
+        case INST_TYPE_RD:
+          print_func (stream, "\t%s", get_field_rd (&buf, inst));
+Index: gdb-14.2/opcodes/microblaze-opc.h
+===================================================================
+--- gdb-14.2.orig/opcodes/microblaze-opc.h
++++ gdb-14.2/opcodes/microblaze-opc.h
+@@ -68,6 +68,9 @@
+ #define INST_TYPE_R1_IMML 24
+ #define INST_TYPE_RD_R1_IMMW_IMMS  21
+ 
++/* For bsefi and bsifi */
++#define INST_TYPE_RD_R1_IMM5_IMM5  21
++
+ #define INST_TYPE_NONE 25
+ 
+ 
+@@ -587,5 +590,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMML  ((long) 0xffffff8000000000L)
+ #define MAX_IMML  ((long) 0x0000007fffffffffL)
+ 
++#define MIN_IMM_WIDTH  ((int) 0x00000001)
++#define MAX_IMM_WIDTH  ((int) 0x00000020)
++
+ #endif /* MICROBLAZE_OPC */
+ 
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0019-initial-support-for-MicroBlaze-64-bit-m64.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0019-initial-support-for-MicroBlaze-64-bit-m64.patch
new file mode 100644
index 00000000..dc78da6b
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0019-initial-support-for-MicroBlaze-64-bit-m64.patch
@@ -0,0 +1,150 @@
+From 45f177e5de751f11c2d084c4d836d7f8ef754cb4 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 1 Nov 2021 19:06:53 +0530
+Subject: [PATCH 19/54] initial support for MicroBlaze 64 bit [-m64]
+
+Conflicts:
+        bfd/elf32-microblaze.c
+        include/elf/common.h
+        ld/Makefile.am
+        ld/Makefile.in
+signed-off-by:Nagaraju Mekala<nmekala@xilinx.com>
+              Mahesh Bodapati<mbodapat@xilinx.com>
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/bfd-in2.h              | 10 ++++++++++
+ bfd/libbfd.h               |  2 ++
+ bfd/reloc.c                | 12 ++++++++++++
+ gas/config/tc-microblaze.h |  4 +++-
+ ld/Makefile.am             |  2 ++
+ ld/configure.tgt           |  3 +++
+ opcodes/microblaze-dis.c   |  8 ++++++--
+ opcodes/microblaze-opc.h   | 11 +++++++----
+ 8 files changed, 45 insertions(+), 7 deletions(-)
+
+Index: gdb-14.2/bfd/bfd-in2.h
+===================================================================
+--- gdb-14.2.orig/bfd/bfd-in2.h
++++ gdb-14.2/bfd/bfd-in2.h
+@@ -6489,12 +6489,22 @@ done here - only used for relaxing  */
+     BFD_RELOC_MICROBLAZE_64_NONE,
+ 
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
++ *  +value in two words (with an imml instruction).  No relocation is
++ *   +done here - only used for relaxing  */
++    BFD_RELOC_MICROBLAZE_64,
++
++/* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  The relocation is
+ PC-relative GOT offset  */
+   BFD_RELOC_MICROBLAZE_64_GOTPC,
+ 
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imml instruction).  The relocation is
++PC-relative GOT offset  */
++  BFD_RELOC_MICROBLAZE_64_GPC,
++
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++value in two words (with an imml instruction).  The relocation is
+ PC-relative GOT offset  */
+   BFD_RELOC_MICROBLAZE_64_GPC,
+ 
+Index: gdb-14.2/bfd/libbfd.h
+===================================================================
+--- gdb-14.2.orig/bfd/libbfd.h
++++ gdb-14.2/bfd/libbfd.h
+@@ -3012,7 +3012,9 @@ static const char *const bfd_reloc_code_
+   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
+   "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
++  "BFD_RELOC_MICROBLAZE_64",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
++  "BFD_RELOC_MICROBLAZE_64_GPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+   "BFD_RELOC_MICROBLAZE_64_PLT",
+   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
+Index: gdb-14.2/bfd/reloc.c
+===================================================================
+--- gdb-14.2.orig/bfd/reloc.c
++++ gdb-14.2/bfd/reloc.c
+@@ -6703,6 +6703,12 @@ ENUMDOC
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
++  This is a 32 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imml instruction).  No relocation is
++  done here - only used for relaxing
++ENUM
++  BFD_RELOC_MICROBLAZE_64
++ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  No relocation is
+   done here - only used for relaxing
+@@ -6710,6 +6716,12 @@ ENUM
+   BFD_RELOC_MICROBLAZE_64_GOTPC
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imml instruction).  No relocation is
++  done here - only used for relaxing
++ENUM
++  BFD_RELOC_MICROBLAZE_64_GPC
++ENUMDOC
++  This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  The relocation is
+   PC-relative GOT offset
+ ENUM
+Index: gdb-14.2/opcodes/microblaze-dis.c
+===================================================================
+--- gdb-14.2.orig/opcodes/microblaze-dis.c
++++ gdb-14.2/opcodes/microblaze-dis.c
+@@ -457,6 +457,10 @@ print_insn_microblaze (bfd_vma memaddr,
+        case INST_TYPE_R1_R2_SPECIAL:
+          print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
+                      get_field_r2 (&buf, inst));
++          break;
++        case INST_TYPE_IMML:
++         print_func (stream, "\t%s", get_field_imml (&buf, inst));
++          /* TODO: Also print symbol */
+          break;
+        case INST_TYPE_RD_IMM15:
+          print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
+@@ -475,8 +479,8 @@ print_insn_microblaze (bfd_vma memaddr,
+                   get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+          break;
+         /* For bit field insns.  */
+-       case INST_TYPE_RD_R1_IMM5_IMM5:
+-          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
++       case INST_TYPE_RD_R1_IMMW_IMMS:
++          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+             break;
+        /* For tuqula instruction */
+        case INST_TYPE_RD:
+Index: gdb-14.2/opcodes/microblaze-opc.h
+===================================================================
+--- gdb-14.2.orig/opcodes/microblaze-opc.h
++++ gdb-14.2/opcodes/microblaze-opc.h
+@@ -69,7 +69,13 @@
+ #define INST_TYPE_RD_R1_IMMW_IMMS  21
+ 
+ /* For bsefi and bsifi */
+-#define INST_TYPE_RD_R1_IMM5_IMM5  21
++#define INST_TYPE_RD_R1_IMMW_IMMS  21
++
++/* For 64-bit instructions */
++#define INST_TYPE_IMML 22
++#define INST_TYPE_RD_R1_IMML 23
++#define INST_TYPE_R1_IMML 24
++#define INST_TYPE_RD_R1_IMMW_IMMS  21
+ 
+ #define INST_TYPE_NONE 25
+ 
+@@ -590,8 +596,5 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMML  ((long) 0xffffff8000000000L)
+ #define MAX_IMML  ((long) 0x0000007fffffffffL)
+ 
+-#define MIN_IMM_WIDTH  ((int) 0x00000001)
+-#define MAX_IMM_WIDTH  ((int) 0x00000020)
+-
+ #endif /* MICROBLAZE_OPC */
+ 
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0020-initial-support-for-MicroBlaze-64-bit-m64.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0020-initial-support-for-MicroBlaze-64-bit-m64.patch
new file mode 100644
index 00000000..a1efcf41
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0020-initial-support-for-MicroBlaze-64-bit-m64.patch
@@ -0,0 +1,82 @@
+From 8ec9b2fe49c8e1e367213fa0b8d6b6f0fedc3456 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 1 Nov 2021 19:06:53 +0530
+Subject: [PATCH 20/54] initial support for MicroBlaze 64 bit [-m64]
+
+Conflicts:
+        bfd/elf32-microblaze.c
+        include/elf/common.h
+        ld/Makefile.am
+        ld/Makefile.in
+signed-off-by:Nagaraju Mekala<nmekala@xilinx.com>
+              Mahesh Bodapati<mbodapat@xilinx.com>
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ ld/emulparams/elf64microblaze.sh   | 23 +++++++++++++++++++++++
+ ld/emulparams/elf64microblazeel.sh | 23 +++++++++++++++++++++++
+ 2 files changed, 46 insertions(+)
+ create mode 100644 ld/emulparams/elf64microblaze.sh
+ create mode 100644 ld/emulparams/elf64microblazeel.sh
+
+diff --git a/ld/emulparams/elf64microblaze.sh b/ld/emulparams/elf64microblaze.sh
+new file mode 100644
+index 00000000000..9c7b0eb7080
+--- /dev/null
++++ b/ld/emulparams/elf64microblaze.sh
+@@ -0,0 +1,23 @@
++SCRIPT_NAME=elfmicroblaze
++OUTPUT_FORMAT="elf64-microblazeel"
++#BIG_OUTPUT_FORMAT="elf64-microblaze"
++LITTLE_OUTPUT_FORMAT="elf64-microblazeel"
++#TEXT_START_ADDR=0
++NONPAGED_TEXT_START_ADDR=0x28
++ALIGNMENT=4
++MAXPAGESIZE=4
++ARCH=microblaze
++EMBEDDED=yes
++
++NOP=0x80000000
++
++# Hmmm, there's got to be a better way.  This sets the stack to the
++# top of the simulator memory (2^19 bytes).
++#PAGE_SIZE=0x1000
++#DATA_ADDR=0x10000
++#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }'
++#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
++#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
++
++TEMPLATE_NAME=elf32
++#GENERATE_SHLIB_SCRIPT=yes
+diff --git a/ld/emulparams/elf64microblazeel.sh b/ld/emulparams/elf64microblazeel.sh
+new file mode 100644
+index 00000000000..9c7b0eb7080
+--- /dev/null
++++ b/ld/emulparams/elf64microblazeel.sh
+@@ -0,0 +1,23 @@
++SCRIPT_NAME=elfmicroblaze
++OUTPUT_FORMAT="elf64-microblazeel"
++#BIG_OUTPUT_FORMAT="elf64-microblaze"
++LITTLE_OUTPUT_FORMAT="elf64-microblazeel"
++#TEXT_START_ADDR=0
++NONPAGED_TEXT_START_ADDR=0x28
++ALIGNMENT=4
++MAXPAGESIZE=4
++ARCH=microblaze
++EMBEDDED=yes
++
++NOP=0x80000000
++
++# Hmmm, there's got to be a better way.  This sets the stack to the
++# top of the simulator memory (2^19 bytes).
++#PAGE_SIZE=0x1000
++#DATA_ADDR=0x10000
++#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }'
++#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
++#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
++
++TEMPLATE_NAME=elf32
++#GENERATE_SHLIB_SCRIPT=yes
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0021-Added-relocations-for-MB-X.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0021-Added-relocations-for-MB-X.patch
new file mode 100644
index 00000000..caf24b8d
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0021-Added-relocations-for-MB-X.patch
@@ -0,0 +1,69 @@
+From 818a103460da557761aacc0d21b9b087721d2d3e Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 11 Sep 2018 17:30:17 +0530
+Subject: [PATCH 21/54] Added relocations for MB-X
+
+Conflicts:
+        bfd/bfd-in2.h
+        gas/config/tc-microblaze.c
+
+Conflicts:
+        gas/config/tc-microblaze.c
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/reloc.c                | 26 ++++++++++++++------------
+ gas/config/tc-microblaze.c | 11 +++++++++++
+ 2 files changed, 25 insertions(+), 12 deletions(-)
+
+Index: gdb-14.2/bfd/reloc.c
+===================================================================
+--- gdb-14.2.orig/bfd/reloc.c
++++ gdb-14.2/bfd/reloc.c
+@@ -6703,12 +6703,6 @@ ENUMDOC
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
+-  This is a 32 bit reloc that stores the 32 bit pc relative
+-  value in two words (with an imml instruction).  No relocation is
+-  done here - only used for relaxing
+-ENUM
+-  BFD_RELOC_MICROBLAZE_64
+-ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  No relocation is
+   done here - only used for relaxing
+@@ -6716,12 +6710,6 @@ ENUM
+   BFD_RELOC_MICROBLAZE_64_GOTPC
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+-  value in two words (with an imml instruction).  No relocation is
+-  done here - only used for relaxing
+-ENUM
+-  BFD_RELOC_MICROBLAZE_64_GPC
+-ENUMDOC
+-  This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  The relocation is
+   PC-relative GOT offset
+ ENUM
+@@ -7976,6 +7964,20 @@ ENUMX
+ ENUMDOC
+   Linux eBPF relocations.
+ 
++  This is a 64 bit reloc that stores 64-bit thread pointer relative offset
++  to two words (uses imml instruction).
++ENUM
++BFD_RELOC_MICROBLAZE_64,
++ENUMDOC
++ This is a 64 bit reloc that stores the 64 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
++ENUM
++BFD_RELOC_MICROBLAZE_64_PCREL,
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
+ ENUM
+   BFD_RELOC_EPIPHANY_SIMM8
+ ENUMDOC
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0022-initial-support-for-MicroBlaze-64-bit-m64.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0022-initial-support-for-MicroBlaze-64-bit-m64.patch
new file mode 100644
index 00000000..2023287a
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0022-initial-support-for-MicroBlaze-64-bit-m64.patch
@@ -0,0 +1,113 @@
+From 587d5179ce81a4f67ebec321063f6c3c9b1673cb Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 1 Nov 2021 19:06:53 +0530
+Subject: [PATCH 22/54] initial support for MicroBlaze 64 bit [-m64]
+
+Conflicts:
+        bfd/elf32-microblaze.c
+        include/elf/common.h
+        ld/Makefile.am
+        ld/Makefile.in
+signed-off-by:Nagaraju Mekala<nmekala@xilinx.com>
+              Mahesh Bodapati<mbodapat@xilinx.com>
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elf64-microblaze.c     |   8 +
+ bfd/reloc.c                |  42 ++-
+ gas/config/tc-microblaze.c | 558 ++++++++++++++++++++++++++++++++-----
+ 3 files changed, 507 insertions(+), 101 deletions(-)
+
+Index: gdb-14.2/bfd/elf64-microblaze.c
+===================================================================
+--- gdb-14.2.orig/bfd/elf64-microblaze.c
++++ gdb-14.2/bfd/elf64-microblaze.c
+@@ -1666,6 +1666,14 @@ microblaze_elf_relocate_section (bfd *ou
+                            outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL);
+                            outrel.r_addend = relocation + addend;
+                          }
++                       unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
++                        if (insn == 0xb2000000 || insn == 0xb2ffffff)
++                          {
++                            insn &= ~0x00ffffff;
++                            insn |= (relocation >> 16) & 0xffffff;
++                            bfd_put_32 (input_bfd, insn,
++                                    contents + offset + endian);
++                          }
+                        else
+                          {
+                            BFD_FAIL ();
+Index: gdb-14.2/bfd/reloc.c
+===================================================================
+--- gdb-14.2.orig/bfd/reloc.c
++++ gdb-14.2/bfd/reloc.c
+@@ -6703,13 +6703,31 @@ ENUMDOC
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
++  This is a 32 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imml instruction).  No relocation is
++  done here - only used for relaxing
++ENUM
++  BFD_RELOC_MICROBLAZE_64
++ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  No relocation is
+   done here - only used for relaxing
+ ENUM
++BFD_RELOC_MICROBLAZE_64_PCREL,
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
++ENUM
+   BFD_RELOC_MICROBLAZE_64_GOTPC
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imml instruction).  No relocation is
++  done here - only used for relaxing
++ENUM
++  BFD_RELOC_MICROBLAZE_64_GPC
++ENUMDOC
++  This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  The relocation is
+   PC-relative GOT offset
+ ENUM
+@@ -7942,18 +7960,6 @@ ENUMDOC
+   This is a 64 bit reloc that stores 64-bit thread pointer relative offset
+   to two words (uses imml instruction).
+ ENUM
+-BFD_RELOC_MICROBLAZE_64,
+-ENUMDOC
+- This is a 64 bit reloc that stores the 64 bit pc relative
+- value in two words (with an imml instruction).  No relocation is
+- done here - only used for relaxing
+-ENUM
+-BFD_RELOC_MICROBLAZE_64_PCREL,
+-ENUMDOC
+- This is a 32 bit reloc that stores the 32 bit pc relative
+- value in two words (with an imml instruction).  No relocation is
+- done here - only used for relaxing
+-ENUM
+   BFD_RELOC_BPF_64
+ ENUMX
+   BFD_RELOC_BPF_DISP32
+@@ -7967,18 +7973,6 @@ ENUMDOC
+   This is a 64 bit reloc that stores 64-bit thread pointer relative offset
+   to two words (uses imml instruction).
+ ENUM
+-BFD_RELOC_MICROBLAZE_64,
+-ENUMDOC
+- This is a 64 bit reloc that stores the 64 bit pc relative
+- value in two words (with an imml instruction).  No relocation is
+- done here - only used for relaxing
+-ENUM
+-BFD_RELOC_MICROBLAZE_64_PCREL,
+-ENUMDOC
+- This is a 32 bit reloc that stores the 32 bit pc relative
+- value in two words (with an imml instruction).  No relocation is
+- done here - only used for relaxing
+-ENUM
+   BFD_RELOC_EPIPHANY_SIMM8
+ ENUMDOC
+   Adapteva EPIPHANY - 8 bit signed pc-relative displacement
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0023-Added-relocations-for-MB-X.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0023-Added-relocations-for-MB-X.patch
new file mode 100644
index 00000000..54b0cc45
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0023-Added-relocations-for-MB-X.patch
@@ -0,0 +1,84 @@
+From 4992c1383473b2a37551b7391f1eb836d2a447d3 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 11 Sep 2018 17:30:17 +0530
+Subject: [PATCH 23/54] Added relocations for MB-X
+
+Conflicts:
+        bfd/bfd-in2.h
+        gas/config/tc-microblaze.c
+
+Conflicts:
+        gas/config/tc-microblaze.c
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/libbfd.h               |  2 --
+ bfd/reloc.c                | 26 ++++++++-------
+ gas/config/tc-microblaze.c | 68 ++++++++++++--------------------------
+ 3 files changed, 36 insertions(+), 60 deletions(-)
+
+Index: gdb-14.2/bfd/libbfd.h
+===================================================================
+--- gdb-14.2.orig/bfd/libbfd.h
++++ gdb-14.2/bfd/libbfd.h
+@@ -3012,9 +3012,7 @@ static const char *const bfd_reloc_code_
+   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
+   "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
+-  "BFD_RELOC_MICROBLAZE_64",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
+-  "BFD_RELOC_MICROBLAZE_64_GPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+   "BFD_RELOC_MICROBLAZE_64_PLT",
+   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
+Index: gdb-14.2/bfd/reloc.c
+===================================================================
+--- gdb-14.2.orig/bfd/reloc.c
++++ gdb-14.2/bfd/reloc.c
+@@ -6669,6 +6669,20 @@ ENUM
+ ENUMDOC
+   Address of a GOT entry.
+ 
++  This is a 64 bit reloc that stores 64-bit thread pointer relative offset
++  to two words (uses imml instruction).
++ENUM
++BFD_RELOC_MICROBLAZE_64,
++ENUMDOC
++ This is a 64 bit reloc that stores the 64 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
++ENUM
++BFD_RELOC_MICROBLAZE_64_PCREL,
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
+ ENUM
+   BFD_RELOC_MICROBLAZE_32_LO
+ ENUMDOC
+@@ -6707,12 +6721,6 @@ ENUMDOC
+   value in two words (with an imml instruction).  No relocation is
+   done here - only used for relaxing
+ ENUM
+-  BFD_RELOC_MICROBLAZE_64
+-ENUMDOC
+-  This is a 64 bit reloc that stores the 32 bit pc relative
+-  value in two words (with an imm instruction).  No relocation is
+-  done here - only used for relaxing
+-ENUM
+ BFD_RELOC_MICROBLAZE_64_PCREL,
+ ENUMDOC
+  This is a 32 bit reloc that stores the 32 bit pc relative
+@@ -6725,12 +6733,6 @@ ENUMDOC
+   value in two words (with an imml instruction).  No relocation is
+   done here - only used for relaxing
+ ENUM
+-  BFD_RELOC_MICROBLAZE_64_GPC
+-ENUMDOC
+-  This is a 64 bit reloc that stores the 32 bit pc relative
+-  value in two words (with an imm instruction).  The relocation is
+-  PC-relative GOT offset
+-ENUM
+   BFD_RELOC_MICROBLAZE_64_GOT
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0025-Fixed-address-computation-issues-with-64bit-address-.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0025-Fixed-address-computation-issues-with-64bit-address-.patch
new file mode 100644
index 00000000..e495e207
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0025-Fixed-address-computation-issues-with-64bit-address-.patch
@@ -0,0 +1,35 @@
+From 33e22262c6c43af6e7e075df0665838b5b3859a6 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 9 Oct 2018 10:14:22 +0530
+Subject: [PATCH 25/54] - Fixed address computation issues with 64bit address -
+ Fixed imml dissassamble issue
+
+Conflicts:
+        gas/config/tc-microblaze.c
+        opcodes/microblaze-dis.c
+
+Conflicts:
+        bfd/elf64-microblaze.c
+
+Conflicts:
+        bfd/elf64-microblaze.c
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elf64-microblaze.c     |  2 +-
+ gas/config/tc-microblaze.c | 74 +++++++++++++++++++++++++++++++++-----
+ 2 files changed, 67 insertions(+), 9 deletions(-)
+
+Index: gdb-14.2/bfd/elf64-microblaze.c
+===================================================================
+--- gdb-14.2.orig/bfd/elf64-microblaze.c
++++ gdb-14.2/bfd/elf64-microblaze.c
+@@ -2131,7 +2131,7 @@ microblaze_elf_relax_section (bfd *abfd,
+                efix = calc_fixup (target_address, 0, sec);
+ 
+             /* Validate the in-band val.  */
+-            val = bfd_get_32 (abfd, contents + irel->r_offset);
++            val = bfd_get_64 (abfd, contents + irel->r_offset);
+             if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
+                fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
+             }
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0028-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0028-fixing-the-long-long-long-mingw-toolchain-issue.patch
new file mode 100644
index 00000000..f6598cee
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0028-fixing-the-long-long-long-mingw-toolchain-issue.patch
@@ -0,0 +1,26 @@
+From 646b229752b9816b25d2b9ffe79b895b69742745 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 29 Nov 2018 17:59:25 +0530
+Subject: [PATCH 28/54] fixing the long & long long mingw toolchain issue
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c | 10 +++++-----
+ opcodes/microblaze-opc.h   |  4 ++--
+ 2 files changed, 7 insertions(+), 7 deletions(-)
+
+Index: gdb-14.2/opcodes/microblaze-opc.h
+===================================================================
+--- gdb-14.2.orig/opcodes/microblaze-opc.h
++++ gdb-14.2/opcodes/microblaze-opc.h
+@@ -593,8 +593,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM6_WIDTH  ((int) 0x00000001)
+ #define MAX_IMM6_WIDTH  ((int) 0x00000040)
+ 
+-#define MIN_IMML  ((long) 0xffffff8000000000L)
+-#define MAX_IMML  ((long) 0x0000007fffffffffL)
++#define MIN_IMML  ((long long) 0xffffff8000000000L)
++#define MAX_IMML  ((long long) 0x0000007fffffffffL)
+ 
+ #endif /* MICROBLAZE_OPC */
+ 
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0029-Added-support-to-new-arithmetic-single-register-inst.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0029-Added-support-to-new-arithmetic-single-register-inst.patch
new file mode 100644
index 00000000..8e9585a0
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0029-Added-support-to-new-arithmetic-single-register-inst.patch
@@ -0,0 +1,176 @@
+From 1a9a688939dfbf7cca9685b326c0387672c567b4 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Fri, 23 Aug 2019 16:18:43 +0530
+Subject: [PATCH 29/54] Added support to new arithmetic single register
+ instructions
+
+Conflicts:
+        opcodes/microblaze-dis.c
+
+Conflicts:
+        gas/config/tc-microblaze.c
+        opcodes/microblaze-dis.c
+
+Conflicts:
+        gas/config/tc-microblaze.c
+signed-off-by:Nagaraju <nmekala@xilinx.com>
+              Mahesh <mbodapat@xilinx.com>
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c | 147 ++++++++++++++++++++++++++++++++++++-
+ opcodes/microblaze-dis.c   |  11 +++
+ opcodes/microblaze-opc.h   |  43 ++++++++++-
+ opcodes/microblaze-opcm.h  |   5 +-
+ 4 files changed, 200 insertions(+), 6 deletions(-)
+
+Index: gdb-14.2/opcodes/microblaze-dis.c
+===================================================================
+--- gdb-14.2.orig/opcodes/microblaze-dis.c
++++ gdb-14.2/opcodes/microblaze-dis.c
+@@ -143,6 +143,14 @@ get_field_imm15 (struct string_buf *buf,
+   return p;
+ }
+ 
++get_field_imm16 (struct string_buf *buf, long instr)
++{
++  char *p = strbuf (buf);
++
++  sprintf (p, "%d", (short)((instr & IMM16_MASK) >> IMM_LOW));
++  return p;
++}
++
+ static char *
+ get_field_special (struct string_buf *buf, long instr,
+                   const struct op_code_struct *op)
+@@ -473,6 +481,9 @@ print_insn_microblaze (bfd_vma memaddr,
+          /* For mbar 16 or sleep insn.  */
+        case INST_TYPE_NONE:
+          break;
++       case INST_TYPE_RD_IMML:
++         print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst));
++          break;
+         /* For bit field insns.  */
+        case INST_TYPE_RD_R1_IMMW_IMMS:
+          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst),
+Index: gdb-14.2/opcodes/microblaze-opc.h
+===================================================================
+--- gdb-14.2.orig/opcodes/microblaze-opc.h
++++ gdb-14.2/opcodes/microblaze-opc.h
+@@ -78,6 +78,7 @@
+ #define INST_TYPE_RD_R1_IMMW_IMMS  21
+ 
+ #define INST_TYPE_NONE 25
++#define INST_TYPE_RD_IMML 26
+ 
+ 
+ 
+@@ -93,6 +94,7 @@
+ #define IMMVAL_MASK_MFS 0x0000
+ 
+ #define OPCODE_MASK_H     0xFC000000 /* High 6 bits only.  */
++#define OPCODE_MASK_LIMM 0xFC1F0000 /* High 6 bits and 12-16 bits */
+ #define OPCODE_MASK_H1    0xFFE00000 /* High 11 bits.  */
+ #define OPCODE_MASK_H2    0xFC1F0000 /* High 6 and bits 20-16.  */
+ #define OPCODE_MASK_H12   0xFFFF0000 /* High 16.  */
+@@ -115,6 +117,33 @@
+ #define OPCODE_MASK_H34C  0xFC0007E0 /* High 6 bits and bits 21-26.  */
+ #define OPCODE_MASK_H8    0xFF000000 /* High 8 bits only.  */
+ 
++/*Defines to identify 64-bit single reg instructions */
++#define ADDLI_ONE_REG_MASK 0x68000000
++#define ADDLIC_ONE_REG_MASK 0x68020000
++#define ADDLIK_ONE_REG_MASK 0x68040000
++#define ADDLIKC_ONE_REG_MASK 0x68060000
++#define RSUBLI_ONE_REG_MASK 0x68010000
++#define RSUBLIC_ONE_REG_MASK 0x68030000
++#define RSUBLIK_ONE_REG_MASK 0x68050000
++#define RSUBLIKC_ONE_REG_MASK 0x68070000
++#define ORLI_ONE_REG_MASK 0x68100000
++#define ANDLI_ONE_REG_MASK 0x68110000
++#define XORLI_ONE_REG_MASK 0x68120000
++#define ANDLNI_ONE_REG_MASK 0x68130000
++#define ADDLI_MASK 0x20000000
++#define ADDLIC_MASK 0x28000000
++#define ADDLIK_MASK 0x30000000
++#define ADDLIKC_MASK 0x38000000
++#define RSUBLI_MASK 0x24000000
++#define RSUBLIC_MASK 0x2C000000
++#define RSUBLIK_MASK 0x34000000
++#define RSUBLIKC_MASK 0x3C000000
++#define ANDLI_MASK 0xA4000000
++#define ANDLNI_MASK 0xAC000000
++#define ORLI_MASK 0xA0000000
++#define XORLI_MASK 0xA8000000
++
++
+ /* New Mask for msrset, msrclr insns.  */
+ #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16.  */
+ /* Mask for mbar insn.  */
+@@ -123,7 +152,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 412
++#define MAX_OPCODES 424
+ 
+ const struct op_code_struct
+ {
+@@ -452,13 +481,21 @@ const struct op_code_struct
+   {"cmpl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
+   {"cmplu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
+   {"addli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68000000, OPCODE_MASK_LIMM, addli, arithmetic_inst },
+   {"rsubli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsubli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68010000, OPCODE_MASK_LIMM, rsubli, arithmetic_inst },
+   {"addlic",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68020000, OPCODE_MASK_LIMM, addlic, arithmetic_inst },
+   {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++    {"rsublic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68030000, OPCODE_MASK_LIMM, rsublic, arithmetic_inst },
+   {"addlik",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68040000, OPCODE_MASK_LIMM, addlik, arithmetic_inst },
+   {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsublik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68050000, OPCODE_MASK_LIMM, rsublik, arithmetic_inst },
+   {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68060000, OPCODE_MASK_LIMM, addlikc, arithmetic_inst },
+   {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },  /* Identical to 32-bit */
++  {"rsublikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68070000, OPCODE_MASK_LIMM, rsublikc, arithmetic_inst },
+   {"mull",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
+   {"bslll",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
+   {"bslra",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
+@@ -509,9 +546,13 @@ const struct op_code_struct
+   {"beaged",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
+   {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
+   {"orli",    INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"orli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68100000, OPCODE_MASK_LIMM, orli, arithmetic_inst },
+   {"andli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"andli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68110000, OPCODE_MASK_LIMM, andli, arithmetic_inst },
+   {"xorli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"xorli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68120000, OPCODE_MASK_LIMM, xorli, arithmetic_inst },
+   {"andnli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"andnli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68130000, OPCODE_MASK_LIMM, andnli, arithmetic_inst },
+   {"imml",    INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
+   {"breai",   INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
+   {"breaid",  INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
+Index: gdb-14.2/opcodes/microblaze-opcm.h
+===================================================================
+--- gdb-14.2.orig/opcodes/microblaze-opcm.h
++++ gdb-14.2/opcodes/microblaze-opcm.h
+@@ -62,7 +62,9 @@ enum microblaze_instr
+   eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
+ 
+   /* 64-bit instructions */
+-  addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++  addl, addli, addlic, addlik, addlikc, rsubl, rsubli, rsublic, rsublik, rsublikc,
++  addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++  andli, andnli, orli, xorli,
+   bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
+   andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
+   brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
+@@ -167,5 +169,6 @@ enum microblaze_instr_type
+ 
+ /* Imm mask for msrset, msrclr instructions.  */
+ #define  IMM15_MASK 0x00007FFF
++#define IMM16_MASK 0x0000FFFF
+ 
+ #endif /* MICROBLAZE-OPCM */
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0030-double-imml-generation-for-64-bit-values.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0030-double-imml-generation-for-64-bit-values.patch
new file mode 100644
index 00000000..72b9cc9f
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0030-double-imml-generation-for-64-bit-values.patch
@@ -0,0 +1,29 @@
+From 6967f52fe0ebebb4bdf437cb1e683d9e87a013ff Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 26 Aug 2019 15:29:42 +0530
+Subject: [PATCH 30/54] double imml generation for 64 bit values.
+
+Conflicts:
+        gas/config/tc-microblaze.c
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c | 321 ++++++++++++++++++++++++++++++-------
+ opcodes/microblaze-opc.h   |   4 +-
+ 2 files changed, 262 insertions(+), 63 deletions(-)
+
+Index: gdb-14.2/opcodes/microblaze-opc.h
+===================================================================
+--- gdb-14.2.orig/opcodes/microblaze-opc.h
++++ gdb-14.2/opcodes/microblaze-opc.h
+@@ -634,8 +634,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM6_WIDTH  ((int) 0x00000001)
+ #define MAX_IMM6_WIDTH  ((int) 0x00000040)
+ 
+-#define MIN_IMML  ((long long) 0xffffff8000000000L)
+-#define MAX_IMML  ((long long) 0x0000007fffffffffL)
++#define MIN_IMML  ((long long) -9223372036854775808)
++#define MAX_IMML  ((long long) 9223372036854775807)
+ 
+ #endif /* MICROBLAZE_OPC */
+ 
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch
new file mode 100644
index 00000000..700ec4c3
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch
@@ -0,0 +1,44 @@
+From 9ff4551a70734606139f3ecd146cf0a1c45e0fb0 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 8 Nov 2021 22:01:23 +0530
+Subject: [PATCH 35/54] ld/emulparams/elf64microblaze: Fix emulation generation
+
+Compilation fails when building ld-new with:
+
+ldemul.o:(.data.rel+0x820): undefined reference to `ld_elf64microblazeel_emulation'
+ldemul.o:(.data.rel+0x828): undefined reference to `ld_elf64microblaze_emulation'
+
+The error appears to be that the elf64 files were referencing the elf32 emulation.
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ ld/emulparams/elf64microblaze.sh   | 2 +-
+ ld/emulparams/elf64microblazeel.sh | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/ld/emulparams/elf64microblaze.sh b/ld/emulparams/elf64microblaze.sh
+index 9c7b0eb7080..7b4c7c411bd 100644
+--- a/ld/emulparams/elf64microblaze.sh
++++ b/ld/emulparams/elf64microblaze.sh
+@@ -19,5 +19,5 @@ NOP=0x80000000
+ #$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
+ #OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
+ 
+-TEMPLATE_NAME=elf32
++TEMPLATE_NAME=elf
+ #GENERATE_SHLIB_SCRIPT=yes
+diff --git a/ld/emulparams/elf64microblazeel.sh b/ld/emulparams/elf64microblazeel.sh
+index 9c7b0eb7080..7b4c7c411bd 100644
+--- a/ld/emulparams/elf64microblazeel.sh
++++ b/ld/emulparams/elf64microblazeel.sh
+@@ -19,5 +19,5 @@ NOP=0x80000000
+ #$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
+ #OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
+ 
+-TEMPLATE_NAME=elf32
++TEMPLATE_NAME=elf
+ #GENERATE_SHLIB_SCRIPT=yes
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch
new file mode 100644
index 00000000..88c0dc4e
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch
@@ -0,0 +1,79 @@
+From a233cd9a21bc94c47c1d33cc10a9e24a5d5b8126 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 24 Jan 2022 16:04:07 +0530
+Subject: [PATCH 36/54] Invalid data offsets (pointer) after relaxation.
+ Proposed patch from community member (dednev@rambler.ru) against 2021.1
+ [CR-1115232]
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elf32-microblaze.c | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 6ba28e757be..7a4d35493e9 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -2174,6 +2174,9 @@ microblaze_elf_relax_section (bfd *abfd,
+                 {
+                   unsigned int val;
+ 
++                 if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                   continue;
++
+                   isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+                   /* hax: We only do the following fixup for debug location lists.  */
+@@ -2213,6 +2216,9 @@ microblaze_elf_relax_section (bfd *abfd,
+               }
+               if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)// || ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64)
+                 {
++                 if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                   continue;
++
+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+                  /* Look at the reloc only if the value has been resolved.  */
+@@ -2245,6 +2251,9 @@ microblaze_elf_relax_section (bfd *abfd,
+                    }
+                  else if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_SYM_OP_SYM)
+                    {
++                     if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                       continue;
++
+                      isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+                      /* Look at the reloc only if the value has been resolved.  */
+@@ -2282,6 +2291,9 @@ microblaze_elf_relax_section (bfd *abfd,
+                       || (ELF32_R_TYPE (irelscan->r_info)
+                                   == (int) R_MICROBLAZE_TEXTREL_32_LO))
+                {
++                 if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                   continue;
++
+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+                  /* Look at the reloc only if the value has been resolved.  */
+@@ -2328,6 +2340,9 @@ microblaze_elf_relax_section (bfd *abfd,
+                  || (ELF32_R_TYPE (irelscan->r_info)
+                              == (int) R_MICROBLAZE_TEXTREL_64))
+                {
++                 if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                   continue;
++
+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+                  /* Look at the reloc only if the value has been resolved.  */
+@@ -2362,6 +2377,9 @@ microblaze_elf_relax_section (bfd *abfd,
+                }
+              else if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_PCREL)
+                {
++                 if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info)
++                   continue;
++
+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+                  /* Look at the reloc only if the value has been resolved.  */
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch
new file mode 100644
index 00000000..3cae48dc
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch
@@ -0,0 +1,107 @@
+From 2d0e4a0b3a9ce2ffebc5892cf34219ac01a2475e Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 24 Jan 2022 16:59:19 +0530
+Subject: [PATCH 37/54] Double free with ld --no-keep-memory. Proposed patches
+ from the community member (dednev@rambler.ru) for 2021.1. [CR-1115233]
+
+Conflicts:
+        bfd/elf32-microblaze.c
+        bfd/elf64-microblaze.c
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elf32-microblaze.c | 40 ++++++++++++++++++++++------------------
+ 1 file changed, 22 insertions(+), 18 deletions(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 7a4d35493e9..554a80ae0e4 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1881,10 +1881,8 @@ microblaze_elf_relax_section (bfd *abfd,
+ {
+   Elf_Internal_Shdr *symtab_hdr;
+   Elf_Internal_Rela *internal_relocs;
+-  Elf_Internal_Rela *free_relocs = NULL;
+   Elf_Internal_Rela *irel, *irelend;
+   bfd_byte *contents = NULL;
+-  bfd_byte *free_contents = NULL;
+   int rel_count;
+   unsigned int shndx;
+   size_t i, sym_index;
+@@ -1928,8 +1926,6 @@ microblaze_elf_relax_section (bfd *abfd,
+   internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory);
+   if (internal_relocs == NULL)
+     goto error_return;
+-  if (! link_info->keep_memory)
+-    free_relocs = internal_relocs;
+ 
+   sdata->relax_count = 0;
+   sdata->relax = (struct relax_table *) bfd_malloc ((sec->reloc_count + 1)
+@@ -1957,7 +1953,6 @@ microblaze_elf_relax_section (bfd *abfd,
+              contents = (bfd_byte *) bfd_malloc (sec->size);
+              if (contents == NULL)
+                goto error_return;
+-             free_contents = contents;
+ 
+              if (!bfd_get_section_contents (abfd, sec, contents,
+                                             (file_ptr) 0, sec->size))
+@@ -2473,25 +2468,26 @@ microblaze_elf_relax_section (bfd *abfd,
+        }
+ 
+       elf_section_data (sec)->relocs = internal_relocs;
+-      free_relocs = NULL;
+ 
+       elf_section_data (sec)->this_hdr.contents = contents;
+-      free_contents = NULL;
+ 
+       symtab_hdr->contents = (bfd_byte *) isymbuf;
+     }
+ 
+-  free (free_relocs);
+-  free_relocs = NULL;
++  if (internal_relocs != NULL
++      && elf_section_data (sec)->relocs != internal_relocs)
++    free (internal_relocs);
+ 
+-  if (free_contents != NULL)
+-    {
+-      if (!link_info->keep_memory)
+-       free (free_contents);
++  if (contents != NULL
++      && elf_section_data (sec)->this_hdr.contents != contents)
++   {
++      if (! link_info->keep_memory)
++       free (contents);
+       else
+-       /* Cache the section contents for elf_link_input_bfd.  */
+-       elf_section_data (sec)->this_hdr.contents = contents;
+-      free_contents = NULL;
++       {
++         /* Cache the section contents for elf_link_input_bfd.  */
++         elf_section_data (sec)->this_hdr.contents = contents;
++       }
+     }
+ 
+   if (sdata->relax_count == 0)
+@@ -2505,8 +2501,16 @@ microblaze_elf_relax_section (bfd *abfd,
+   return true;
+ 
+  error_return:
+-  free (free_relocs);
+-  free (free_contents);
++ 
++  if (isymbuf != NULL
++      && symtab_hdr->contents != (unsigned char *) isymbuf)
++    free (isymbuf);
++  if (internal_relocs != NULL
++      && elf_section_data (sec)->relocs != internal_relocs)
++    free (internal_relocs);
++  if (contents != NULL
++      && elf_section_data (sec)->this_hdr.contents != contents)
++    free (contents);
+   free (sdata->relax);
+   sdata->relax = NULL;
+   sdata->relax_count = 0;
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0038-MB-binutils-Upstream-port-issues.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0038-MB-binutils-Upstream-port-issues.patch
new file mode 100644
index 00000000..a27a9807
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0038-MB-binutils-Upstream-port-issues.patch
@@ -0,0 +1,83 @@
+From 06e678ebb6c136c85f73ba8a4a064f9050ae47ce Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sun, 28 Nov 2021 17:17:15 +0530
+Subject: [PATCH 38/54] MB binutils Upstream port issues.
+
+It's resolving the seg faults with ADDLIK
+Conflicts:
+        bfd/elf64-microblaze.c
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c |  2 +-
+ opcodes/microblaze-dis.c   | 12 ++++++------
+ opcodes/microblaze-opc.h   |  2 +-
+ 3 files changed, 8 insertions(+), 8 deletions(-)
+
+Index: gdb-14.2/opcodes/microblaze-dis.c
+===================================================================
+--- gdb-14.2.orig/opcodes/microblaze-dis.c
++++ gdb-14.2/opcodes/microblaze-dis.c
+@@ -153,7 +153,7 @@ get_field_imm16 (struct string_buf *buf,
+ 
+ static char *
+ get_field_special (struct string_buf *buf, long instr,
+-                  const struct op_code_struct *op)
++                  struct op_code_struct *op)
+ {
+   char *p = strbuf (buf);
+   char *spr;
+@@ -226,11 +226,11 @@ get_field_special (struct string_buf *bu
+ static unsigned long
+ read_insn_microblaze (bfd_vma memaddr,
+                      struct disassemble_info *info,
+-                     const struct op_code_struct **opr)
++                     struct op_code_struct **opr)
+ {
+   unsigned char       ibytes[4];
+   int                 status;
+-  const struct op_code_struct *op;
++  struct op_code_struct *op;
+   unsigned long inst;
+ 
+   status = info->read_memory_func (memaddr, ibytes, 4, info);
+@@ -266,7 +266,7 @@ print_insn_microblaze (bfd_vma memaddr,
+   fprintf_ftype print_func = info->fprintf_func;
+   void *stream = info->stream;
+   unsigned long inst, prev_inst;
+-  const struct op_code_struct *op, *pop;
++  struct op_code_struct *op, *pop;
+   int immval = 0;
+   bool immfound = false;
+   static bfd_vma prev_insn_addr = -1;  /* Init the prev insn addr.  */
+@@ -518,7 +518,7 @@ get_insn_microblaze (long inst,
+                     enum microblaze_instr_type *insn_type,
+                     short *delay_slots)
+ {
+-  const struct op_code_struct *op;
++  struct op_code_struct *op;
+   *isunsignedimm = false;
+ 
+   /* Just a linear search of the table.  */
+@@ -560,7 +560,7 @@ microblaze_get_target_address (long inst
+                               bool *targetvalid,
+                               bool *unconditionalbranch)
+ {
+-  const struct op_code_struct *op;
++  struct op_code_struct *op;
+   long targetaddr = 0;
+ 
+   *unconditionalbranch = false;
+Index: gdb-14.2/opcodes/microblaze-opc.h
+===================================================================
+--- gdb-14.2.orig/opcodes/microblaze-opc.h
++++ gdb-14.2/opcodes/microblaze-opc.h
+@@ -154,7 +154,7 @@
+ 
+ #define MAX_OPCODES 424
+ 
+-const struct op_code_struct
++struct op_code_struct
+ {
+   const char * name;
+   short inst_type;            /* Registers and immediate values involved.  */
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0039-Initial-port-of-core-reading-support-Added-support-f.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0039-Initial-port-of-core-reading-support-Added-support-f.patch
new file mode 100644
index 00000000..3372de27
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0039-Initial-port-of-core-reading-support-Added-support-f.patch
@@ -0,0 +1,89 @@
+From e907440fcfce0828efa7b059ef0c6d61c7736d02 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 10 Oct 2022 16:37:53 +0530
+Subject: [PATCH 39/54] Initial port of core reading support Added support for
+ reading notes in linux core dumps Support for reading of PRSTATUS and PSINFO
+ information for rebuilding ".reg" sections of core dumps at run time.
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/microblaze-linux-tdep.c | 11 +++++++++++
+ gdb/microblaze-tdep.c       | 37 +++++++++++++++++++++++++++++++++++++
+ 2 files changed, 48 insertions(+)
+
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 39592a43f7c..20daef2ccd4 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -193,6 +193,17 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+   set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
+   set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
+ 
++  /* BFD target for core files.  */
++  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++  else
++    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++
++
++  /* Shared library handling.  */
++  set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
++  set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
++
+   /* Enable TLS support.  */
+   set_gdbarch_fetch_tls_load_module_address (gdbarch,
+                                              svr4_fetch_objfile_link_map);
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index d4b9ef837e5..363fee34040 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -957,6 +957,43 @@ make_regs (struct gdbarch *arch)
+ }
+ #endif
+ 
++void
++microblaze_supply_gregset (const struct regset *regset,
++                        struct regcache *regcache,
++                        int regnum, const void *gregs)
++{
++  const unsigned int *regs = (const unsigned int *)gregs;
++  if (regnum >= 0)
++    regcache->raw_supply (regnum, regs + regnum);
++
++  if (regnum == -1) {
++    int i;
++
++    for (i = 0; i < 50; i++) {
++      regcache->raw_supply (i, regs + i);
++    }
++  }
++}
++
++
++/* Return the appropriate register set for the core section identified
++   by SECT_NAME and SECT_SIZE.  */
++
++static void
++microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
++                                     iterate_over_regset_sections_cb *cb,
++                                     void *cb_data,
++                                     const struct regcache *regcache)
++{
++  struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch);
++
++  cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data);
++
++  cb(".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
++}
++
++
++
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ {
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch
new file mode 100644
index 00000000..3ea09e7e
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch
@@ -0,0 +1,185 @@
+From 73b456c4d8f64ec01b170a49330e6de66716eb1a Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 14 Mar 2024 10:41:33 +0530
+Subject: [PATCH 40/54] Fix build issues after Xilinx 2023.2 binutils merge
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/bfd-in2.h            | 10 ------
+ gdb/microblaze-tdep.c    | 71 ++++++++++++++--------------------------
+ opcodes/microblaze-dis.c | 10 ------
+ 3 files changed, 25 insertions(+), 66 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 9dcf233f19f..4b022dbfba1 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -6473,11 +6473,6 @@ done here - only used for relaxing  */
+  *   +done here - only used for relaxing  */
+     BFD_RELOC_MICROBLAZE_64_PCREL,
+ 
+-/* This is a 64 bit reloc that stores the 32 bit relative
+- *  +value in two words (with an imml instruction).  No relocation is
+- *   +done here - only used for relaxing  */
+-    BFD_RELOC_MICROBLAZE_64,
+-
+ /* This is a 64 bit reloc that stores the 32 bit relative
+  *  +value in two words (with an imml instruction).  No relocation is
+  *   +done here - only used for relaxing  */
+@@ -6503,11 +6498,6 @@ value in two words (with an imml instruction).  The relocation is
+ PC-relative GOT offset  */
+   BFD_RELOC_MICROBLAZE_64_GPC,
+ 
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
+-value in two words (with an imml instruction).  The relocation is
+-PC-relative GOT offset  */
+-  BFD_RELOC_MICROBLAZE_64_GPC,
+-
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  The relocation is
+ GOT offset  */
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 363fee34040..818306f2197 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -70,6 +70,7 @@ static const char *microblaze_abi_string;
+ static const char *const microblaze_abi_strings[] = {
+   "auto",
+   "m64",
++  NULL
+ };
+ 
+ enum microblaze_abi
+@@ -105,7 +106,7 @@ global_microblaze_abi (void)
+     if (microblaze_abi_strings[i] == microblaze_abi_string)
+       return (enum microblaze_abi) i;
+ 
+-//  internal_error (__FILE__, __LINE__, _("unknown ABI string"));
++  internal_error (__FILE__, __LINE__, _("unknown ABI string"));
+ }
+ 
+ static void
+@@ -894,16 +895,31 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
+ }
+ 
+ static void
+-microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
++microblaze_register_g_packet_guesses (struct gdbarch *gdbarch, enum microblaze_abi abi)
+ {
+ 
+-  register_remote_g_packet_guess (gdbarch,
+-                                 4 * MICROBLAZE_NUM_CORE_REGS,
+-                                 tdesc_microblaze64);
++  if (abi == MICROBLAZE_ABI_M64) 
++    {
++
++      register_remote_g_packet_guess (gdbarch,
++                                     8 * MICROBLAZE_NUM_CORE_REGS,
++                                     tdesc_microblaze64);
++
++      register_remote_g_packet_guess (gdbarch,
++                                     8 * MICROBLAZE_NUM_REGS,
++                                     tdesc_microblaze64_with_stack_protect);
++    } 
++  else 
++    {
++
++      register_remote_g_packet_guess (gdbarch,
++                                     4 * MICROBLAZE_NUM_CORE_REGS,
++                                     tdesc_microblaze);
+ 
+-  register_remote_g_packet_guess (gdbarch,
+-                                 4 * MICROBLAZE_NUM_REGS,
+-                                 tdesc_microblaze64_with_stack_protect);
++      register_remote_g_packet_guess (gdbarch,
++                                     4 * MICROBLAZE_NUM_REGS,
++                                     tdesc_microblaze_with_stack_protect);
++    }
+ }
+ 
+ void
+@@ -957,43 +973,6 @@ make_regs (struct gdbarch *arch)
+ }
+ #endif
+ 
+-void
+-microblaze_supply_gregset (const struct regset *regset,
+-                        struct regcache *regcache,
+-                        int regnum, const void *gregs)
+-{
+-  const unsigned int *regs = (const unsigned int *)gregs;
+-  if (regnum >= 0)
+-    regcache->raw_supply (regnum, regs + regnum);
+-
+-  if (regnum == -1) {
+-    int i;
+-
+-    for (i = 0; i < 50; i++) {
+-      regcache->raw_supply (i, regs + i);
+-    }
+-  }
+-}
+-
+-
+-/* Return the appropriate register set for the core section identified
+-   by SECT_NAME and SECT_SIZE.  */
+-
+-static void
+-microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
+-                                     iterate_over_regset_sections_cb *cb,
+-                                     void *cb_data,
+-                                     const struct regcache *regcache)
+-{
+-  struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch);
+-
+-  cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data);
+-
+-  cb(".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
+-}
+-
+-
+-
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ {
+@@ -1134,7 +1113,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ 
+   set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc);
+ 
+-  //microblaze_register_g_packet_guesses (gdbarch);
++  // microblaze_register_g_packet_guesses (gdbarch, microblaze_abi);
+ 
+   frame_base_set_default (gdbarch, &microblaze_frame_base);
+ 
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 540ddecafd4..00712d5eaf1 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -466,10 +466,6 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+          print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
+                      get_field_r2 (&buf, inst));
+           break;
+-        case INST_TYPE_IMML:
+-         print_func (stream, "\t%s", get_field_imml (&buf, inst));
+-          /* TODO: Also print symbol */
+-         break;
+        case INST_TYPE_RD_IMM15:
+          print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
+                      get_field_imm15 (&buf, inst));
+@@ -484,12 +480,6 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+        case INST_TYPE_RD_IMML:
+          print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst));
+           break;
+-        /* For bit field insns.  */
+-       case INST_TYPE_RD_R1_IMMW_IMMS:
+-         print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst),
+-                  get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+-         break;
+-        /* For bit field insns.  */
+        case INST_TYPE_RD_R1_IMMW_IMMS:
+           print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+             break;
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0041-disable-truncated-register-warning-gdb-remote.c.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0041-disable-truncated-register-warning-gdb-remote.c.patch
new file mode 100644
index 00000000..6f5a5f1e
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0041-disable-truncated-register-warning-gdb-remote.c.patch
@@ -0,0 +1,26 @@
+From a96aee31c41e4d851531100a0716401c3464f6ef Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 14 Mar 2024 15:44:56 +0530
+Subject: [PATCH 41/54] disable truncated register warning (gdb/remote.c)
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/remote.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gdb/remote.c b/gdb/remote.c
+index ae08c980efc..8055c8f62e6 100644
+--- a/gdb/remote.c
++++ b/gdb/remote.c
+@@ -8678,7 +8678,7 @@ remote_target::process_g_packet (struct regcache *regcache)
+          if (rsa->regs[i].pnum == -1)
+            continue;
+ 
+-         if (offset >= sizeof_g_packet)
++         if (offset >= sizeof_g_packet || (offset + reg_size > sizeof_g_packet))
+            rsa->regs[i].in_g_packet = 0;
+          else if (offset + reg_size > sizeof_g_packet)
+            error (_("Truncated register %d in remote 'g' packet"), i);
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch
new file mode 100644
index 00000000..0b5f27b4
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch
@@ -0,0 +1,42 @@
+From f9ffc37f48bd9213e89c8821cd07fc679e113007 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 28 Mar 2024 10:20:48 +0530
+Subject: [PATCH 42/54] Fix unresolved conflicts from binutils_2_42_merge
+
+opcodes/microblaze-dis.c
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ opcodes/microblaze-dis.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 00712d5eaf1..31dbad46b75 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -478,11 +478,16 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+        case INST_TYPE_NONE:
+          break;
+        case INST_TYPE_RD_IMML:
+-         print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst));
+-          break;
+-       case INST_TYPE_RD_R1_IMMW_IMMS:
+-          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+-            break;
++         print_func (stream, "\t%s, %s", 
++                 get_field_rd (&buf, inst), get_field_imm16 (&buf, inst));
++         break;
++       case INST_TYPE_RD_R1_IMMW_IMMS:
++         print_func (stream, "\t%s, %s, %s, %s", 
++                 get_field_rd (&buf, inst),
++                 get_field_r1(&buf, inst),
++                 get_field_immw (&buf, inst), 
++                 get_field_imms (&buf, inst));
++         break;
+        /* For tuqula instruction */
+        case INST_TYPE_RD:
+          print_func (stream, "\t%s", get_field_rd (&buf, inst));
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch
new file mode 100644
index 00000000..5e1fb44f
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch
@@ -0,0 +1,177 @@
+From 03df31becbc7dc6d35189fec3b4b2c7dfd3a8103 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 28 Mar 2024 10:59:40 +0530
+Subject: [PATCH 43/54] microblaze_gdbarch_init: set microblaze_abi based on
+ wanted_abi and found_abi
+
+Earlier found_abi was declared but not set, instead gdbarch_info info
+was checked every time. Also, microblaze_abi remained undefined for 32-bit
+machines. As a result, gdb would show 64-bit registers when connecting
+to 32-bit targets with all register values garbled (r5 ended up in r2).
+This defect is fixed. found_abi is set from gdbarch_info, microblaze_abi
+is set based on wanted_abi and found_abi. Now upon connecting to a 32-bit
+remote target (mb-qemu) registers have the correct 32-bit size.
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/microblaze-tdep.c | 73 +++++++++++++++++++------------------------
+ 1 file changed, 33 insertions(+), 40 deletions(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 818306f2197..47863819724 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -116,7 +116,7 @@ show_microblaze_abi (struct ui_file *file,
+                const char *ignored_value)
+ {
+       enum microblaze_abi global_abi = global_microblaze_abi ();
+-      enum microblaze_abi actual_abi = microblaze_abi (target_gdbarch ());
++      enum microblaze_abi actual_abi = microblaze_abi (current_inferior ()->arch ());
+       const char *actual_abi_str = microblaze_abi_strings[actual_abi];
+ 
+ #if 1 
+@@ -203,6 +203,13 @@ microblaze_register_name (struct gdbarch *gdbarch, int regnum)
+ static struct type *
+ microblaze_register_type (struct gdbarch *gdbarch, int regnum)
+ {
++
++  int mb_reg_size = microblaze_abi_regsize(gdbarch);
++
++  if (gdbarch_debug)
++    gdb_printf (gdb_stdlog, "microblaze_register_type: reg_size = %d\n",
++                        mb_reg_size);
++
+   if (regnum == MICROBLAZE_SP_REGNUM)
+     return builtin_type (gdbarch)->builtin_data_ptr;
+ 
+@@ -980,34 +987,38 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   enum microblaze_abi microblaze_abi, found_abi, wanted_abi;
+   const struct target_desc *tdesc = info.target_desc;
+ 
++  /* If there is already a candidate, use it.  */
++  arches = gdbarch_list_lookup_by_info (arches, &info);
++  if ((arches != NULL) && (microblaze_abi != MICROBLAZE_ABI_M64))
++    return arches->gdbarch;
++
+  /* What has the user specified from the command line?  */
+   wanted_abi = global_microblaze_abi ();
+   if (gdbarch_debug)
+     gdb_printf (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n",
+                         wanted_abi);
++
++  found_abi = MICROBLAZE_ABI_AUTO;
++
++  if (info.bfd_arch_info->mach == bfd_mach_microblaze64) 
++    found_abi = MICROBLAZE_ABI_M64;
++
+   if (wanted_abi != MICROBLAZE_ABI_AUTO)
+     microblaze_abi = wanted_abi;
+-
+-  /* If there is already a candidate, use it.  */
+-  arches = gdbarch_list_lookup_by_info (arches, &info);
+-  if ((arches != NULL) && (microblaze_abi != MICROBLAZE_ABI_M64))
+-    return arches->gdbarch;
++  else
++    microblaze_abi = found_abi;
+ 
+   if (microblaze_abi == MICROBLAZE_ABI_M64)
+     {
+-          tdesc = tdesc_microblaze64;
+-          reg_size = 8;
++      tdesc = tdesc_microblaze64;
++      reg_size = 8;
+     }
+-  if (tdesc == NULL)
++  else 
+     {
+-      if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) 
+-        {
+-         tdesc = tdesc_microblaze64;
+-          reg_size = 8;
+-       }
+-      else
+-       tdesc = tdesc_microblaze;
++      tdesc = tdesc_microblaze;
++      reg_size = 4;
+     }
++
+   /* Check any target description for validity.  */
+   if (tdesc_has_registers (tdesc))
+     {
+@@ -1015,7 +1026,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+       int valid_p;
+       int i;
+ 
+-      if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64))
++      if (microblaze_abi == MICROBLAZE_ABI_M64)
+         feature = tdesc_find_feature (tdesc,
+                                     "org.gnu.gdb.microblaze64.core");
+       else
+@@ -1029,7 +1040,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+       for (i = 0; i < MICROBLAZE_NUM_REGS; i++)
+         valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), i,
+                                             microblaze_register_names[i]);
+-      if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64))
++      if (microblaze_abi == MICROBLAZE_ABI_M64)
+         feature = tdesc_find_feature (tdesc,
+                                     "org.gnu.gdb.microblaze64.stack-protect");
+       else
+@@ -1075,15 +1086,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   
+   /* Register set.  
+   make_regs (gdbarch); */
+-  switch (info.bfd_arch_info->mach)
+-    {
+-    case bfd_mach_microblaze64:
+-      set_gdbarch_ptr_bit (gdbarch, 64);
+-    break;
+-    }
+-  if(microblaze_abi == MICROBLAZE_ABI_M64)
++  if (microblaze_abi == MICROBLAZE_ABI_M64)
+     set_gdbarch_ptr_bit (gdbarch, 64);
+-  
++  else
++    set_gdbarch_ptr_bit (gdbarch, 32);
++
+   /* Map Dwarf2 registers to GDB registers.  */
+   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum);
+ 
+@@ -1105,8 +1112,6 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+                                       microblaze_breakpoint::bp_from_kind);
+ //  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
+ 
+-//  set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+-
+   set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+ 
+   set_gdbarch_frame_args_skip (gdbarch, 8);
+@@ -1145,9 +1150,6 @@ _initialize_microblaze_tdep ()
+ 
+   gdbarch_register (bfd_arch_microblaze, microblaze_gdbarch_init);
+ 
+-// static struct cmd_list_element *setmicroblazecmdlist = NULL;
+-// static struct cmd_list_element *showmicroblazecmdlist = NULL;
+-
+   /* Add root prefix command for all "set microblaze"/"show microblaze" commands.  */
+  
+   add_setshow_prefix_cmd ("microblaze", no_class,
+@@ -1155,15 +1157,6 @@ _initialize_microblaze_tdep ()
+                         _("Various microblaze specific commands."),
+                         &setmicroblazecmdlist,&showmicroblazecmdlist,
+                         &setlist,&showlist);
+-#if 0
+-  add_prefix_cmd ("microblaze", no_class, set_microblaze_command,
+-                  _("Various microblaze specific commands."),
+-                  &setmicroblazecmdlist, "set microblaze ", 0, &setlist);
+-
+-  add_prefix_cmd ("microblaze", no_class, show_microblaze_command,
+-                  _("Various microblaze specific commands."),
+-                  &showmicroblazecmdlist, "show microblaze ", 0, &showlist);
+-#endif
+ 
+   /* Allow the user to override the ABI.  */
+   add_setshow_enum_cmd ("abi", class_obscure, microblaze_abi_strings,
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch
new file mode 100644
index 00000000..f949a982
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch
@@ -0,0 +1,32 @@
+From 254bd83017b21301c73e7501c71b2cf128ac18d9 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 28 Mar 2024 11:36:32 +0530
+Subject: [PATCH 44/54] Start bfd_mach_microblaze values from 0 (0,1) instead
+ of (1,2)
+
+Before 64-bit support there was only bfd_mach_microblaze (implicitly set to 0),
+setting microblaze_mach_microblaze64 to 1
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/archures.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/bfd/archures.c b/bfd/archures.c
+index 2994a09bc37..e552349319f 100644
+--- a/bfd/archures.c
++++ b/bfd/archures.c
+@@ -515,8 +515,8 @@ DESCRIPTION
+ .  bfd_arch_lm32,      {* Lattice Mico32.  *}
+ .#define bfd_mach_lm32         1
+ .  bfd_arch_microblaze,{* Xilinx MicroBlaze.  *}
+-.#define bfd_mach_microblaze   1
+-.#define bfd_mach_microblaze64 2
++.#define bfd_mach_microblaze   0
++.#define bfd_mach_microblaze64 1
+ .  bfd_arch_kvx,        {* Kalray VLIW core of the MPPA processor family *}
+ .#define bfd_mach_kv3_unknown       0
+ .#define bfd_mach_kv3_1             1
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch
new file mode 100644
index 00000000..6e4137ef
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch
@@ -0,0 +1,61 @@
+From b2377a83918c814fd3b6ee2cd46a5f413f97a08e Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 28 Mar 2024 15:37:11 +0530
+Subject: [PATCH 45/54] Fix build issues - bfd/reloc.c add missing relocs used
+ elsewhere
+
+        BFD_RELOC_MICROBLAZE_EA64
+        BFD_RELOC_MICROBLAZE_64_GPC
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/reloc.c | 16 +++++++++++-----
+ 1 file changed, 11 insertions(+), 5 deletions(-)
+
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index fc28e27662f..5afe1518cd0 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6672,13 +6672,19 @@ ENUMDOC
+   This is a 64 bit reloc that stores 64-bit thread pointer relative offset
+   to two words (uses imml instruction).
+ ENUM
+-BFD_RELOC_MICROBLAZE_64,
++BFD_RELOC_MICROBLAZE_64
+ ENUMDOC
+  This is a 64 bit reloc that stores the 64 bit pc relative
+  value in two words (with an imml instruction).  No relocation is
+  done here - only used for relaxing
+ ENUM
+-BFD_RELOC_MICROBLAZE_64_PCREL,
++BFD_RELOC_MICROBLAZE_EA64
++ENUMDOC
++ This is a 64 bit reloc that stores the 64 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
++ENUM
++BFD_RELOC_MICROBLAZE_64_PCREL
+ ENUMDOC
+  This is a 32 bit reloc that stores the 32 bit pc relative
+  value in two words (with an imml instruction).  No relocation is
+@@ -6721,13 +6727,13 @@ ENUMDOC
+   value in two words (with an imml instruction).  No relocation is
+   done here - only used for relaxing
+ ENUM
+-BFD_RELOC_MICROBLAZE_64_PCREL,
++BFD_RELOC_MICROBLAZE_64_GOTPC
+ ENUMDOC
+- This is a 32 bit reloc that stores the 32 bit pc relative
++ This is a 64 bit reloc that stores the 32 bit pc relative
+  value in two words (with an imml instruction).  No relocation is
+  done here - only used for relaxing
+ ENUM
+-  BFD_RELOC_MICROBLAZE_64_GOTPC
++  BFD_RELOC_MICROBLAZE_64_GPC
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imml instruction).  No relocation is
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch
new file mode 100644
index 00000000..e9383c6f
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch
@@ -0,0 +1,125 @@
+From 4d201d0a948ab6160f449d41a50a6794dd3efde7 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 28 Mar 2024 15:47:56 +0530
+Subject: [PATCH 46/54] Regenerate - bfd/bfd-in2.h bfd/libbfd.h
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/bfd-in2.h | 65 +++++++++++++++++++++++++++++----------------------
+ 1 file changed, 37 insertions(+), 28 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 4b022dbfba1..171de10910c 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -1771,8 +1771,8 @@ enum bfd_architecture
+   bfd_arch_lm32,      /* Lattice Mico32.  */
+ #define bfd_mach_lm32          1
+   bfd_arch_microblaze,/* Xilinx MicroBlaze.  */
+-#define bfd_mach_microblaze    1
+-#define bfd_mach_microblaze64  2
++#define bfd_mach_microblaze    0
++#define bfd_mach_microblaze64  1
+   bfd_arch_kvx,        /* Kalray VLIW core of the MPPA processor family */
+ #define bfd_mach_kv3_unknown       0
+ #define bfd_mach_kv3_1             1
+@@ -6440,9 +6440,27 @@ the linker could optimize the movq to a leaq if possible.  */
+ /* Relative offset within page of GOT slot.  */
+   BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12,
+ 
+-/* Address of a GOT entry.  */
++/* Address of a GOT entry.
++
++This is a 64 bit reloc that stores 64-bit thread pointer relative offset
++to two words (uses imml instruction).  */
+   BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT,
+ 
++/* This is a 64 bit reloc that stores the 64 bit pc relative
++value in two words (with an imml instruction).  No relocation is
++done here - only used for relaxing  */
++  BFD_RELOC_MICROBLAZE_64,
++
++/* This is a 64 bit reloc that stores the 64 bit pc relative
++value in two words (with an imml instruction).  No relocation is
++done here - only used for relaxing  */
++  BFD_RELOC_MICROBLAZE_EA64,
++
++/* This is a 32 bit reloc that stores the 32 bit pc relative
++value in two words (with an imml instruction).  No relocation is
++done here - only used for relaxing  */
++  BFD_RELOC_MICROBLAZE_64_PCREL,
++
+ /* This is a 32 bit reloc for the microblaze that stores the
+ low 16 bits of a value  */
+   BFD_RELOC_MICROBLAZE_32_LO,
+@@ -6468,34 +6486,19 @@ value in two words (with an imm instruction).  No relocation is
+ done here - only used for relaxing  */
+   BFD_RELOC_MICROBLAZE_32_NONE,
+ 
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
+- *  +value in two words (with an imml instruction).  No relocation is
+- *   +done here - only used for relaxing  */
+-    BFD_RELOC_MICROBLAZE_64_PCREL,
+-
+-/* This is a 64 bit reloc that stores the 32 bit relative
+- *  +value in two words (with an imml instruction).  No relocation is
+- *   +done here - only used for relaxing  */
+-    BFD_RELOC_MICROBLAZE_EA64,
+-
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
+- *  +value in two words (with an imm instruction).  No relocation is
+- *   +done here - only used for relaxing  */
+-    BFD_RELOC_MICROBLAZE_64_NONE,
+-
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
+- *  +value in two words (with an imml instruction).  No relocation is
+- *   +done here - only used for relaxing  */
+-    BFD_RELOC_MICROBLAZE_64,
++/* This is a 32 bit reloc that stores the 32 bit pc relative
++value in two words (with an imml instruction).  No relocation is
++done here - only used for relaxing  */
++  BFD_RELOC_MICROBLAZE_64_NONE,
+ 
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+-value in two words (with an imm instruction).  The relocation is
+-PC-relative GOT offset  */
++value in two words (with an imml instruction).  No relocation is
++done here - only used for relaxing  */
+   BFD_RELOC_MICROBLAZE_64_GOTPC,
+ 
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+-value in two words (with an imml instruction).  The relocation is
+-PC-relative GOT offset  */
++value in two words (with an imml instruction).  No relocation is
++done here - only used for relaxing  */
+   BFD_RELOC_MICROBLAZE_64_GPC,
+ 
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+@@ -7199,7 +7202,10 @@ assembler and not (currently) written to any object files.  */
+   BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA,
+   BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA,
+ 
+-/* Tilera TILE-Gx Relocations.  */
++/* Tilera TILE-Gx Relocations.
++
++This is a 64 bit reloc that stores 64-bit thread pointer relative offset
++to two words (uses imml instruction).  */
+   BFD_RELOC_TILEGX_HW0,
+   BFD_RELOC_TILEGX_HW1,
+   BFD_RELOC_TILEGX_HW2,
+@@ -7310,7 +7316,10 @@ assembler and not (currently) written to any object files.  */
+   BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD,
+   BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD,
+ 
+-/* Linux eBPF relocations.  */
++/* Linux eBPF relocations.
++
++This is a 64 bit reloc that stores 64-bit thread pointer relative offset
++to two words (uses imml instruction).  */
+   BFD_RELOC_BPF_64,
+   BFD_RELOC_BPF_DISP32,
+   BFD_RELOC_BPF_DISPCALL32,
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch
new file mode 100644
index 00000000..d31eb8ee
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch
@@ -0,0 +1,32 @@
+From 2a1036ac7639aa3b67b1f1ad7e1a6e7c4c22704b Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 28 Mar 2024 16:32:22 +0530
+Subject: [PATCH 47/54] gdb/remote.c - revert earlier change to
+ process_g_packet
+
+When connecting to remote target, gdb (microblaze-xilinx-elf) was
+generating Truncated register 29 error when parsing the g packet,
+workaround added being reverted.
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/remote.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gdb/remote.c b/gdb/remote.c
+index 8055c8f62e6..ae08c980efc 100644
+--- a/gdb/remote.c
++++ b/gdb/remote.c
+@@ -8678,7 +8678,7 @@ remote_target::process_g_packet (struct regcache *regcache)
+          if (rsa->regs[i].pnum == -1)
+            continue;
+ 
+-         if (offset >= sizeof_g_packet || (offset + reg_size > sizeof_g_packet))
++         if (offset >= sizeof_g_packet)
+            rsa->regs[i].in_g_packet = 0;
+          else if (offset + reg_size > sizeof_g_packet)
+            error (_("Truncated register %d in remote 'g' packet"), i);
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch
new file mode 100644
index 00000000..f9cbb4a6
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch
@@ -0,0 +1,46 @@
+From 6a5887919f00da84c973ec61c59efcd7d0fb120e Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Mon, 1 Apr 2024 16:21:28 +0530
+Subject: [PATCH 48/54] Fix build issues after Xilinx 2023.2 binutils patch
+ merge
+
+binutils/readelf.c - duplicate case statement
+gas/config/tc-microblaze.c - Missing , between array elements
+gas/config/tc-microblaze.c - A whole hunk ended up in wrong function/switch
+
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/libbfd.h               |   6 +-
+ binutils/readelf.c         |   5 -
+ gas/config/tc-microblaze.c | 375 +++++++++++++++++++------------------
+ 3 files changed, 192 insertions(+), 194 deletions(-)
+
+Index: gdb-14.2/bfd/libbfd.h
+===================================================================
+--- gdb-14.2.orig/bfd/libbfd.h
++++ gdb-14.2/bfd/libbfd.h
+@@ -3005,6 +3005,9 @@ static const char *const bfd_reloc_code_
+   "BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21",
+   "BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12",
+   "BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT",
++  "BFD_RELOC_MICROBLAZE_64",
++  "BFD_RELOC_MICROBLAZE_EA64",
++  "BFD_RELOC_MICROBLAZE_64_PCREL",
+   "BFD_RELOC_MICROBLAZE_32_LO",
+   "BFD_RELOC_MICROBLAZE_32_LO_PCREL",
+   "BFD_RELOC_MICROBLAZE_32_ROSDA",
+@@ -3013,13 +3016,12 @@ static const char *const bfd_reloc_code_
+   "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
++  "BFD_RELOC_MICROBLAZE_64_GPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+   "BFD_RELOC_MICROBLAZE_64_PLT",
+   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
+   "BFD_RELOC_MICROBLAZE_32_GOTOFF",
+   "BFD_RELOC_MICROBLAZE_COPY",
+-  "BFD_RELOC_MICROBLAZE_64",
+-  "BFD_RELOC_MICROBLAZE_64_PCREL",
+   "BFD_RELOC_MICROBLAZE_64_TLS",
+   "BFD_RELOC_MICROBLAZE_64_TLSGD",
+   "BFD_RELOC_MICROBLAZE_64_TLSLD",
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0049-Add-back-R_MICROBLAZE_NONE-for-linker-relaxation-pro.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0049-Add-back-R_MICROBLAZE_NONE-for-linker-relaxation-pro.patch
new file mode 100644
index 00000000..76fcef7d
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0049-Add-back-R_MICROBLAZE_NONE-for-linker-relaxation-pro.patch
@@ -0,0 +1,27 @@
+From bf491bdb2e4d30c14968be096969da700dedfc64 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Wed, 17 Apr 2024 16:14:14 +0530
+Subject: [PATCH 49/54] Add back R_MICROBLAZE_NONE for linker relaxation
+ processing
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ bfd/elf32-microblaze.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 554a80ae0e4..ec6613b6572 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -2102,6 +2102,7 @@ microblaze_elf_relax_section (bfd *abfd,
+                                                   irel->r_addend);
+              }
+              break;
++           case R_MICROBLAZE_NONE:
+            case R_MICROBLAZE_32_NONE:
+              {
+                /* This was a PC-relative instruction that was
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0050-When-unwinding-pc-value-adjust-return-pc-value.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0050-When-unwinding-pc-value-adjust-return-pc-value.patch
new file mode 100644
index 00000000..c9da78c3
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0050-When-unwinding-pc-value-adjust-return-pc-value.patch
@@ -0,0 +1,92 @@
+From d8b25fd6d8cac000bb8f5ad65ada949447322fca Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Wed, 1 May 2024 11:12:32 +0530
+Subject: [PATCH 50/54] When unwinding pc value, adjust return pc value
+
+A call (branch and link) instruction can include a delay slot, the
+value of pc stored in the link register for Microblaze architecture
+is the pc value corresponding to last executed instruction (call)
+in the caller. The return instruction (branch reg) includes an
+offset of 8 so that when function returns execution continues from
+the address at : link register + 8, as the instruction in delay slot
+(link register + 4) is already executed at the time of call.
+
+Handle this by adjusting pc value during unwind-pc.
+
+Basically restoring code to do this that seems to have been removed
+as part of a gdb patch (gdb patch #8, Xilinx Yocto 2023.2)
+
+That patch caused hundreds of regressions in gdb testuite, including
+gdb.base/advance.exp, which is now fixed.
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/microblaze-tdep.c | 24 ++++++++++++++++++------
+ 1 file changed, 18 insertions(+), 6 deletions(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 47863819724..f87e406ada0 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -523,6 +523,12 @@ microblaze_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame)
+ {
+   CORE_ADDR pc;
+   pc=frame_unwind_register_unsigned (next_frame, MICROBLAZE_PC_REGNUM);
++  /* For sentinel frame, return address is actual PC.  For other frames,
++     return address is pc+8.  This is a workaround because gcc does not
++     generate correct return address in CIE.  */
++  if (frame_relative_level (next_frame) >= 0)
++    pc = pc + 8;
++  microblaze_debug ("unwind pc = 0x%x\n", (int) pc);
+   return pc;
+ }
+ 
+@@ -615,6 +621,7 @@ microblaze_frame_prev_register (frame_info_ptr this_frame,
+   struct microblaze_frame_cache *cache =
+     microblaze_frame_cache (this_frame, this_cache);
+ 
++#if 1
+ if ((regnum == MICROBLAZE_SP_REGNUM &&
+       cache->register_offsets[MICROBLAZE_SP_REGNUM])
+       || (regnum == MICROBLAZE_FP_REGNUM &&
+@@ -625,15 +632,22 @@ if ((regnum == MICROBLAZE_SP_REGNUM &&
+ 
+ if (regnum == MICROBLAZE_PC_REGNUM)
+ {
+-      regnum = 15;
++      regnum = MICROBLAZE_PREV_PC_REGNUM;
++
++      microblaze_debug ("prev pc is r15 @ frame offset 0x%x\n",
++                         (int) cache->register_offsets[regnum] );
++
+       return frame_unwind_got_memory (this_frame, regnum,
+                                       cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM]);
+-
+ }
++
+ if (regnum == MICROBLAZE_SP_REGNUM)
+         regnum = 1;
+-#if 0
+ 
++  return trad_frame_get_prev_register (this_frame, cache->saved_regs,
++ regnum);
++
++#else
+   if (cache->frameless_p)
+     {
+       if (regnum == MICROBLAZE_PC_REGNUM)
+@@ -646,9 +660,7 @@ if (regnum == MICROBLAZE_SP_REGNUM)
+   else
+     return trad_frame_get_prev_register (this_frame, cache->saved_regs,
+                                         regnum);
+-#endif
+-  return trad_frame_get_prev_register (this_frame, cache->saved_regs,
+-                                       regnum); 
++#endif 
+ }
+ 
+ static const struct frame_unwind microblaze_frame_unwind =
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0051-info-reg-pc-does-not-print-symbolic-value.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0051-info-reg-pc-does-not-print-symbolic-value.patch
new file mode 100644
index 00000000..887ee56e
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0051-info-reg-pc-does-not-print-symbolic-value.patch
@@ -0,0 +1,116 @@
+From 66c0cc9a030667111d4b632314502e868e5e8e37 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 9 May 2024 11:30:22 +0530
+Subject: [PATCH 51/54] info reg pc does not print symbolic value
+
+Problem - Test gdb.base/pc-fp.exp fails
+Fix - Change feature/microblaze-core.xml add type=code_ptr for pc
+
+Files changed
+        features/microblaze-core.xml
+        features/microblaze.c (generated)
+        features/microblaze-with-stack-protect.c (generated)
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/features/microblaze-core.xml             |  4 ++--
+ gdb/features/microblaze-with-stack-protect.c | 10 ++++++----
+ gdb/features/microblaze.c                    |  8 ++++----
+ 3 files changed, 12 insertions(+), 10 deletions(-)
+
+diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml
+index ac052365773..205cdf94a27 100644
+--- a/gdb/features/microblaze-core.xml
++++ b/gdb/features/microblaze-core.xml
+@@ -8,7 +8,7 @@
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze.core">
+   <reg name="r0" bitsize="32" regnum="0"/>
+-  <reg name="r1" bitsize="32"/>
++  <reg name="r1" bitsize="32" type="data_ptr"/>
+   <reg name="r2" bitsize="32"/>
+   <reg name="r3" bitsize="32"/>
+   <reg name="r4" bitsize="32"/>
+@@ -39,7 +39,7 @@
+   <reg name="r29" bitsize="32"/>
+   <reg name="r30" bitsize="32"/>
+   <reg name="r31" bitsize="32"/>
+-  <reg name="rpc" bitsize="32"/>
++  <reg name="rpc" bitsize="32" type="code_ptr"/>
+   <reg name="rmsr" bitsize="32"/>
+   <reg name="rear" bitsize="32"/>
+   <reg name="resr" bitsize="32"/>
+diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c
+index 8ab9565a047..95e3eed1a4e 100644
+--- a/gdb/features/microblaze-with-stack-protect.c
++++ b/gdb/features/microblaze-with-stack-protect.c
+@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+ 
+   feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core");
+   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
+   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
+@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
+   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
+@@ -70,10 +70,12 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+   tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+-
+-  feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.stack-protect");
+   tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int");
+ 
++  feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.stack-protect");
++  tdesc_create_reg (feature, "slr", 59, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "shr", 60, 1, NULL, 32, "int");
++
+   tdesc_microblaze_with_stack_protect = result.release ();
+ }
+diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c
+index ed12e5bcfd2..ff4865b2acc 100644
+--- a/gdb/features/microblaze.c
++++ b/gdb/features/microblaze.c
+@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void)
+ 
+   feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core");
+   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
+   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
+@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void)
+   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
+   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
+@@ -70,8 +70,8 @@ initialize_tdesc_microblaze (void)
+   tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
+-  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int");
+ 
+   tdesc_microblaze = result.release ();
+ }
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0052-Wrong-target-description-accepted-by-microblaze-arch.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0052-Wrong-target-description-accepted-by-microblaze-arch.patch
new file mode 100644
index 00000000..89318eec
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0052-Wrong-target-description-accepted-by-microblaze-arch.patch
@@ -0,0 +1,51 @@
+From 0982e0c2733aa773d88876e68320b072e5b2a9ad Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 9 May 2024 11:34:04 +0530
+Subject: [PATCH 52/54] Wrong target description accepted by microblaze
+ architecture
+
+Fix - Modify microblaze_gdbarch_init, set tdesc only when it is NULL
+
+Files changed - gdb/microblaze-tdep.c
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/microblaze-tdep.c | 21 ++++++++++++---------
+ 1 file changed, 12 insertions(+), 9 deletions(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index f87e406ada0..4d8c76bcf4c 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -1020,15 +1020,18 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   else
+     microblaze_abi = found_abi;
+ 
+-  if (microblaze_abi == MICROBLAZE_ABI_M64)
+-    {
+-      tdesc = tdesc_microblaze64;
+-      reg_size = 8;
+-    }
+-  else 
+-    {
+-      tdesc = tdesc_microblaze;
+-      reg_size = 4;
++  if (tdesc == NULL) 
++    { 
++       if (microblaze_abi == MICROBLAZE_ABI_M64)
++         {
++           tdesc = tdesc_microblaze64;
++           reg_size = 8;
++         }
++       else 
++         {
++           tdesc = tdesc_microblaze;
++           reg_size = 4;
++         }
+     }
+ 
+   /* Check any target description for validity.  */
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0053-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0053-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch
new file mode 100644
index 00000000..2cb3ff06
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0053-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch
@@ -0,0 +1,42 @@
+From 31b8744afcb31825083a23bbc08b6e00772ebd07 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Thu, 23 May 2024 16:02:59 +0530
+Subject: [PATCH 53/54] Merge gdb/microblaze-linux-tdep.c to gdb-14 and fix
+ compilation issues.
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/microblaze-linux-tdep.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 20daef2ccd4..16d3a0b5196 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -48,10 +48,12 @@ microblaze_debug (const char *fmt, ...)
+   if (microblaze_debug_flag)
+     {
+        va_list args;
++       string_file file (gdb_stdout->can_emit_style_escape ());
+ 
+        va_start (args, fmt);
+        printf_unfiltered ("MICROBLAZE LINUX: ");
+-       vprintf_unfiltered (fmt, args);
++       file.vprintf (fmt, args);
++       gdb_stdout->puts_unfiltered (file.string ().c_str ());
+        va_end (args);
+     }
+ }
+@@ -145,7 +147,7 @@ static void
+ microblaze_linux_init_abi (struct gdbarch_info info,
+                           struct gdbarch *gdbarch)
+ {
+-  struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *)  gdbarch_tdep (gdbarch);
++  struct microblaze_gdbarch_tdep *tdep = gdbarch_tdep<microblaze_gdbarch_tdep> (gdbarch);
+ 
+   tdep->sizeof_gregset = 200;
+ 
+-- 
+2.34.1
+
diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0054-Roll-back-an-improvement-which-inlines-target_gdbarc.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0054-Roll-back-an-improvement-which-inlines-target_gdbarc.patch
new file mode 100644
index 00000000..eb6bde20
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gdb/gdb/0054-Roll-back-an-improvement-which-inlines-target_gdbarc.patch
@@ -0,0 +1,29 @@
+From 8a7a8b724a87c532096004f43b987c352474a905 Mon Sep 17 00:00:00 2001
+From: Gopi Kumar Bulusu <gopi@sankhya.com>
+Date: Fri, 19 Jul 2024 12:39:24 +0530
+Subject: [PATCH 54/54] Roll back an improvement which inlines target_gdbarch
+ () inherited from binutils 2.42 merge that causes compilation issues on gdb
+ 14.2
+
+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gdb/microblaze-tdep.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 4d8c76bcf4c..cb6697654b0 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -116,7 +116,7 @@ show_microblaze_abi (struct ui_file *file,
+                const char *ignored_value)
+ {
+       enum microblaze_abi global_abi = global_microblaze_abi ();
+-      enum microblaze_abi actual_abi = microblaze_abi (current_inferior ()->arch ());
++      enum microblaze_abi actual_abi = microblaze_abi ( target_gdbarch () );
+       const char *actual_abi_str = microblaze_abi_strings[actual_abi];
+ 
+ #if 1 
+-- 
+2.34.1
+