meta-xilinx: Restructuring meta-xilinx to support multiple layers

As discussed previously on mailing list, we are proceeding with layer
restructuring. For rocko release we will have the following layers

meta-xilinx
        ->meta-xilinx-bsp (current meta-xilinx)
        ->meta-xilinx-contrib

In the subsequent releases we will add other layers from Xilinx
meta-xilinx
        ->meta-xilinx-bsp (current meta-xilinx)
        ->meta-petalinux
        ->meta-xilinx-tools
        ->meta-xilinx-contrib

This will provide one clone to get all the required meta layers from
Xilinx for a complete solution, and the users can blacklist any layer
which they don't want to use using bblayer.conf.
This will enables us to help our vendors/partners to add their reference
designs, board definitions etc.

Recipe changes :
 * Move reference design zybo-linux-bd.bb to meta-xilinx-contrib
 * Move kernel patches realted to zybo-linux-bd-zynq7 board to
   meta-xilinx-contrib
 * Update README

Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>

1 files changed, 98 insertions, 0 deletions

diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts b/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts
new file mode 100644
index 00000000..4ec64f5e
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts
@@ -0,0 +1,98 @@
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+/include/ "zynq-7000-qspi-dummy.dtsi"
+
+/ {
+        model = "Avnet picoZed";
+        compatible = "avnet,picozed", "xlnx,zynq-7000";
+
+        aliases {
+                ethernet0 = &gem0;
+                serial0 = &uart1;
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "earlyprintk";
+                stdout-path = "serial0:115200n8";
+        };
+
+        usb_phy0: phy0 {
+                compatible = "usb-nop-xceiv";
+                #phy-cells = <0>;
+                reset-gpios = <&gpio0 7 1>; /* MIO 7, GPIO_ACTIVE_LOW */
+        };
+};
+
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii-id";
+        phy-handle = <&ethernet_phy>;
+
+        ethernet_phy: ethernet-phy@0 {
+                compatible = "marvell,88e1512";
+                device_type = "ethernet-phy";
+                reg = <0>;
+        };
+};
+
+&sdhci1 {
+        status = "okay";
+        /* SD1 is onnected to a non-removable eMMC flash device */
+        non-removable;
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&usb0 {
+        status = "okay";
+        dr_mode = "host";
+        usb-phy = <&usb_phy0>;
+};
+
+&qspi {
+        status = "okay";
+        primary_flash: ps7-qspi@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "micron,m25p80", "spansion,s25fl128s", "jedec,spi-nor";
+                reg = <0x0>;
+                spi-max-frequency = <50000000>;
+                /* Example 16M partition table using U-Boot + U-Boot SPL */
+                partition@0x0 {
+                        label = "boot";
+                        reg = <0x0 0xe0000>;
+                };
+                partition@0xe0000 {
+                        label = "ubootenv";
+                        reg = <0xe0000 0x20000>;
+                };
+                partition@0x100000 {
+                        label = "uboot";
+                        reg = <0x100000 0x100000>;
+                };
+                partition@0x200000 {
+                        label = "kernel";
+                        reg = <0x200000 0x4f0000>;
+                };
+                partition@0x6f0000 {
+                        label = "devicetree";
+                        reg = <0x6f0000 0x10000>;
+                };
+                partition@0x700000 {
+                        label = "rootfs";
+                        reg = <0x700000 0x400000>;
+                };
+                partition@0xb00000 {
+                        label = "spare";
+                        reg = <0xb00000 0x500000>;
+                };
+        };
+};
+