meta-xilinx: Restructuring meta-xilinx to support multiple layers

As discussed previously on mailing list, we are proceeding with layer
restructuring. For rocko release we will have the following layers

meta-xilinx
        ->meta-xilinx-bsp (current meta-xilinx)
        ->meta-xilinx-contrib

In the subsequent releases we will add other layers from Xilinx
meta-xilinx
        ->meta-xilinx-bsp (current meta-xilinx)
        ->meta-petalinux
        ->meta-xilinx-tools
        ->meta-xilinx-contrib

This will provide one clone to get all the required meta layers from
Xilinx for a complete solution, and the users can blacklist any layer
which they don't want to use using bblayer.conf.
This will enables us to help our vendors/partners to add their reference
designs, board definitions etc.

Recipe changes :
 * Move reference design zybo-linux-bd.bb to meta-xilinx-contrib
 * Move kernel patches realted to zybo-linux-bd-zynq7 board to
   meta-xilinx-contrib
 * Update README

Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>

1 files changed, 63 insertions, 0 deletions

diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi b/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi
new file mode 100644
index 00000000..0f678d39
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi
@@ -0,0 +1,63 @@
+/*
+ * CAUTION: This file is automatically generated by Xilinx.
+ * Version: HSI 2015.4
+ * Today is: Fri Mar  4 15:40:49 2016
+*/
+
+
+/ {
+        cpus {
+                cpu@0 {
+                        operating-points = <650000 1000000 325000 1000000>;
+                };
+        };
+};
+&gem0 {
+        phy-mode = "rgmii-id";
+        status = "okay";
+        xlnx,ptp-enet-clock = <0x6750918>;
+};
+&gpio0 {
+        emio-gpio-width = <64>;
+        gpio-mask-high = <0x0>;
+        gpio-mask-low = <0x5600>;
+};
+&i2c0 {
+        clock-frequency = <400000>;
+        status = "okay";
+};
+&i2c1 {
+        clock-frequency = <400000>;
+        status = "okay";
+};
+&intc {
+        num_cpus = <2>;
+        num_interrupts = <96>;
+};
+&qspi {
+        is-dual = <0>;
+        num-cs = <1>;
+        status = "okay";
+};
+&sdhci0 {
+        status = "okay";
+        xlnx,has-cd = <0x1>;
+        xlnx,has-power = <0x0>;
+        xlnx,has-wp = <0x1>;
+};
+&uart1 {
+        current-speed = <115200>;
+        device_type = "serial";
+        port-number = <0>;
+        status = "okay";
+};
+&usb0 {
+        dr_mode = "host";
+        phy_type = "ulpi";
+        status = "okay";
+        usb-reset = <&gpio0 46 0>;
+};
+&clkc {
+        fclk-enable = <0x3>;
+        ps-clk-frequency = <50000000>;
+};