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authorManjukumar Matha <manjukumar.harthikote-matha@xilinx.com>2017-12-06 16:06:35 -0800
committerManjukumar Matha <manjukumar.harthikote-matha@xilinx.com>2017-12-13 16:11:14 -0800
commita18947c20dba2c0c38db8bde1ad4684995df4bbd (patch)
tree917bf2abbe439a6f99ede8cfafb25812dca54a9a /meta-xilinx-bsp/recipes-microblaze/gdb/files/0001-Patch-microblaze-Add-wdc.ext.clear-and-wdc.ext.flush.patch
parent6ddc5873b0ede30e6542f0ab151a6236acc37944 (diff)
downloadmeta-xilinx-a18947c20dba2c0c38db8bde1ad4684995df4bbd.tar.gz
meta-xilinx: Restructuring meta-xilinx to support multiple layers
As discussed previously on mailing list, we are proceeding with layer restructuring. For rocko release we will have the following layers meta-xilinx ->meta-xilinx-bsp (current meta-xilinx) ->meta-xilinx-contrib In the subsequent releases we will add other layers from Xilinx meta-xilinx ->meta-xilinx-bsp (current meta-xilinx) ->meta-petalinux ->meta-xilinx-tools ->meta-xilinx-contrib This will provide one clone to get all the required meta layers from Xilinx for a complete solution, and the users can blacklist any layer which they don't want to use using bblayer.conf. This will enables us to help our vendors/partners to add their reference designs, board definitions etc. Recipe changes : * Move reference design zybo-linux-bd.bb to meta-xilinx-contrib * Move kernel patches realted to zybo-linux-bd-zynq7 board to meta-xilinx-contrib * Update README Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
Diffstat (limited to 'meta-xilinx-bsp/recipes-microblaze/gdb/files/0001-Patch-microblaze-Add-wdc.ext.clear-and-wdc.ext.flush.patch')
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gdb/files/0001-Patch-microblaze-Add-wdc.ext.clear-and-wdc.ext.flush.patch69
1 files changed, 69 insertions, 0 deletions
diff --git a/meta-xilinx-bsp/recipes-microblaze/gdb/files/0001-Patch-microblaze-Add-wdc.ext.clear-and-wdc.ext.flush.patch b/meta-xilinx-bsp/recipes-microblaze/gdb/files/0001-Patch-microblaze-Add-wdc.ext.clear-and-wdc.ext.flush.patch
new file mode 100644
index 00000000..3575cd7e
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gdb/files/0001-Patch-microblaze-Add-wdc.ext.clear-and-wdc.ext.flush.patch
@@ -0,0 +1,69 @@
1From 8ab9a20c73acedbb636a41842a681872af8ae1d6 Mon Sep 17 00:00:00 2001
2From: David Holsgrove <david.holsgrove@xilinx.com>
3Date: Wed, 8 May 2013 11:03:36 +1000
4Subject: [PATCH 01/16] [Patch, microblaze]: Add wdc.ext.clear and
5 wdc.ext.flush insns
6
7Added two new instructions, wdc.ext.clear and wdc.ext.flush,
8to enable MicroBlaze to flush an external cache, which is
9used with the new coherency support for multiprocessing.
10
11Signed-off-by:nagaraju <nmekala@xilix.com>
12Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
13Upstream-Status: Pending
14---
15 opcodes/microblaze-opc.h | 5 ++++-
16 opcodes/microblaze-opcm.h | 6 +++---
17 2 files changed, 7 insertions(+), 4 deletions(-)
18
19diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
20index e3cc1d9..f453097 100644
21--- a/opcodes/microblaze-opc.h
22+++ b/opcodes/microblaze-opc.h
23@@ -91,6 +91,7 @@
24 #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
25 #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
26 #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
27+#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
28 #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
29
30 /* New Mask for msrset, msrclr insns. */
31@@ -101,7 +102,7 @@
32 #define DELAY_SLOT 1
33 #define NO_DELAY_SLOT 0
34
35-#define MAX_OPCODES 289
36+#define MAX_OPCODES 291
37
38 struct op_code_struct
39 {
40@@ -174,7 +175,9 @@ struct op_code_struct
41 {"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
42 {"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
43 {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
44+ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
45 {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
46+ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
47 {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
48 {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
49 {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
50diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
51index 6868389..8f5c1cb 100644
52--- a/opcodes/microblaze-opcm.h
53+++ b/opcodes/microblaze-opcm.h
54@@ -31,9 +31,9 @@ enum microblaze_instr
55 idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
56 ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
57 andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
58- wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
59- brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
60- bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
61+ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar,
62+ br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned,
63+ blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
64 imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
65 brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
66 bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
67--
681.9.0
69