machine/include/arm: Backport tune files from master

Backport the tune files from poky master as of commit:
dd4c941e9fe9e0f1b73a934d9ecd0d165ee85474

This adds support for cortex-r5 and cortexr-r52 hard float ABI, as well
as cortex-a78.

Signed-off-by: Mark Hatle <mark.hatle@amd.com>

3 files changed, 31 insertions, 0 deletions

diff --git a/meta-xilinx-core/conf/machine/include/arm/armv7r/tune-cortexr5hf.inc b/meta-xilinx-core/conf/machine/include/arm/armv7r/tune-cortexr5hf.inc
new file mode 100644
index 00000000..5679b989
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/include/arm/armv7r/tune-cortexr5hf.inc
@@ -0,0 +1,6 @@
+include conf/machine/include/arm/armv7r/tune-cortexr5.inc
+
+AVAILTUNES                            += "cortexr5hf"
+ARMPKGARCH:tune-cortexr5hf             = "cortexr5"
+TUNE_FEATURES:tune-cortexr5hf          = "${TUNE_FEATURES:tune-cortexr5} callconvention-hard"
+PACKAGE_EXTRA_ARCHS:tune-cortexr5hf    = "cortexr5hf-vfpv3d16"
diff --git a/meta-xilinx-core/conf/machine/include/arm/armv8-2a/tune-cortexa78.inc b/meta-xilinx-core/conf/machine/include/arm/armv8-2a/tune-cortexa78.inc
new file mode 100644
index 00000000..8c85d98e
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/include/arm/armv8-2a/tune-cortexa78.inc
@@ -0,0 +1,16 @@
+#
+# Tune Settings for Cortex-A78
+#
+DEFAULTTUNE                                        ?= "cortexa78"
+
+TUNEVALID[cortexa78] = "Enable Cortex-A78 specific processor optimizations"
+TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa78', ' -mcpu=cortex-a78', '', d)}"
+
+require conf/machine/include/arm/arch-armv8-2a.inc
+
+# Little Endian base configs
+AVAILTUNES                                         += "cortexa78"
+ARMPKGARCH:tune-cortexa78                           = "cortexa78"
+TUNE_FEATURES:tune-cortexa78                        = "${TUNE_FEATURES:tune-armv8-2a-crypto} cortexa78"
+PACKAGE_EXTRA_ARCHS:tune-cortexa78                  = "${PACKAGE_EXTRA_ARCHS:tune-armv8-2a-crypto} cortexa78"
+BASE_LIB:tune-cortexa78                             = "lib64"
diff --git a/meta-xilinx-core/conf/machine/include/arm/armv8r/tune-cortexr52hf.inc b/meta-xilinx-core/conf/machine/include/arm/armv8r/tune-cortexr52hf.inc
new file mode 100644
index 00000000..42c6fb37
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/include/arm/armv8r/tune-cortexr52hf.inc
@@ -0,0 +1,9 @@
+require conf/machine/include/arm/armv8r/tune-cortexr52.inc
+
+# simd is special, we don't pass this to the -mfpu, it's implied
+TUNE_CCARGS_MFLOAT = "${@ bb.utils.contains('TUNE_FEATURES', 'callconvention-hard', 'hard', 'softfp', d) if (d.getVar('TUNE_CCARGS_MFPU') != '' or bb.utils.contains('TUNE_FEATURES', 'simd', True, False, d)) else '' }"
+
+AVAILTUNES                             += "cortexr52hf"
+ARMPKGARCH:tune-cortexr52hf             = "cortexr52"
+TUNE_FEATURES:tune-cortexr52hf          = "${TUNE_FEATURES:tune-cortexr52} callconvention-hard"
+PACKAGE_EXTRA_ARCHS:tune-cortexr52hf    = "cortexr52hf"