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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-04-08 06:18:13 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-04-08 09:47:09 +0530 |
| commit | d43240bc686eed964a88b06d973f188f3eef5b4a (patch) | |
| tree | 60574d79ad4b30fc71c40a7adc5e672707f89a2b /meta-xilinx-core/conf | |
| parent | eae40b3fffd9cf75956405b7e16629dcee68b6f0 (diff) | |
| download | meta-xilinx-d43240bc686eed964a88b06d973f188f3eef5b4a.tar.gz | |
u-boot-xlnx : Updated SRCREV for 2024.1_5819
arm64: versal-net Add dcc node and dcc in aliases for versal-net-ipp-rev1.9.dts
mtd: spi-nor: Remove SPI_NOR_OCTAL_READ flag
soc: zynqmp: Add the IDcode for TEG variant
zlib: Remove incorrect ZLIB_VERSION
zlib: Port fix for CVE-2016-9841 to U-Boot
zlib: Rename write variable to wnext (window write index)
zlib: Rename this variable to here (current decoding table entry)
configs: versal: Disable the config for spansion flash
Diffstat (limited to 'meta-xilinx-core/conf')
0 files changed, 0 insertions, 0 deletions