diff options
| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-02-05 12:57:41 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-02-05 14:17:24 +0530 |
| commit | 5b9e2e8a4f508ff9f71ed4bc985d24df4ef43336 (patch) | |
| tree | f3c991ed2dfb0607aaf005c5e0147396716366ff /meta-xilinx-core/dynamic-layers/meta-python/recipes-devtools/python | |
| parent | 3397dd9ba02e0cd6798ce0113e011e574c2d4c6a (diff) | |
| download | meta-xilinx-5b9e2e8a4f508ff9f71ed4bc985d24df4ef43336.tar.gz | |
dts : Updated SRCREV for 2024.1_5707
versal-net: remove hardcoded ADMA addresses
zynqmp: set correct revidr value one the Cortex-A
board-versal-xcve2802: Add 2Gib OSPI flash
versal: Add vhk158 es1 board
Diffstat (limited to 'meta-xilinx-core/dynamic-layers/meta-python/recipes-devtools/python')
0 files changed, 0 insertions, 0 deletions