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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-02-06 15:51:18 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-02-06 17:27:25 +0530 |
| commit | 4c56c54a700d166b86e2989f89d190d49305b8ed (patch) | |
| tree | 509f406bc7b77bbb15a55dfc3d5a7538ecbac9be /meta-xilinx-core/dynamic-layers/meta-python | |
| parent | 7f2930eaaf420388a45bd87c65208ecbcf46fe38 (diff) | |
| download | meta-xilinx-4c56c54a700d166b86e2989f89d190d49305b8ed.tar.gz | |
embeddedsw : Updated SRCREV for 2024.1_5919
lib: sw_apps: OpenAMP Demos: sdt: Streamline app-create step
intc: Initialize IVAR register based on mtvec in case of Microblaze RISC-V
bsp: riscv: Initialize mtvec with _trap_handler at start of boot code
bsp: riscv: Add constructor to initailize mtvec with _trap_handler
lib: bsp: arm: Dont invoke XTime_StartTTCTimer() if xiltimer library is enabled
xxvethernet: Add support for compiling driver examples in yocto flow
sw_apps: img_rcvry: Clean up
sw_apps: img_rcvry: update the imgrcvry template app to support vitisng flow.
clk_wiz: Add support for compiling driver examples in Yocto flow
i3cpsx: Update the compatible
i3cpsx: Update the base address
i3cpsx: Add prints under debug
i3cpsx: Add support for compiling driver examples in Yocto flow
Diffstat (limited to 'meta-xilinx-core/dynamic-layers/meta-python')
0 files changed, 0 insertions, 0 deletions