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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-10-09 07:43:10 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-10-09 08:27:09 +0530 |
| commit | e7c3ab2db7f7148e3f2eacb7b80d0280d5329904 (patch) | |
| tree | 99cfbbde5cabeae4218f22e832f28f3e7a39c6bf /meta-xilinx-core/dynamic-layers/virtualization-layer | |
| parent | c3b5c8d40a5a53ff8f223052fc91088bd7fcbb61 (diff) | |
| download | meta-xilinx-e7c3ab2db7f7148e3f2eacb7b80d0280d5329904.tar.gz | |
u-boot-xlnx : Updated SRCREV for 2024.2_7131
arm64: versal2: Correct the UFS clock values
xilinx: common: fix script address for Microblaze
arm64: xilinx: Fix file location described in zynqmp-p-a2197-00-revA.dts
arm64: versal: Describe EEPROM on i2c on vek280
arm64: versal: Wire USB0 in distro boot
arm64: versal: Remove description for USB1
Diffstat (limited to 'meta-xilinx-core/dynamic-layers/virtualization-layer')
0 files changed, 0 insertions, 0 deletions