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authorNava kishore Manne <nava.kishore.manne@amd.com>2024-03-08 14:16:49 +0530
committerMark Hatle <mark.hatle@amd.com>2024-03-11 11:05:39 -0500
commit5599da1f076e660617783d1838aa8985ba035299 (patch)
tree76fd22dbc12a7c1117a7a46552d8e38425aabe59 /meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c
parent7a52d1c22001e98471229aff49b3a7bc29271aab (diff)
downloadmeta-xilinx-5599da1f076e660617783d1838aa8985ba035299.tar.gz
fpgautil: Add proper validation checks for the user params
Add proper validation checks for the user inputs(bitstream and Overlay files) and it also updates the error handling logic to provide the proper error messages. Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
Diffstat (limited to 'meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c')
-rw-r--r--meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c36
1 files changed, 34 insertions, 2 deletions
diff --git a/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c b/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c
index 04777a91..281e1828 100644
--- a/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c
+++ b/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c
@@ -1,7 +1,7 @@
1/****************************************************************************** 1/******************************************************************************
2 * 2 *
3 * Copyright (C) 2019-2022 Xilinx, Inc. All rights reserved. 3 * Copyright (C) 2019-2022 Xilinx, Inc. All rights reserved.
4 * Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved. 4 * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy of 6 * Permission is hereby granted, free of charge, to any person obtaining a copy of
7 * this software and associated documentation files (the "Software"), to deal in 7 * this software and associated documentation files (the "Software"), to deal in
@@ -75,6 +75,20 @@ int fpga_getplatform()
75 75
76} 76}
77 77
78static bool file_exists(const char *filename)
79{
80 FILE *fp = fopen(filename, "r");
81 bool is_exist = false;
82
83 if (fp != NULL)
84 {
85 is_exist = true;
86 fclose(fp); // close the file
87 }
88
89 return is_exist;
90}
91
78void print_usage(char *prg) 92void print_usage(char *prg)
79{ 93{
80 int iszynqmp = fpga_getplatform(); 94 int iszynqmp = fpga_getplatform();
@@ -252,6 +266,12 @@ int main(int argc, char **argv)
252 struct stat sb; 266 struct stat sb;
253 double time; 267 double time;
254 struct timeval t1, t0; 268 struct timeval t1, t0;
269 uid_t euid = geteuid();
270
271 if (euid) {
272 printf("Error: This binary requires root access to execute. \n");
273 return 0;
274 }
255 275
256 if (argc == 1) { 276 if (argc == 1) {
257 print_usage(basename(argv[0])); 277 print_usage(basename(argv[0]));
@@ -262,10 +282,18 @@ int main(int argc, char **argv)
262 switch (opt) { 282 switch (opt) {
263 case 'o': 283 case 'o':
264 overlay = optarg; 284 overlay = optarg;
285 if (!file_exists(overlay)) {
286 printf("Error: User provided Overlay file doesn't exist\r\n");
287 return 1;
288 }
265 flow = OVERLAY; 289 flow = OVERLAY;
266 break; 290 break;
267 case 'b': 291 case 'b':
268 binfile = optarg; 292 binfile = optarg;
293 if (!file_exists(binfile)) {
294 printf("Error: User provided bitstream file doesn't exist\r\n");
295 return 1;
296 }
269 if (!(flow == OVERLAY)) 297 if (!(flow == OVERLAY))
270 flow = FPGA_SYSFS; 298 flow = FPGA_SYSFS;
271 break; 299 break;
@@ -415,7 +443,11 @@ int main(int argc, char **argv)
415 if (binfile != NULL) { 443 if (binfile != NULL) {
416 if (!fpga_state()) { 444 if (!fpga_state()) {
417 printf("Time taken to load BIN is %f Milli Seconds\n\r", time); 445 printf("Time taken to load BIN is %f Milli Seconds\n\r", time);
418 printf("BIN FILE loaded through FPGA manager successfully\n\r"); 446 if (ret) {
447 printf("BIN FILE loaded through FPGA manager successfull but failed to apply Overlay\n\r");
448 } else {
449 printf("BIN FILE loaded through FPGA manager successfully\n\r");
450 }
419 } else { 451 } else {
420 printf("BIN FILE loading through FPGA manager failed\n\r"); 452 printf("BIN FILE loading through FPGA manager failed\n\r");
421 } 453 }