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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-03-09 12:47:03 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-03-09 14:17:10 +0530 |
| commit | eeec7d93fbb5b8fd96cb8eb53caac4145ae496b1 (patch) | |
| tree | 1cf72d0a62f8293719c77091e3815dc41e6a83e2 /meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c | |
| parent | 235acbf7263b35d5662ad27aec56fcfb5643cea0 (diff) | |
| download | meta-xilinx-eeec7d93fbb5b8fd96cb8eb53caac4145ae496b1.tar.gz | |
dts : Updated SRCREV for 2024.1_2415
vpk180: Place default memory of 8Gb for DDR2
Diffstat (limited to 'meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c')
0 files changed, 0 insertions, 0 deletions