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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-03-11 12:55:58 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-03-11 14:47:10 +0530 |
| commit | a3ab3824dc3127fe1a9f03e2b6156e2deab7c923 (patch) | |
| tree | dd8fe46c466e36f021819630e2a88d5515b2bd87 /meta-xilinx-core/recipes-bsp/fpga-manager-script/fpga-manager-script_1.0.bb | |
| parent | e154cddc779703125bcd144716dea61e12cc96e9 (diff) | |
| download | meta-xilinx-a3ab3824dc3127fe1a9f03e2b6156e2deab7c923.tar.gz | |
embeddedsw : Updated SRCREV for 2024.1_7755
xilsem: Fixed IPI notification for SDT flow.
openamp: apps: Enable DDR sections to be configured from command line
xilplmi: Corrected debug level XilSEM options for VP1902 device.
xilsem: Enable XilSEM macros for VP1902 device.
lib: bsp: standalone: Add examples in yaml file
lib: bsp: standalone: Fix xil_nested_interrupts_example compilation error
ipipsu: Add Doxygen fixes
sw_services:xilplmi:Modification is done to consider error in S-SLR PMC CDO
Diffstat (limited to 'meta-xilinx-core/recipes-bsp/fpga-manager-script/fpga-manager-script_1.0.bb')
0 files changed, 0 insertions, 0 deletions