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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-06-05 18:19:55 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-06-05 19:47:11 +0530 |
| commit | 219d51b5d9db753513f5e3a47d3e56bb4919ef71 (patch) | |
| tree | 2521ed76ed630d20f0404b292cf783df6bfcbd90 /meta-xilinx-standalone | |
| parent | 1b1d8ace9cef0af0251554ca7cea1dbc032a09d9 (diff) | |
| download | meta-xilinx-219d51b5d9db753513f5e3a47d3e56bb4919ef71.tar.gz | |
Updated SRCREV of embeddedsw for 2023.2_2463
sw_services: xilpuf: Check if IRO frequency update is required
sw_services:xilocp:Fix circular buffer issues during HWPCR logging
xilplmi:Fixed doxygen warnings
lib: bsp: standalone: Document the PM_IOCTL API version bumpup changes
sw_services: xilpm: versal: Zeroization of AIE2 data memory separately
sw_services: xilpm: versal: Zeroization of AIE1 data memory separately
sw_services: xilpm: versal: Zeroization of AIE data memory separately.
qspipsu: Fix code format issue
qspipsu: Update sector calculation logic
sw_services: xilnvm: Support to read HWTSTBITS_DIS and PMC_SC_EN bits
sw_services: xilcert: Modified logic for storing user configuration
ttcps: Update check for MatchValue and IntervalValue as per platform
ttcps: Fix code formatting issues with checkpatch
emacps: example: Add Clock settings to Versal Net
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
Diffstat (limited to 'meta-xilinx-standalone')
| -rw-r--r-- | meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index cd338ab3..3efd09cd 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | |||
| @@ -8,7 +8,7 @@ ESW_BRANCH[2023.2] = "master-next" | |||
| 8 | BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" | 8 | BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" |
| 9 | 9 | ||
| 10 | ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab" | 10 | ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab" |
| 11 | ESW_REV[2023.2] = "b236be2782cc4141990094eed6df790beb0c0e2b" | 11 | ESW_REV[2023.2] = "767bd3ffb64dff29e47f5b632be8a17f9552d4c7" |
| 12 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" | 12 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" |
| 13 | 13 | ||
| 14 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" | 14 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" |