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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-03-26 06:15:12 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-03-26 07:57:10 +0530 |
| commit | ab62f0fee94ea4f8525b0eb7033a2cca7e19e1c9 (patch) | |
| tree | 5e92df87d8f27a1bc7d38d7a0798c55b03d7c507 /meta-xilinx-standalone | |
| parent | 947bbd44982a6940654d2b6ae077dadc0e37fe99 (diff) | |
| download | meta-xilinx-ab62f0fee94ea4f8525b0eb7033a2cca7e19e1c9.tar.gz | |
embeddedsw : Updated SRCREV for 2024.1_5291
trafgen: Add SDT check to use interrupt wrapper API
wdttb: Add SDT check to use interrupt wrapper API
uartpsv: Add SDT check to use interrupt wrapper API
uartps: Add SDT check to use interrupt wrapper API
gpio: Add SDT check to use interrupt wrapper API
clk_wiz: Add SDT check to use interrupt wrapper API
axipmon: Add SDT check to use interrupt wrapper API
bsp: standalone: Remove 64bit variable prints support for 32bit platforms
cpu_cortexr5: Export flag to identify R5 FSBL BSP
xloader:versal_net Remove releasing DDR from update psm.elf
emacps: Update driver for emacps+pcspma design in SDT flow
emacps: Add additional SDT check to XCLOCKING macro
lwip : Enable dhcp and acd debug flags in lwip stack
lwip : Add ACD Feature in Classic flow
lwip : Add ACD Feature in sdt flow.
xilpm: versal_common: server: Refactor of AddRequirement()
xilpm: versal_net: server: add check for UART instances
sw_services: xilsecure: Add support for non-word aligned data
i3c: Correct maximum data length value
i3c: Add Tx FIFO threshold configuration parameter
i3c: Add SCL configuration support
ttcps: Add examples support in SDT flow.
lwip220: Fix support for emaclite in lwip adapter in SDT flow
sw_services: xilpm: Refactor PGGS/GGS ioctl read/write operation checks
lib: sw_apps: memory_tests: Add required_mem for Zynq platform
scripts: pyesw: library_utils: Fix remove library for windows platform
scripts: pyesw: library_utils: Fix race condition in the remove library
Diffstat (limited to 'meta-xilinx-standalone')
| -rw-r--r-- | meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 31ceb018..ce9e81a7 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | |||
| @@ -13,7 +13,7 @@ BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" | |||
| 13 | ESW_REV[git] = "${AUTOREV}" | 13 | ESW_REV[git] = "${AUTOREV}" |
| 14 | ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" | 14 | ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" |
| 15 | ESW_REV[2023.2] = "e847e1935dca630615e5f7dc694365a44b89699c" | 15 | ESW_REV[2023.2] = "e847e1935dca630615e5f7dc694365a44b89699c" |
| 16 | ESW_REV[2024.1] = "e09e622affce82f87c5ee3204e066eddc93814bd" | 16 | ESW_REV[2024.1] = "10dd5c32b1f61b8d70b60ddf41768687080ad37c" |
| 17 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or 'INVALID'}" | 17 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or 'INVALID'}" |
| 18 | 18 | ||
| 19 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" | 19 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" |