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| author | Nathan Rossi <nathan.rossi@xilinx.com> | 2014-04-04 15:38:45 +1000 |
|---|---|---|
| committer | Nathan Rossi <nathan.rossi@xilinx.com> | 2014-04-04 15:38:45 +1000 |
| commit | e4e3a69341531350964d51b9d6b44578ed8f9c69 (patch) | |
| tree | 91dca1d673221c4b5ce27d96270814715eb0ad0b /recipes-devtools/qemu/files/hw-net-xilinx_axienet.c-Add-phy-soft-reset-bit-clear.patch | |
| parent | ba55c84cd0bd5df3f6a55c3b5b4604f46a41d8d5 (diff) | |
| download | meta-xilinx-e4e3a69341531350964d51b9d6b44578ed8f9c69.tar.gz | |
zynq-7-base.dtsi: Update base dts for zynq
* Add missing clocking properties to various devices
* Add additional compatible strings for various devices
* Fix up some missing interrupt information
* Update the slcr node
Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
Diffstat (limited to 'recipes-devtools/qemu/files/hw-net-xilinx_axienet.c-Add-phy-soft-reset-bit-clear.patch')
0 files changed, 0 insertions, 0 deletions