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The tune files were really soc configuration files. Tune files should
only specify toolchain flags that affect optimiation and abi.
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
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Using the optimized tune file (tune-cortexa72-cortexa53.inc) instead of
armv8a tune for versal and zynqmp.
Also changing DEFAULTTUNE from aarch64 to cortexa72-cortexa53 as
otherwise it was taking aarch64, the first declared default
Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com>
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
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Rename include file from arch-armv8.inc -> arch-armv8a.inc
Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
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Set default SOC_VARIANT for all versal machines as s80.
Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
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Add tune file supporting versal devices.
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
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