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* meta-xilinx-bsp: Rename soc configuration masquerading as a tune fileMark Hatle2020-03-131-18/+0
| | | | | | | The tune files were really soc configuration files. Tune files should only specify toolchain flags that affect optimiation and abi. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Using tune-cortexa72-cortexa53.inc for versal and zynqmp tunesJaewon Lee2020-01-221-2/+2
| | | | | | | | | | | Using the optimized tune file (tune-cortexa72-cortexa53.inc) instead of armv8a tune for versal and zynqmp. Also changing DEFAULTTUNE from aarch64 to cortexa72-cortexa53 as otherwise it was taking aarch64, the first declared default Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com> Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
* tune-zynqmp.inc: Use arch-armv8a tune instead of arch-armv8Manjukumar Matha2019-03-041-1/+1
| | | | | | Use the updated arch-armv8a tune instead of the old tune file Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
* tune-zynqmp.inc: Set default SOC_VARIANT to egVineeth Chowdary Karumanchi2018-06-111-0/+7
| | | | | | | | | | | | | | | | | | | | | UltraScale MPSoC is shipped in 3 device variants. https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html#productTable Available SOC_VARIANT's for zynqmp: "cg" - Zynq UltraScale+ CG Devices "eg" - Zynq UltraScale+ EG Devices (MALI 400) "ev" - Zynq UltraScale+ EV Devices (MALI 400 + VCU) This will extend MACHINEOVERRIDES for each device variant as: cg --> zynqmpcg eg --> zynqmpeg ev --> zynqmpev This patch sets the default value of SOC_VARIANT to eg. This can be overriden in machine configuration to match the intended FPGA device. Signed-off-by: Vineeth Chowdary Karumanchi <vineethchowz.chowdary@xilinx.com> Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
* meta-xilinx: Restructuring meta-xilinx to support multiple layersManjukumar Matha2017-12-131-0/+11
As discussed previously on mailing list, we are proceeding with layer restructuring. For rocko release we will have the following layers meta-xilinx ->meta-xilinx-bsp (current meta-xilinx) ->meta-xilinx-contrib In the subsequent releases we will add other layers from Xilinx meta-xilinx ->meta-xilinx-bsp (current meta-xilinx) ->meta-petalinux ->meta-xilinx-tools ->meta-xilinx-contrib This will provide one clone to get all the required meta layers from Xilinx for a complete solution, and the users can blacklist any layer which they don't want to use using bblayer.conf. This will enables us to help our vendors/partners to add their reference designs, board definitions etc. Recipe changes : * Move reference design zybo-linux-bd.bb to meta-xilinx-contrib * Move kernel patches realted to zybo-linux-bd-zynq7 board to meta-xilinx-contrib * Update README Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>