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* various: Remove SOC_VARIANT, split versal and versal-net, add machine_featuresMark Hatle2024-11-211-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | SOC_VARIANT has been remove, we are now only using the YP standard SOC_FAMILY configuration. The defined families are: zynq, zynqmp, versal and versal-net. Our decision of breaking up versal-net from versal, is based on the SoC CPU changes from cortexa72/r5 to cortexa78/r52, thus we're treating it as a different SoC family. In order to capture the individual capabilities that we used to handle via SOC_VARIANT, we have defined the following features (some may have been previously defined): - mali400 (zynqmp eg and ev) - vcu (zynqmp ev) - rfsoc (zynqmp dr RF capabiltiies) - aie - (versal ai & premium) - vdu - (versal ai) SOC_VARIANT_ARCH and SOC_FAMILY_ARCH are now obsolete and replaced by MACHINE_ARCH. This is based on the guideline that any recipes that use MACHINE_FEATURES should be MACHINE_ARCH specific. Signed-off-by: Mark Hatle <mark.hatle@amd.com>
* Initial restructure/split of meta-xilinx-bspMark Hatle2022-01-141-0/+10
Create a new meta-xilinx-core, move core functionality to the core, keeping board specific files in the bsp layer. zynqmp-generic changed from require <board> to include, so if meta-xilinx-bsp is not available it will not fail. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>