| Commit message (Collapse) | Author | Age | Files | Lines |
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iio: adc: versal-sysmon: Redefine HBM temperature channel
iio: adc: versal-sysmon: Adds oversampling/averaging feature sets
iio: adc: versal-sysmon: Macro definition change for reusability
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misc: xilinx_puf: Cleanup platform device resource on module exit
crypto: xilinx/zynqmp-aes-gcm: Fix return error code of GCM decrypt operation
Reapply "dt-bindings: Add binding for IDT 8T49N24x UFT"
PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver
dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge
net: axienet: Add support for DCMAC ethernet IP
dt-bindings: net: xlnx,axi-ethernet: Add bindings for DCMAC
net: axienet: Add gt_reset hook in struct axienet_config to reset GT
net: axienet: Rename MRMAC specific reset delay macro to generic one
net: phylink: Add phy interfaces 100Gbase-r, 200Gbase-r and 400Gbase-r
net: phy: Add phy interfaces 100Gbase-r, 200Gbase-r and 400Gbase-r
arm64: xilinx: Remove current-speed property from pl011
arm64: versal-net: add OSPI reset gpio for VNX board
usb: dwc3: core: Prevent phy suspend during init
xilinx-ecdsa: Export ASN decoding function from ecdsa module
crypto: xilinx: Cleanup platform device resource on module exit
phy: xilinx: phy-zynqmp: Fix SGMII linkup failure on resume
irqchip: xilinx: adopt clock support
staging: tsmux: Fix module autoloading
gpio: zynqmp-modepin: Fix module autoloading
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net: axienet: Deprecate xlnx,mrmac-rate and switch to generic max-speed binding
dt-bindings: net: xlnx,axi-ethernet: Use "max-speed" device tree property
arm64: xilinx: Enable UFS, ARM SCMI in default config
ufs: amd-versal2: Disable AUTO_HIBERN8 and HS modes
ufs: amd-versal2: Add AMD Versal Gen 2 UFS support
ufs: core: Add vendor specific ops to handle interrupts
firmware: xilinx: Add UFS interface API support for Versal Gen 2
dt-bindings: ufs: amd-versal2: Add support for AMD Versal Gen 2 UFS
edac: xilsem: Add error event handling support for Versal NET platform
dmaengine: zynqmp_dma: Add support for AMD Versal Gen 2 DMA IP
dt-bindings: dmaengine: zynqmp_dma: Add a new compatible string
staging: xilinx-tsn: Add Endpoint Packet Switch Feature and Control Frame Handling for STP/LLDP
dt-bindings: staging: xilinx_tsn_ep_ex: Deprecate packet-switch property
dt-bindings: staging: xilinx_tsn_ep: Add Endpoint Packet Switch support
arm64: configs: Enable CRYPTO_DEV_XILINX_ECDSA by default
crypto: xilinx: Add NIST P-521 curve support in ECDSA Driver
remoteproc: zynqmp_r5: Update power domains property to power-domains
crypto: x509 - Add OID for NIST P521 and extend parser for it
crypto: asymmetric_keys - Adjust signature size calculation for NIST P521
crypto: ecdsa - Register NIST P521 and extend test suite
crypto: ecdsa - Rename keylen to bufsize where necessary
crypto: ecdsa - Replace ndigits with nbits where precision is needed
crypto: ecc - Add NIST P521 curve parameters
crypto: ecc - Add special case for NIST P521 in ecc_point_mult
crypto: ecc - Implement vli_mmod_fast_521 for NIST p521
crypto: ecc - Add nbits field to ecc_curve structure
crypto: ecdsa - Extend res.x mod n calculation for NIST P521
crypto: ecdsa - Adjust tests on length of key parameters
crypto: ecdsa - Convert byte arrays with key coordinates to digits
crypto: ecc - Use ECC_CURVE_NIST_P192/256/384_DIGITS where possible
i2c: cadence: Add atomic transfer support for controller version 1.4
i2c: cadence: Split cdns_i2c_master_xfer for Atomic Mode
i2c: cadence: Relocate cdns_i2c_runtime_suspend and cdns_i2c_runtime_resume to facilitate atomic mode
i2c: cadence: remove printout on handled timeouts
i2c: cadence: Add system suspend and resume PM support
misc: xilinx-ai-engine: Add condition compilation flag
irqchip/xilinx: Fix shift out of bounds
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This reverts commit 110ab8cc450c4a17b5b62ceb96fd0bd8a0364e3d.
Triggers a problem booting Kria boards. Reverting until we can understand why.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Jonathan Stroud <jonathan.stroud@amd.com>
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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net: axienet: Deprecate xlnx,mrmac-rate and switch to generic max-speed binding
dt-bindings: net: xlnx,axi-ethernet: Use "max-speed" device tree property
arm64: xilinx: Enable UFS, ARM SCMI in default config
ufs: amd-versal2: Disable AUTO_HIBERN8 and HS modes
ufs: amd-versal2: Add AMD Versal Gen 2 UFS support
ufs: core: Add vendor specific ops to handle interrupts
firmware: xilinx: Add UFS interface API support for Versal Gen 2
dt-bindings: ufs: amd-versal2: Add support for AMD Versal Gen 2 UFS
edac: xilsem: Add error event handling support for Versal NET platform
dmaengine: zynqmp_dma: Add support for AMD Versal Gen 2 DMA IP
dt-bindings: dmaengine: zynqmp_dma: Add a new compatible string
staging: xilinx-tsn: Add Endpoint Packet Switch Feature and Control Frame Handling for STP/LLDP
dt-bindings: staging: xilinx_tsn_ep_ex: Deprecate packet-switch property
dt-bindings: staging: xilinx_tsn_ep: Add Endpoint Packet Switch support
arm64: configs: Enable CRYPTO_DEV_XILINX_ECDSA by default
crypto: xilinx: Add NIST P-521 curve support in ECDSA Driver
remoteproc: zynqmp_r5: Update power domains property to power-domains
crypto: x509 - Add OID for NIST P521 and extend parser for it
crypto: asymmetric_keys - Adjust signature size calculation for NIST P521
crypto: ecdsa - Register NIST P521 and extend test suite
crypto: ecdsa - Rename keylen to bufsize where necessary
crypto: ecdsa - Replace ndigits with nbits where precision is needed
crypto: ecc - Add NIST P521 curve parameters
crypto: ecc - Add special case for NIST P521 in ecc_point_mult
crypto: ecc - Implement vli_mmod_fast_521 for NIST p521
crypto: ecc - Add nbits field to ecc_curve structure
crypto: ecdsa - Extend res.x mod n calculation for NIST P521
crypto: ecdsa - Adjust tests on length of key parameters
crypto: ecdsa - Convert byte arrays with key coordinates to digits
crypto: ecc - Use ECC_CURVE_NIST_P192/256/384_DIGITS where possible
i2c: cadence: Add atomic transfer support for controller version 1.4
i2c: cadence: Split cdns_i2c_master_xfer for Atomic Mode
i2c: cadence: Relocate cdns_i2c_runtime_suspend and cdns_i2c_runtime_resume to facilitate atomic mode
i2c: cadence: remove printout on handled timeouts
i2c: cadence: Add system suspend and resume PM support
misc: xilinx-ai-engine: Add condition compilation flag
irqchip/xilinx: Fix shift out of bounds
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Add initial version of recipe for building HDMI v2.1 FMC module
Signed-off-by: Rajesh Gugulothu <rajesh.gugulothu@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Revert "arm64: xilinx: Enable SMMU by default"
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Upstream poky/oe-core contains the exact same recipe. Remove the local one and
let upstream maintain it.
Signed-off-by: Trevor Woerner <trevor.woerner@amd.com>
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
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Revert "irqchip: gic: Add changes to handle SGI for Zynq Remoteproc driver"
Revert "irqchip: gic: Add remoteproc changes to the driver"
staging: xilinx-tsn: fix kernel crash when new bridge if is created
dma: xilinx_dpdma: Fix locking
Revert "dmaengine: xilinx: dpdma: Fix race condition in vsync IRQ"
EDAC/synopsys: Fix error injection on Zynq UltraScale+
remoteproc: zynq: remove openamp support for Zynq-7000
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clk: idt: Fix incompatible function pointer types error
mailbox: zynqmp-ipi: Make polling period configurable
drm: xlnx: Fix DRM_XLNX_HDCP configuration
ASoC: xilinx: Add missing module descriptions
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Changelog:
dmaengine: xilinx: dpdma: removed extra vchan lock
arm64: zynqmp: Fix pwm-fan polarity
arm64: versal-net: Enable sysmon for VN-P-B2197 revA board
Revert "Revert "clk: Add ccf driver for IDT 8T49N24x UFT""
firmware: xilinx: Fix buffer overflow in config_reg_store
v4l: xilinx: isppipeline: Add support for ISP-ENABLE and restructure xisp_dev to resolve pahole issues
v4l: xilinx: isppipeline: Add support for RESIZE
v4l: xilinx: isppipeline: Add support for MEDIAN
v4l: xilinx: isppipeline: Add support for CLAHE
v4l: xilinx: isppipeline: Add support for RGB STATS
v4l: xilinx: isppipeline: Add support for LUMA STATS
v4l: xilinx: isppipeline: Add support for BAYER STATS
v4l: xilinx: isppipeline: Add support for CSC
v4l: xilinx: isppipeline: Add support for 3DLUT
v4l: xilinx: isppipeline: Add support for Tone mapping
v4l: xilinx: isppipeline: Add support for HDR
v4l: xilinx: isppipeline: Add support for GAMMA CORRECTION
v4l: xilinx: isppipeline: Add support for Gain Control
v4l: xilinx: isppipeline: Add support for CCM
v4l: xilinx: isppipeline: Add support for DEMOSAIC
v4l: xilinx: isppipeline: Add support for LSC
v4l: xilinx: isppipeline: Add support for RGBIR
v4l: xilinx: isppipeline: Add support for DEGAMMA
v4l: xilinx: isppipeline: Add support for BPC
v4l: xilinx: isppipeline: Add support for AWB
v4l: xilinx: isppipeline: Add support for BLC
v4l: xilinx: isppipeline: Add support for AEC
v4l: xilinx: isppipeline: Add compatible string for v2.0
dt-bindings: media: xilinx: Add documentation for ISP-2.0
usb: misc: usb5744: Increase post reset delay
arm64: xilinx: Enable SMMU by default
include: linux: firmware: correct versal-net sw error event masks
usb: dwc3: Export symbol dwc3_host_wakeup_register/capable
firmware: xilinx: fix feature check logic for TF-A specific APIs
arm64: zynqmp: dts: Add rts delay property for rs485 mode on KD240
drivers: iio: adc: xilinx-ams: Add module description
arm64: dts: zynqmp: zcu106a: Remove dpcon node
v4l: xilinx: isppipeline: Fix comment around Red Gain
phy: xilinx-xhdmiphy: Add support for selection of PLL/MMCM clock primitive
dt-bindings: phy: v-hdmi-phy1: Add dt entries for Tx/Rx clock primitives
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
(cherry picked from commit 1ab38403e91e5cfdf08852c06e5583f707aa53c1)
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Updated commit ID to latest HEAD
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Updated commit ID to latest HEAD
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Updated commit ID to latest HEAD
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Updated commit ID to latest HEAD
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Updated commit ID to latest HEAD
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SOC_VARIANT has been remove, we are now only using the YP standard SOC_FAMILY
configuration. The defined families are: zynq, zynqmp, versal and versal-net.
Our decision of breaking up versal-net from versal, is based on the SoC CPU
changes from cortexa72/r5 to cortexa78/r52, thus we're treating it as a
different SoC family.
In order to capture the individual capabilities that we used to handle via
SOC_VARIANT, we have defined the following features (some may have been
previously defined):
- mali400 (zynqmp eg and ev)
- vcu (zynqmp ev)
- rfsoc (zynqmp dr RF capabiltiies)
- aie - (versal ai & premium)
- vdu - (versal ai)
SOC_VARIANT_ARCH and SOC_FAMILY_ARCH are now obsolete and replaced by
MACHINE_ARCH. This is based on the guideline that any recipes that use
MACHINE_FEATURES should be MACHINE_ARCH specific.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Create a new layer containing all code related to the Mali400 graphics
stack and software. This includes the Mali kernel module / patches,
libglu/libgles code, mesa, wayland, kernel recipe and udev rules. This
layer also includes a dynamic layer for the qt5 bbappends and patches.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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There is no need for multiple versions, the latest version should work with
all of the kernels we care about. Version has been adjusted to 6.1.60 to
indicate the latest kernel it was actively tested with.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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There is no need for multiple versions, the latest version will work with
all of the kernels we care about. Version has been adjusted to 6.1.60 to
indicate the latest kernel it was actively tested with.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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The recipe version is now 'major.minor_vivado'. In the future we may
drop the vivado component and just stay with major_minor. But this sets
us up to make that change easier in the future.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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SRCPV is no longer needed, Simply various usages.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Jonathan Stroud <jonathan.stroud@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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drivers: crypto: xilinx: Add support for do_one_request
mtd: spi-nor: gigadevice: Disable 16bit SR operation for gd25lx256e flash
mtd: spi-nor: Fix RX tuning failure for OSPI flashes connected in stacked mode
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drivers: crypto: xilinx: Fix the request size
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phy: xilinx-xhdmiphy: Add support for FRL 6G 3-lane mode
phy: xilinx-xhdmiphy: Fix bug in xhdmiphy_rpll_param function
phy: xilinx-xhdmiphy: Fix configuring retimer chip in HDMI 2.1 mode
phy: xilinx-xhdmiphy: Clear all the config flags after being served
phy: xilinx-xhdmiphy: Select FRL clock source after configuring in HDMI 2.1 mode
firmware: xilinx: Fix feature check for crypto drivers
usb: udc: remove warning when queue disabled ep
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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misc: rsmu: add rsmu cdev driver
ptp: 82p33: move register definitions out of ptp folder
mfd: rsmu: add FemtoClock3 support
mfd: rsmu: support I2C SMBus access
ptp: clockmatrix: move register and firmware related definition to idt8a340_reg.h
ptp: clockmatrix: Fix caps.max_adj to reflect DPLL_MAX_FREQ_OFFSET[MAX_FFO]
ptp: clockmatrix: dco input-to-output delay is 20 FOD cycles + 8ns
ptp: clockmatrix: set write phase timer to 0 when not in PCW mode
ptp: clockmatrix: support 32-bit address space
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drivers: mailbox: handle SGI for shared IPI
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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microblaze: Change TLB mapping and free space allocation
arm64: versal-net Add dcc node and dcc in aliases for versal-net-ipp-rev1.9.dts
arm64: zynqmp: Disable Tri-state for SDIO
arm64: dts: zynqmp: make hw-ecc as the default ecc mode
mailbox: zynqmp: Enable Bufferless IPI usage on Versal-based SOCs
mailbox: zynqmp: Move buffered IPI setup to of_match selected routine
mailbox: zynqmp: Move of_match structure closer to usage
phy: xilinx-xhdmiphy: Configure retimer at FRL training linerate
video/hdmi: Add support for version 3 AVI Infoframe
phy: xilinx-xhdmiphy: Configure HDMIPHY in TMDS mode
drm: xlnx: hdmi: Set wait event flag for TMDS mode
drm: xlnx: hdmi: Fix TMDS clock calculation for RGB YUV422 YUV444 formats
phy: xilinx-xhdmiphy: Add pll-selection allowed range of values for GTYP/GTYE5
drm: xlnx: hdmi: Fix overwriting the max_frl_rate variable
drm: xlnx: hdmi: Downgrade the FRL rate when sink requests
drm: xlnx: hdmi: Fix lts2 state machine
drm: xlnx: hdmi: Implement xlnx_hdmi_frl_config function
drm: xlnx: hdmi: Implement streamdown callback function
drm: xlnx: hdmi: Add support for all FRL line rates
drm: xlnx: hdmi: Implement streamup callback function
drm: xlnx: hdmi: Implement connect callback function
drm: xlnx: hdmi: Set wait event flag in ltsp state
drm: xlnx: hdmi: Fix FRL link and video clock values
drm: xlnx: hdmi: Fix VTC macros as per the IP specification
phy: xilinx-xhdmiphy: Fix MMCM parameter values for GTYE5/GTYP
drm: xlnx: hdmi: Optimize phy configuration function calls
firmware: xilinx: Dont send linux address to get fpga config get status
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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net: axienet: Correct tx_buff size when DRE is not enabled
clk: clocking-wizard: calculate dividers fractional parts
v4l: xilinx: dprxss: Fix xhdcp1x_rx_init() function declaration
v4l: xilinx: dprxss: Fix gcc warning
staging: xilinx_hdcp: Fix gcc warning
mtd: spi-nor: Use same bit mask macro in spi & spi-nor core
Revert "drivers: clk: zynqmp: add hack to use old algorithm for divider round rate"
fpga: Fix the reset handling
remoteproc: zynqmp_r5: Clean up support for Versal NET CTCM
mtd: spi-nor: Add support for BP3 at SR bit 5
mtd: spi-nor: Use params->size for flash size info
mtd: spi-nor: Avoid writing EAR register for flashes less than 16MB
mtd: spi-nor: Use nor->info->id[0] for manufacturer id
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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v4l: xilinx: dprx: Replace irq_of_parse_and_map with platform_get_irq_byname
v4l: xilinx: dprx: Fix incorrect reconfiguration of registers
v4l: xilinx: dprx: Correct the XDPRX_DEVICE_SERVICE_IRQ_CP_IRQ_MASK macro value
soc: xilinx: Fix event notification issue for SW event node
drm: xlnx: hdcp: Remove unused variable srm_version
xen/pci: Add xen_reset_device_state function
net: phy: xilinx-gmii2rgmii: Adopt clock support
dt-bindings: net: xilinx_gmii2rgmii: Add clock support
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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