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* vcu: Version vcu componentsMark Hatle2022-09-121-50/+0
| | | | | | Only the SRCREV and BRANCH is different between version Signed-off-by: Mark Hatle <mark.hatle@amd.com>
* Updated SRCREV for 2022.2Siva Addepalli2022-06-071-1/+1
| | | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com> Signed-off-by: Mark Hatle <mhatle@xilinx.com>
* Revert "Updated SRCREV for 2022.1"Mark Hatle2022-04-061-3/+0
| | | | | | | | This reverts commit 0c6017795ba1499cb6b6aaab67a78f10a71dbdd3. Prep for 2022.2 update Signed-off-by: Mark Hatle <mhatle@xilinx.com>
* Updated SRCREV for 2022.1Siva Addepalli2022-03-131-0/+3
| | | | | | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com> Backported 2022.1 change to 2022.2 Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Initial restructure/split of meta-xilinx-bspMark Hatle2021-12-221-0/+50
Create a new meta-xilinx-core, move core functionality to the core, keeping board specific files in the bsp layer. zynqmp-generic changed from require <board> to include, so if meta-xilinx-bsp is not available it will not fail. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>