fluentbit: Enable vectorizer on riscv64

Signed-off-by: Khem Raj <raj.khem@gmail.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/conf/nonclangable.conf b/conf/nonclangable.conf
index 0bf23a7..ddd94a4 100644
--- a/conf/nonclangable.conf
+++ b/conf/nonclangable.conf
@@ -563,6 +563,10 @@ CFLAGS:append:pn-dav1d:riscv64:toolchain-clang = " -no-integrated-as"
 TOOLCHAIN_OPTIONS:append:pn-python3-numpy:riscv64:toolchain-clang = " -march=rv64gcv"
 TOOLCHAIN_OPTIONS:append:pn-python3-numpy:riscv32:toolchain-clang = " -march=rv32gcv"
 
+# git/lib/simdutf-amalgamation-5.5.0/src/simdutf/simdutf.cpp:4941:57: error: RISC-V type 'vuint16m1_t' (aka '__rvv_uint16m1_t') requires the 'zve32x' extension
+#      return __riscv_vmacc_vx_u16m1(__riscv_vsrl_vx_u16m1(v, 8, vl), 0x100, v, vl);
+TOOLCHAIN_OPTIONS:append:pn-fluentbit:riscv64:toolchain-clang = " -march=rv64gcv"
+
 # test_connectx segfaults with this option set to -fstack-protector-strong
 SECURITY_STACK_PROTECTOR:pn-lksctp-tools:toolchain-clang = ""