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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-04-15 20:12:35 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-04-15 21:57:09 +0530 |
| commit | 0b97d86d11f3defc08e23bfb09a9651bd5f25f76 (patch) | |
| tree | 3edde5cd94c5b237723889fbbc15c7a8d03fa111 | |
| parent | 9451b262ab17ffd1a42260fe51ae4d38a62d7d6c (diff) | |
| download | meta-xilinx-0b97d86d11f3defc08e23bfb09a9651bd5f25f76.tar.gz | |
embeddedsw : Updated SRCREV for 2024.1_4703
update Embedded SW license 2024.1 release
sw_services: xilfpga: Add doxygen fixes
sysmonpsu: Add Xiltimer to CMakeLists
scripts: pyesw: Enable user-driven customization of library options for xilpm
trngpsv: Update trngpsv minor version
trngpsx: Update trngpsx minor version
sw_services: xilsecure: Update minor version number to 24.1
sw_services:xilocp: Fix DME failure
sysmonpsv: Handle Secondary SLRs
sw_services:xilsecure:Fix Branch Past initialization
sw_services:xilsecure:Fix MISRA-C Rule 17.7
sw_services:xilsecure:Fix MISRA-C Rule 10.3
sw_services:xilsecure:Fix overrun issue
sw_services: xilpm: Enable the capability to adjust bsp config flags in the Rigel flow
freertos10_xilinx: Fix portPOINTER_SIZE_TYPE value for Cortex A78
scripts: pyesw: retarget_app: Add support for shared workspace use case
xilpm: versal_common: server: Add a macro to exclude USB idle code
bsp: Add macro to disable long values print support as needed
dp12txss: examples: Fix IIC Baseaddress for new unified version
dp12rxss: examples: Fix IIC Baseaddress for new unified version
xilpm: versal: NoC ScanClear workaround for xcvm2152
| -rw-r--r-- | meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 388855cc..9271bb5f 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | |||
| @@ -13,7 +13,7 @@ BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" | |||
| 13 | ESW_REV[git] = "${AUTOREV}" | 13 | ESW_REV[git] = "${AUTOREV}" |
| 14 | ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" | 14 | ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" |
| 15 | ESW_REV[2023.2] = "e847e1935dca630615e5f7dc694365a44b89699c" | 15 | ESW_REV[2023.2] = "e847e1935dca630615e5f7dc694365a44b89699c" |
| 16 | ESW_REV[2024.1] = "21678feea6c535657988b9cede10270f8bdf3695" | 16 | ESW_REV[2024.1] = "86b2c5e38d51a98e6559799a2f25dc8c72535797" |
| 17 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or 'INVALID'}" | 17 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or 'INVALID'}" |
| 18 | 18 | ||
| 19 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" | 19 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" |
| @@ -23,7 +23,7 @@ LICENSE = "MIT" | |||
| 23 | LIC_FILES_CHKSUM[master] = '9fceecdbcad88698f265578f3d4cb26c' | 23 | LIC_FILES_CHKSUM[master] = '9fceecdbcad88698f265578f3d4cb26c' |
| 24 | LIC_FILES_CHKSUM[xlnx_rel_v2023.1_update] = '3c310a3ee2197a4c92c6a0e2937c207c' | 24 | LIC_FILES_CHKSUM[xlnx_rel_v2023.1_update] = '3c310a3ee2197a4c92c6a0e2937c207c' |
| 25 | LIC_FILES_CHKSUM[xlnx_rel_v2023.2_update] = '9fceecdbcad88698f265578f3d4cb26c' | 25 | LIC_FILES_CHKSUM[xlnx_rel_v2023.2_update] = '9fceecdbcad88698f265578f3d4cb26c' |
| 26 | LIC_FILES_CHKSUM[xlnx_rel_v2024.1-next] = '9fceecdbcad88698f265578f3d4cb26c' | 26 | LIC_FILES_CHKSUM[xlnx_rel_v2024.1-next] = '443113d5aa8fd5facf31e9c5d25dc114' |
| 27 | LIC_FILES_CHKSUM ??= "file://license.txt;md5=${@d.getVarFlag('LIC_FILES_CHKSUM', d.getVar('BRANCH')) or '0'}" | 27 | LIC_FILES_CHKSUM ??= "file://license.txt;md5=${@d.getVarFlag('LIC_FILES_CHKSUM', d.getVar('BRANCH')) or '0'}" |
| 28 | 28 | ||
| 29 | SRC_URI = "${EMBEDDEDSW_SRCURI}" | 29 | SRC_URI = "${EMBEDDEDSW_SRCURI}" |