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author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-04-15 20:12:35 +0530 |
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committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-04-15 21:57:09 +0530 |
commit | 0b97d86d11f3defc08e23bfb09a9651bd5f25f76 (patch) | |
tree | 3edde5cd94c5b237723889fbbc15c7a8d03fa111 /meta-xilinx-mali400/recipes-benchmarks/files/0001-src-options.cpp-Add-options-to-configure-bpp-and-dep.patch | |
parent | 9451b262ab17ffd1a42260fe51ae4d38a62d7d6c (diff) | |
download | meta-xilinx-0b97d86d11f3defc08e23bfb09a9651bd5f25f76.tar.gz |
embeddedsw : Updated SRCREV for 2024.1_4703
update Embedded SW license 2024.1 release
sw_services: xilfpga: Add doxygen fixes
sysmonpsu: Add Xiltimer to CMakeLists
scripts: pyesw: Enable user-driven customization of library options for xilpm
trngpsv: Update trngpsv minor version
trngpsx: Update trngpsx minor version
sw_services: xilsecure: Update minor version number to 24.1
sw_services:xilocp: Fix DME failure
sysmonpsv: Handle Secondary SLRs
sw_services:xilsecure:Fix Branch Past initialization
sw_services:xilsecure:Fix MISRA-C Rule 17.7
sw_services:xilsecure:Fix MISRA-C Rule 10.3
sw_services:xilsecure:Fix overrun issue
sw_services: xilpm: Enable the capability to adjust bsp config flags in the Rigel flow
freertos10_xilinx: Fix portPOINTER_SIZE_TYPE value for Cortex A78
scripts: pyesw: retarget_app: Add support for shared workspace use case
xilpm: versal_common: server: Add a macro to exclude USB idle code
bsp: Add macro to disable long values print support as needed
dp12txss: examples: Fix IIC Baseaddress for new unified version
dp12rxss: examples: Fix IIC Baseaddress for new unified version
xilpm: versal: NoC ScanClear workaround for xcvm2152
Diffstat (limited to 'meta-xilinx-mali400/recipes-benchmarks/files/0001-src-options.cpp-Add-options-to-configure-bpp-and-dep.patch')
0 files changed, 0 insertions, 0 deletions